Apple Macbook PRO A1286 (Late 2008-Early 2009), Laptop Logic Board Schematic Diagram
January 31, 2017 | Author: juz22 | Category: N/A
Short Description
Download Apple Macbook PRO A1286 (Late 2008-Early 2009), Laptop Logic Board Schematic Diagram...
Description
8
6
7
2
3
4
5
1 CK APPD
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. 2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
REV
SCHEM,MBP 15"MLB
ZONE
ECN
ENG APPD
DESCRIPTION OF CHANGE DATE
?
?
?
?
DATE
?
08/18/2008 (.csa)
D
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 24 25 26 28 29 31 32 33 34 35 37 38 39 41 42 43 45 46 48 49 50 51 52
Date
Contents
Sync
Table of Contents System Block Diagram Power Block Diagram Power Block Diagram BOM Configuration JTAG Scan Chain Functional / ICT Test Power Aliases Signal Aliases CPU FSB CPU Power & Ground CPU Decoupling & VID eXtended Debug Port(MiniXDP) MCP CPU Interface MCP Memory Interface MCP Memory Misc MCP PCIe Interfaces MCP Ethernet & Graphics MCP PCI & LPC MCP SATA & USB MCP HDA & MISC MCP Power & Ground MCP79 A01 Silicon Support MCP Standard Decoupling MCP Graphics Support SB Misc FSB/DDR3/FRAMEBUF Vref Margining DDR3 SO-DIMM Connector A DDR3 SO-DIMM Connector B DDR3 Support Right Clutch Connector ExpressCard Connector Ethernet PHY (RTL8211CL) Ethernet & AirPort Support Ethernet Connector FireWire LLC/PHY (FW643) FireWire Port Power FireWire Ports SATA Connectors External USB Connectors Front Flex Support SMC SMC Support LPC+SPI Debug Connector M98 SMBus Connections
N/A
(.csa)
Page TABLE_TABLEOFCONTENTS_HEAD
N/A 12/12/2007
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T18_MLB 12/12/2007
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T18_MLB N/A
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N/A N/A
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N/A 07/22/2008
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DDR N/A
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N/A (MASTER)
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(MASTER) (MASTER)
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(MASTER) 10/17/2007
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M87_MLB 10/17/2007
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M87_MLB 10/17/2007
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M87_MLB 01/08/2008
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M99_MLB 06/18/2008
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T18_MLB 06/18/2008
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T18_MLB 06/18/2008
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T18_MLB 06/18/2008
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T18_MLB 06/18/2008
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T18_MLB 06/18/2008
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T18_MLB 06/18/2008
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T18_MLB 06/18/2008
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T18_MLB 06/18/2008
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T18_MLB 03/31/2008
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T18_MLB 06/18/2008
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T18_MLB 06/18/2008 AMASON_M98_MLB 12/17/2007 T18_MLB 07/22/2008 DDR 07/22/2008 DDR 07/22/2008 DDR 06/18/2008 T18_MLB 07/02/2008 YITE_M98_MLB 07/02/2008 YITE_M98_MLB 07/01/2008 SUMA_M98_MLB 07/01/2008 SUMA_M98_MLB 07/01/2008 SUMA_M98_MLB 08/14/2008 SENSOR 08/14/2008 SENSOR 08/14/2008 SENSOR 07/01/2008 CHANG_M98_MLB 07/02/2008 AMASON_M98_MLB 07/01/2008 CHANG_M98_MLB 06/18/2008 T18_MLB 06/18/2008 AMASON_M98_MLB 07/01/2008 CHANG_M98_MLB 07/22/2008 DDR
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46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
53 54 55 56 57 58 59 61 62 63 65 66 67 68 69 70 71 72 73 75 76 77 78 79 80 81 82 84 85 86 87 88 89 90 93 94 95 96 97 98 99 100 101 102 103
Date
Contents
(.csa)
Sync
Current & Voltage Sensing Current Sensing Thermal Sensors Fan Connectors WELLSPRING 1 WELLSPRING 2 Sudden Motion Sensor (SMS) SPI ROM AUDIO:CODEC AUDIO: LINE IN AUDIO: HEADPHONE AMP AUDIO:SPEAKER AMP AUDIO: JACKS AUDIO: JACK TRANSLATORS DC-In & Battery Connectors PBus Supply & Battery Charger IMVP6 CPU VCore Regulator 5V / 3.3V Power Supply 1.5V DDR3 Supply 1.05V / MCP Core Regulator CPU VTT Power Supply Misc Power Supplies Power Control Power FETs NV G96 PCI-E NV G96 Core/FB Power NV G96 Frame Buffer I/F GDDR3 Frame Buffer A (Top) GDDR3 Frame Buffer B (Top) NV G96 GPIO/MIO/Misc G96 GPIOs & Straps NV G96 Video Interfaces GPU (G84M) Core Supply LVDS Display Connector Muxed Graphics Support DisplayPort Connector 1.1V / 1V8 FB Power Supply Graphics MUX (GMUX) LCD BACKLIGHT DRIVER LCD Backlight Support Misc Power Supplies CPU/FSB Constraints Memory Constraints MCP Constraints 1 MCP Constraints 2
Page
08/14/2008
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SENSOR 08/14/2008
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SENSOR 08/14/2008
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SENSOR 10/17/2007
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M87_MLB 06/18/2008 AMASON_M98_MLB 05/12/2008 PWRSQNC 08/14/2008 SENSOR 07/01/2008 CHANG_M98_MLB 07/09/2008 AUDIO 07/09/2008 AUDIO 07/09/2008 AUDIO 07/09/2008 AUDIO 07/09/2008 AUDIO 07/09/2008 AUDIO 12/06/2007 T18_MLB 12/10/2007 M99_MLB 10/17/2007 M87_MLB 01/09/2008 M99_MLB 12/13/2007 M99_MLB 01/08/2008 M99_MLB 12/14/2007 M99_MLB 12/14/2007 M99_MLB 05/12/2008 PWRSQNC 05/12/2008 PWRSQNC 07/10/2008 MUXGFX 07/10/2008 MUXGFX 07/10/2008 MUXGFX 07/10/2008 MUXGFX 07/10/2008 MUXGFX 07/10/2008 MUXGFX 07/09/2008 MUXGFX 07/10/2008 MUXGFX 10/17/2007 M87_MLB 02/25/2008 MUXGFX 07/10/2008 MUXGFX 07/10/2008 MUXGFX 07/10/2008 MUXGFX 07/10/2008 MUXGFX 07/02/2008 YITE_M98_MLB 07/02/2008 YITE_M98_MLB 02/01/2008 MUXGFX 02/18/2008 MUXGFX 02/18/2008 MUXGFX 02/18/2008 MUXGFX 02/18/2008 MUXGFX
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91 92 93 94 95 96
104 105 106 107 108 109
Contents Ethernet Constraints FireWire Constraints SMC Constraints GPU (G96) Constraints Project Specific Constraints PCB Rule Definitions
D
Date
Sync 02/18/2008 MUXGFX 02/18/2008 MUXGFX 02/18/2008 MUXGFX 02/18/2008 MUXGFX 02/21/2008 MUXGFX 01/22/2008 M99_MLB
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C
B
TABLE_TABLEOFCONTENTS_ITEM
www.laptop-schematics.com
A
DIMENSIONS ARE IN MILLIMETERS
APPLE INC.
METRIC
XX
X.XX DRAFTER
Schematic / PCB #’s PART NUMBER
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING ENG APPD
MFG APPD
QA APPD
DESIGNER
RELEASE
SCALE
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
ANGLES
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
051-7546
1
SCHEM,FIBBO,M98
SCH
CRITICAL
820-2330
1
PCBF,FIBBO,M98
PCB
CRITICAL
A
NOTICE OF PROPRIETARY PROPERTY
DESIGN CK
X.XXX
BOM OPTION
TITLE
DO NOT SCALE DRAWING
SCHEM,MBP 15MLB NONE
DRAWING
SIZE
TITLE=MLB ABBREV=DRAWING LAST_MODIFIED=Mon Aug 18 01:48:34 2008
8
THIRD ANGLE PROJECTION
7
6
5
4
3
MATERIAL/FINISH NOTED AS APPLICABLE
D
DRAWING NUMBER
REV.
051-7546 SHT
2
1
1
A.0.0 OF
96
8
6
7
2
3
4
5
1
U1000 U1300
INTEL CPU XDP CONN
2.X OR 3.X GHZ
PG 12
PENRYN
MAIN MEMORY
FSB INTERFACE
GPIOs
2 UDIMMs DDR2-800MHZ DDR3-1067/1333MHZ
POWER SUPPLY
PG 60
J2900
DIMM
PG 14
U4900 PG 25,26
TEMP SENSOR PG 41
Misc
CLK
PG 24 U6100
SYNTH J4510
SATA Conn HD
POWER PGSENSE 45
SPI Boot ROM
SPI
J5650,5600,5610,5611,5660,5720,5730,5750
FAN CONN AND CONTROL
PG 52 1.05V/3GHZ.
PG 48,49
PG 20
PG 38
NVIDIA
J4520
SATA Conn ODD
1.05V/3GHZ.
J4900
SMC LPC
PG 19
PG 38
ADC
B,0 BSB
MCP79
SATA
Fan Ser Prt
J5100
PG 41
LPC Conn Port80,serial
C
PG 43 PG 18
U1400 J9000
PWR
LVDS CONN
CTRL
LVDS OUT PG 71
RGB OUT J4720
DP OUT
DISPLAY PORT CONN
HDMI OUT
PG 40
DVI OUT TMDS OUT
USB
PG 71
J4700
Bluetooth
PG 17
J4710
J4710
TRACKPAD/ KEYBOARD
IR
PG 40
PG 40
J3900,4635,4655
CAMERA
EXTERNAL USB Connectors
PG 40
PG 39
PG 16
0 1 2 3 4 5 6 7 8 9
J9400
PCI-E
A
DC/BATT
PG 13
UP TO 20 LANES3
B
D
J6950
800/1067/1333 MHz
PG 19
C
FSB 64-Bit
(UP TO 12 DEVICES)
D
www.laptop-schematics.com
PG 9
B SMB
SMB CONN
PG 20
RGMII
PCI
(UP TO FOUR PORTS)
HDA
PG 44
DIMM’s
PG 17 PG 18
PG 20
U6200
Audio Codec PG 53
U6301
U3700
GB E-NET
U6400
Line In Amp
88E1116
PG 54
U6500
HEADPHONE Amp
Line Out Amp
Speaker Amps
PG 56
PG 57
PG 55
System Block Diagram
U6600,6605,6610,6620
SYNC_MASTER=T18_MLB
SYNC_DATE=12/12/2007
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
PG 31
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE J3400
U3900
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
Mini PCI-E AirPort
J6800,6801,6802,6803
E-NET Conn
Audio Conns
PG 28
SIZE
DRAWING NUMBER
D
PG 33 PG 59
APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
2
1
96
A
6
7
M98 POWER SYSTEM ARCHITECTURE ENABLE
PPVIN_G3H_P3V42G3H
3.425V G3HOT
D6905
PP3V42_G3H_REG LT3470 U6990 (PAGE 59)
PBUSB_VSENSE
V
8A FUSE PPVBAT_G3H_CHGR_REG
Q5315
PPBUS_G3H
V
U5705 ENABLES
6A FUSE
A
VIN
VOUT
A U5715
CPU VCORE VOUT VIN ISL9504B
U7100 IMVP_VR_ON_R VR_ON PPVBAT_G3H_CHGR_R
PGOOD
(PAGE 61) CHGR_BGATE
TPS51117 U7600 (PAG 66)
PPVCORE_GPU_REG
PGOOD
CPUVTTS0_PGOOD
GPUVCORE_PGOOD
A
RSMRST*
SMC_CPU_VSENSE
V
MCP_PS_PWRGD CPU_PWRGD PWROK CPUPWRGD(GPIO49)
PPVCORE_CPU_S0 CPUVCORE_IOUT VR_PWRGD_CLKEN_L
U1400 (PAGE 14~22)
U2850
VR_PWRGOOD_DELAY Q7920
CPU
P1V1GPU_EN EN1
VIN
VOUT1
P5VS3_EN LIO_S3_EN
SLP_S3#(G17)
U1400
P1V8FB_ENEN2
SMC
VOUT2
PP1V1_S0GPU_REG
Q7900
PP5V_S3_FET
P5VS3_SS
TPS51124 U9500 (PAGE 82)
U7859
P60 SMC_PM_G2_EN
VIN
5V
VOUT1 PP5V_S5_REG (8A MAX CURRENT)
3.3V
VOUT2
(R/H)
P3V3S5_EN VIN U7400 PP5V_RT_REG VOUT EN/PSV SC417 P5V_RT_EN (PAGE 64) P5V_RT_PGOOD ENL PGOOD
PP5V_S3
(L/H)
(S5) (PAGE 42)
(PAGE 14~22)
PP3V3_S5_REG (5.5A MAX CURRENT)
TPS51125
PP3V3_S5
PP3V3_S3_FET
(PAGE 62) PGOOD1,2VREG3 P3V3S3_SS P5V3V3_S5_PGOOD
Q7930
SMC
PP3V3_S0GPU_FET
PM_WLAN_EN_L
WOW_EN
PP1V05_S5_MCP
ISL8009 V4 U7750 (PAGE 66)
Q7910
EN0 U7201
Q3805
B
GOSHAWK6P
BKLT_EN
PM_ENET_EN
U9701
PP3V3_S0_FET
ENA VOUT (PAGE 84)
P1V2ENET_EN ENETAVDD_EN
RSMRST_PWRGD
Q7970
PPVOUT_S0_LCDBKLT
PM_ENET_EN_L
Q3800 WOL_EN PM_ENET_EN_L SMC_ADAPTER_EN
A
P1V8S0_EN RC DELAY
RC DELAY
PP1V9_ENET_REG
DDRVTT_EN
VIN
P3V3_ENET_FET PP1V2_ENET_REG
PM_SLP_S3_L
RST* SMC_RESET_L
SLP_S5_L(P95) SLP_S4_L(P94) SLP_S3_L(P93)
U4900 (PAGE 42)
RST* PP5V_S0 PP3V3_S0
V1 V2 V3 LTC2900 PP1V5_S0_REG V4 U7870
TPS51116 U7300 (PAGE 63)
(S0)
P1V8S0_PGOOD P1V5S0_PGOOD S0PGOOD_PWROK
MCP_CORE
MCPDDR_EN RC DELAY
P3V3S0_EN (S0)
MCPCORES0_EN
CPUVTTS0_EN RC DELAY
PBUSVSENS_EN (S0)
P1V05S0_EN
MCPCORES0_EN RC DELAY
PM_SLP_S3_DELAY_L
EN2
VOUT2
1.1V EN1
VOUT1
MCPCPCORE_S0_REG
Power Block Diagram SYNC_MASTER=T18_MLB
SYNC_DATE=12/12/2007
NOTICE OF PROPRIETARY PROPERTY
(PAGE 68)
(25A MAX CURRENT)
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
PP5V_RT_REG
II NOT TO REPRODUCE OR COPY IT
(5A MAX CURRENT)
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
ISL6236
VIN U7500 (PAGE 65)
(S0)
DRAWING NUMBER
D APPLE INC.
7
6
5
4
3
2
REV.
051-7546
SCALE
SHT NONE
8
B
99ms DLY
IMVP_VR_ON IMVP_VR_ON(P16) RSMRST_IN(P13) PLT_RST* PWR_BUTTON(P90) PM_PWRBTN_L P17(BTN_OUT)
VLDOIN
1.8V S5 VOUT1 PPDDR_S3_REG (12A MAX CURRENT) S3 0.9VVOUT2 PPVTT_S0_DDR_LDO
P5VS0_EN
P1V05S0_PGOOD P5VRIGHT_PGOOD MCPCORES0_PGOODPM_SLP_S5_L CPUVTTS0_PGOOD PM_SLP_S4_L
Q3810
PPVIN_S0_DDRREG_LDO
DDRREG_EN
SMC_ONOFF_L
P3V3GPU_SS
VINLTC3407 VOUT1 RUN2 U3850 (PAGE 33) RUN1 VOUT2
P3V3ENET_EN_L
P5VRIGHT_EN RC DELAY
PWRGD(P12)
VIN P3V3S0_SS
PM_SLP_S3_L
RSMRST_OUT(P15)PM_RSMRST_L
ALL_SYS_PWRGD
Q3801
PWRGOOD
U1000 (PAGE 10,11) RESET*
PP1V8_GPU_REG
1.8V(R/H)
U4900
C
PP5V_S0_FET
1.103V(L/H)
SLP_S5#(H17)
PWRBTN#
VR_PWRGD_CLKENVRMPWRGD
P5VS0_SS
MCP79
MCP79 CK_PWRGD
U2830
PPBUS_G3H
P3V3S3_EN
D
1.05V
PLTRST*PLT_RST_L
U5400
Q7055
C
PPCPUVTT_S0_REG (6A MAX CURRENT)
SMC_BATT_ISENSE
J6950
BATT_POS_F
VOUT
(PAGE 78)
ISL6258A U7000
(9 TO 12.6V)
EN_PSV
GPUVCORE_IOUT(18A MAX CURRENT)
PGOOD
(PAGE 60) LIO_DCIN_ISENSE PBUS SUPPLY/ BATTERY CHARGER
3S2P
A
GPU VCORE VOUT VIN ISL6263B U8900 PM_GPUVCORE_EN EN_PSV
CHGR_EN (S5)
VIN
CPUVTTS0_EN
SMC_GPU_VSENSE
U5498 AC DCIN(16.5V) ADAPTER IN
1
SMC PWRGD RN5VD30A-FSMC_RESET_L U5000 (PAGE 43)
D6905
D
2
3
4
5
www.laptop-schematics.com
8
A.0.0 OF
3
1
96
A
8
7
6
5
4
3
2
1
D
C
C
B
B
www.laptop-schematics.com
D
Power Block Diagram SYNC_MASTER=N/A
A
SYNC_DATE=N/A
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
4
1
96
A
8
6
7
5
4
3
2
1
BOM Variants TABLE_BOMGROUP_HEAD
BOM NUMBER
BOM NAME
BOM OPTIONS
630-9334
PCBA,2.4GHZ,256SAM_VRAM,M98
M98_COMMON,EEE_0ZA,CPU_2_4GHZ,FB_256_SAMSUNG
630-9335
PCBA,2.4GHZ,256HYN_VRAM,M98
M98_COMMON,EEE_0ZB,CPU_2_4GHZ,FB_256_HYNIX
630-9336
PCBA,2.5GHZ,512SAM_VRAM,M98
M98_COMMON,EEE_0ZC,CPU_2_5GHZ,FB_512_SAMSUNG
630-9337
PCBA,2.5GHZ,512QIM_VRAM,M98
M98_COMMON,EEE_0ZD,CPU_2_5GHZ,FB_512_QIMONDA
630-9585
PCBA,2.8GHZ,512SAM_VRAM,M98
M98_COMMON,EEE_2NH,CPU_2_8GHZ,FB_512_SAMSUNG
630-9586
PCBA,2.8GHZ,512QIM_VRAM,M98
M98_COMMON,EEE_2NJ,CPU_2_8GHZ,FB_512_QIMONDA
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
D
D
M98 BOM Groups TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
M98_COMMON
ALTERNATE,COMMON,M98_COMMON1,M98_COMMON2,M98_COMMON3,M98_DEBUG,M98_PROGPARTS
M98_COMMON1
ONEWIRE_PU,ISL6258A,MEMRESET_HW,MEMRESET_MCP,MCP_B02,MCP_PROD,MCPSEQ_SMC
M98_COMMON2
BKLT_PLL_NOT,BMON_ENG,MIKEY,BOOT_MODE_USER,GPUVID_1P00V,MUXGFX
M98_COMMON3
DPMUX_EN_S0,DP_ESD,EG_PWRSEQ_HW,DP_CA_DET_EG_PLD,MCP_CS1_NO
M98_DEBUG
SMC_DEBUG_YES,XDP,LPCPLUS,VREFMRGN
M98_PROGPARTS
GMUX_PROG,BOOTROM_PROG,SMC_PROG,TPAD_PROG
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
www.laptop-schematics.com
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
FB_256_SAMSUNG
VRAM4,VRAM_256_SAMSUNG
FB_256_HYNIX
VRAM4,VRAM_256_HYNIX
FB_512_SAMSUNG
VRAM4,VRAM_512_SAMSUNG
FB_512_QIMONDA
VRAM4,VRAM_512_QIMONDA
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
Bar Code Labels / EEE #’s C
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEE:0ZA]
CRITICAL
BOM OPTION EEE_0ZA
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEE:0ZB]
CRITICAL
EEE_0ZB
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEE:0ZC]
CRITICAL
EEE_0ZC
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEE:0ZD]
CRITICAL
EEE_0ZD
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEE:2NH]
CRITICAL
EEE_2NH
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEE:2NJ]
CRITICAL
EEE_2NJ
C
Module Parts
B
PART NUMBER
QTY
REFERENCE DES
CRITICAL
337S3639
1
IC,PDC,SLB4N,PRQ,2.4G,25W,1066,M0,3M,BGA
DESCRIPTION
U1000
CRITICAL
BOM OPTION CPU_2_4GHZ
337S3640
1
IC,PDC,SL3BX,PRQ,2.53G,35W,1066,C0,6M,BGA
U1000
CRITICAL
CPU_2_5GHZ
338S0554
1
IC,GPU,55nm,NV G96-GS,BGA969,LF
U8000
CRITICAL
338S0570
1
IC,RTL8211CL,GIGE TRANSCEIVER,48P TQFP
U3700
CRITICAL
338S0523
1
IC,FW643-06,1394B PHY/OHCI LINK/PCI-E,12
U4100
CRITICAL
338S0600
1
IC,GMCP,MCP79-B01,35x35MM,BGA1437
U1400
CRITICAL
MCP_B01
338S0563
1
IC,SMC,HS8/2117,9MMX9MM,TLP
U4900
CRITICAL
SMC_BLANK
341S2289
1
IC,SMC,DEVELOPMENT,M98
U4900
CRITICAL
SMC_PROG
335S0384
1
IC,32MBIT 8-PIN SPI SERIAL FLASH,SOIC8
U6100
CRITICAL
BOOTROM_BLANK
341S2366
1
IC,EFI ROM,DEVELOPMENT,M98
U6100
CRITICAL
BOOTROM_PROG
341S2272
1
IC,HDCP ROM,NVG96, 8 PIN SOIC,LF,HF
U8770
CRITICAL
HDCP_YES
341S2384
1
IR,ENCORE II, CY7C63803-LQXC
U4800
CRITICAL
338S0635
1
IC,GMCP,MCP79-B02,35x35MM,BGA1437
U1400
CRITICAL
MCP_B02
341S2383
1
IC,PSOC +W/USB,56PIN,MLF,M98
U5701
CRITICAL
TPAD_PROG
337S3641
1
IC,PDC,SLB43,PRQ,2.8G,35W,1066,C0,6M,BGA
U1000
CRITICAL
CPU_2_8GHZ
333S0482
4
IC,SGRAM,GDDR3,16Mx32,800MHZ,136 FBGA
U8400,U8450,U8500,U8550
CRITICAL
VRAM_256_SAMSUNG
333S0483
4
IC,SGRAM,GDDR3,16Mx32,900MHZ,136 FBGA
U8400,U8450,U8500,U8550
CRITICAL
VRAM_256_HYNIX
333S0481
4
IC,SGRAM,GDDR3,32Mx32,900MHZ,136 FBGA
U8400,U8450,U8500,U8550
CRITICAL
VRAM_512_SAMSUNG
333S0472
4
IC,SGRAM,GDDR3,32Mx32,900MHZ,136 FBGA
U8400,U8450,U8500,U8550
CRITICAL
VRAM_512_QIMONDA
B
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR PART NUMBER
138S0603
BOM OPTION
REF DES
COMMENTS:
138S0602
ALL
Murata alt to Samsung
353S1681
353S1294
ALL
LMV2011,OPAMP. GBW
152S0276
152S0683
ALL
Maglayers alt to Dale/Vishay
341S2367
341S2366
ALL
Macronix alt to SST
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
BOM Configuration
TABLE_ALT_ITEM
A
SYNC_MASTER=N/A
TABLE_ALT_ITEM
152S0876
152S0867
ALL
NOTICE OF PROPRIETARY PROPERTY
TABLE_ALT_ITEM
157S0058
157S0055
ALL
SYNC_DATE=N/A
Maglayer alt to Delta
Delta alt to TDK Magnetics
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
TABLE_ALT_ITEM
353S2312
353S1466
ALL
INTERSIL ALT TO INTERSIL
514-0612
514-0607
ALL
FOXLINK XCVR ALT TO FOXCONN
514-0613
514-0608
ALL
FOXLINK RCVR ALT TO FOXCONN
TABLE_ALT_ITEM
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT
TABLE_ALT_ITEM
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART TABLE_ALT_ITEM
152S0915
152S0796
ALL
Maglayers alt to Cyntec IND
SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
5
1
96
A
8
6
7
2
3
4
5
1
1.05V TO 3.3V LEVEL TRANSLATOR (M98: ON ICT FIXTURE) =PP3V3_S0_XDP 13 8 6
U1000 CPU
From XDP connector JTAG_ALLDEV 1
C0601 0.1UF
20% 2 10V CERM 402
JTAG_ALLDEV 1
C0602 0.1UF
20% 2 10V CERM 402
87 13 10 6
IN
87 13 10
IN
87 13 10 6
IN
87 13 10 6
IN
XDP_TCK XDP_TDI XDP_TMS XDP_TRST_L
D
To XDP connector and/or level translator
=PP1V05_S0_CPU 62 13 12 11 10 8
XDP
R0603 87 10
XDP_TDO
1
0
2
PLACEMENT_NOTE=Place near pin U1000.AB3 XDP_TDO_CONN
5% 1/16W MF-LF 402
13
OUT
XDP connector
www.laptop-schematics.com
D
JTAG_ALLDEV
R06011 1
11
10K 5% 1/16W MF-LF 402 2
From XDP connector or via level translator
VCCA VCCB
U0600
U1400 MCP
NLSV4T244
XDP_TCK
87 13 10 6
NOSTUFF 1
R0602
87 13 10 6
0
87 13 10 6
5% 1/16W MF-LF 402 2
XDP_TMS XDP_TRST_L
JTAG_LVL_TRANS_EN_L
2 3 4 5
UQFN A1 B1 A2 B2 A3 B3 JTAG_ALLDEV A4 B4
10 9 8 7
MAKE_BASE=TRUE
MAKE_BASE=TRUE
JTAG_MCP_TCK JTAG_MCP_TDI JTAG_MCP_TMS JTAG_MCP_TRST_L
13 21
XDP
13 21 23
R0604
13 21 23 13 21
21
JTAG_MCP_TDO
R0606
OE*
10K
GND
2
PLACEMENT_NOTE=Place near pin U1400.F19 JTAG_MCP_TDO_CONN
13
OUT
XDP connector
C
5% 1/16W MF-LF 2 402
6
C
0
5% 1/16W MF-LF 402
1
12
1
MAKE_BASE=TRUE
NOSTUFF
6
U8000 GPU
VCC
U0601
GPU_JTAG_TCK GPU_JTAG_TDI GPU_JTAG_TMS GPU_JTAG_TRST_L
74LVC1G07 2 A
GMUX CPLD Programming Port
1 NC
SOT886 GND
NC 5
76 75 8
=PP3V3_GPU_VDD33
1
10K
PLACEMENT_NOTE=Place close to U8000 GPU_JTAG_TMS
2
6 75
5% 1/16W MF-LF 402
75 75 6 75 75
75
GPU_JTAG_TDO
TP_GPU_JTAG_TDO MAKE_BASE=TRUE
NC
3
NC
Y 4
R0605
CRITICAL
PLACEMENT_NOTE=Place close to U0600
J0600
1909782 M-RT-SM 7
1 2 3 4
=PP3V3_S0_XDP 6 8 13
TDO TDI TMS
U9200 GMUX
5
B
6
TCK
JTAG_GMUX_TCK JTAG_GMUX_TDI JTAG_GMUX_TMS
8
B
83 9 83 9 83 83 9
JTAG_GMUX_TDO
JTAG Scan Chain
A
SYNC_MASTER=DDR
SYNC_DATE=07/22/2008
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
6
1
96
A
8
6
7
Functional Test Points
2
3
4
5
1
ICT Test Points CPU FSB NO_TESTs
Fan Connectors
NO_TEST
FUNC_TEST
D
TRUE
=PP5V_S0_FAN_LT
TRUE TRUE
FAN_LT_PWM FAN_LT_TACH
TRUE TRUE TRUE
FAN_RT_PWM FAN_RT_TACH GND
8 49
TRUE TRUE TRUE
FSB_A_L FSB_ADS_L FSB_ADSTB_L
TRUE
FSB_D_L
10 14 87
TRUE
FSB_DINV_L
10 14 87
TRUE TRUE TRUE TRUE TRUE TRUE
FSB_DSTB_L_N FSB_DSTB_L_P FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_REQ_L
10 14 87 10 14 87 10 14 87
3 TPs per Fan
D
49 49
49 49
5 TPs per Fan
10 14 87 10 14 87 10 14 87 10 14 87 10 14 87 10 14 87
www.laptop-schematics.com
LVDS Connectors FUNC_TEST TRUE TRUE TRUE TRUE TRUE TRUE TRUE
I568 I567 I570 I571 I572 I573 I569
=PP3V3_S0_DDC_LCD PP3V3_SW_LCD
BKL_SYNC LVDS_DDC_CLK LVDS_DDC_DATA LVDS_CONN_A_DATA_N LVDS_CONN_A_DATA_P
8 76 79 79
Speaker Connectors
79 84 79 80 79 80
FUNC_TEST
79 80 94
I557 79 80 94
I558
TRUE TRUE
I574 I566
LVDS_CONN_A_DATA_N LVDS_CONN_A_DATA_P
I559 79 80 94
I560 79 80 94
I561 I575
C
I576
TRUE TRUE
LVDS_CONN_A_DATA_N LVDS_CONN_A_DATA_P
TRUE TRUE TRUE TRUE
LVDS_CONN_A_CLK_F_N LVDS_CONN_A_CLK_F_P LVDS_CONN_B_DATA_N LVDS_CONN_B_DATA_P
I562 79 80 94
I563 79 80 94
I564 I577 I578 I579 I580
79 94
I565
BI_MIC_LO BI_MIC_SHIELD BI_MIC_HI SPKRCONN_L_P_OUT SPKRCONN_L_N_OUT SPKRCONN_R_P_OUT SPKRCONN_R_N_OUT SPKRCONN_S_P_OUT SPKRCONN_S_N_OUT
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
58 59 58 59 58 59 57 58 95 57 58 95 57 58 95 57 58 95
79 80 94
TRUE 6 TPs
79 80 94
57 58 95
I757
GND
I758 I759
TRUE TRUE
I581 I582
LVDS_CONN_B_DATA_N LVDS_CONN_B_DATA_P
79 80 94
I756
79 80 94
I753 I752
TRUE TRUE
I583 I584
TRUE TRUE
I585 I586
TRUE TRUE TRUE TRUE TRUE TRUE
I587 I588 I590 I589 I592 I591
LVDS_CONN_B_DATA_N LVDS_CONN_B_DATA_P LVDS_CONN_B_CLK_F_N LVDS_CONN_B_CLK_F_P LED_RETURN_1 LED_RETURN_2 LED_RETURN_3 LED_RETURN_4 LED_RETURN_5 LED_RETURN_6
79 80 94
I754
79 80 94
I755
79 84
I595 79 84
I594 79 84
I596 79 84
I597 79 84
I593 79 84
TRUE TRUE TRUE TRUE TRUE TRUE
EXCARD Connector I640
I644 I645 I646 I648 I647 I650 I649 I651 I653 I652 I654 I655 I641 I657 I656
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
4 TPs PP5V_SW_ODD SMC_ODD_DETECT
I748
39
I746 39 42
I747
SATA_ODD_R2D_P SATA_ODD_R2D_N SATA_ODD_D2R_C_N SATA_ODD_D2R_C_P
39 89
I745 39 89
I744 39 89
I743 39 89
I741
GND
I742
5 TPs
I740 I739
POWER RAILS
FUNC_TEST I643
I750
FUNC_TEST
TRUE
I642
I749
79 94
I598
B
I751
SATA ODD Connectors
79 94
USB2_EXCARD_CONN_N 32 95 USB2_EXCARD_CONN_P 32 95 PCIE_CLK100M_EXCARD_CONN_N 32 95 PCIE_CLK100M_EXCARD_CONN_P 32 95 PCIE_EXCARD_R2D_N 32 89 95 PCIE_EXCARD_R2D_P 32 89 95 PCIE_EXCARD_D2R_P 17 32 89 PCIE_EXCARD_D2R_N 17 32 89 PP3V3_S3_EXCARD_SWITCH 32 PP3V3_S0_EXCARD_SWITCH 32 PP1V5_S0_EXCARD_SWITCH 32 PLT_RESET_SWITCH_L 32 EXCARD_CPPE_L 32 EXCARD_CPUSB_L 32 EXCARD_CLKREQ_CONN_L 32 SMBUS_MCP_0_CLK SMBUS_MCP_0_DATA
13 21 45 90 13 21 45 90
I602 I603 I604 I605 I607 I606 I609 I608 I610 I612 I611 I613 I600 I625 I624 I623 I622 I620 I621 I618 I619 I617 I615 I616 I614
A
I627 I626 I639 I638 I637 I636 I709 I760 I761 I762 I765
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
PM_SLP_S3_L
21 34 37 42 44 68 81 83
PPBUS_G3H PPBUS_CPU_IMVP_ISNS PP3V42_G3H PP5V_S3 PP5V_S0 PPVCORE_S0_CPU PPVCORE_S0_MCP_REG PPVCORE_S0_MCP PP3V3_S5 PP3V3_S3 PP3V3_S0 PP2V5_S0 PP1V2_S0
8
I736 7 8 43
I737 8
I735 8
I734 8
I733 8
I731 I732 8 95
I730 8
I728 8 95
I729 8
I726 8
I727 8
I725 8
I724 8
I723 8
I721 8
I722 8
I720 8
I718 I719 8
I717 8
I715 8
I716 8
I713 8
I714 8 8
PP1V8_S0GPU_ISNS PPVCORE_GPU PP1V8_S0GPU_ISNS_R PP3V3_S5_AVREF_SMC PPVOUT_S0_LCDBKLT PPDCIN_G3H PPVTTDDR_S3 PP1V8_GPUIFPX
51
51 7 51 50 51 50 51 50 51 50 51 50 51 51 50 51 50 51
50 51 50 51 50 51
50 51 50 51
50 51 45 93 45 93
50 51
50 51
KEYBOARD CONN
I712
PP1V1_S0GPU_REG
IPD_FLEX_CONN PP3V3_S3_LDO TRUE PP18V5_S3 TRUE TPAD_GND_F TRUE Z2_CS_L TRUE Z2_DEBUG3 TRUE Z2_MOSI TRUE Z2_MISO TRUE Z2_SCLK TRUE Z2_BOOST_EN TRUE Z2_HOST_INTN TRUE Z2_BOOT_CFG1 TRUE Z2_CLKIN TRUE Z2_KEY_ACT_L TRUE Z2_RESET TRUE PSOC_MISO TRUE PSOC_MOSI TRUE PSOC_SCLK TRUE SMBUS_SMC_A_S3_SDA TRUE SMBUS_SMC_A_S3_SCL TRUE PSOC_F_CS_L TRUE PICKB_L TRUE
B
8 46
PP1V8_S0 PP1V8R1V5_S3 PP1V8R1V5_S0_FET PPMCPDDR_ISNS PP1V05_S0_REG PP1V2R1V05_S5 PPCPUVTT_S0 PPCPUFSB_ISNS_R PP0V9R0V75_S0_DDRVTT
PP1V2R1V05_ENET PP3V3_ENET_PHY PPVP_FW PP1V0_FW PP3V3_S0GPU
C
57 58 95
79 94
I711 8
I710 8
I763 8
I764
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
PP3V42_G3H WS_KBD1 WS_KBD2 WS_KBD3 WS_KBD4 WS_KBD5 WS_KBD6 WS_KBD7 WS_KBD8 WS_KBD9 WS_KBD10 WS_KBD11 WS_KBD12 WS_KBD13 WS_KBD14 WS_KBD15_CAP WS_KBD16_NUM WS_KBD17 WS_KBD18 WS_KBD19 WS_KBD20 WS_KBD21 WS_KBD22 WS_KBD23 WS_KBD_ONOFF_L WS_LEFT_SHIFT_KBD WS_LEFT_OPTION_KBD WS_CONTROL_KBD KBDLED_ANODE TPAD_GND_F
7 8 43
50 50
50 50 50 50
50 50 50
50 50 50 50 50 50 50 50
50 50 50 50
Functional / ICT Test
50 50
SYNC_MASTER=N/A
50
SYNC_DATE=N/A
NOTICE OF PROPRIETARY PROPERTY
50 50
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
50 51
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
7 51
II NOT TO REPRODUCE OR COPY IT
42 43
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
79 84 8
SIZE 8
DRAWING NUMBER
D
8
APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
7
1
96
A
6
7
"G3Hot" (Always-Present) Rails
3.3V-2.5V Rails
PPBUS_G3H
=PPBUS_G3H
61
7 46
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V MAKE_BASE=TRUE
=PPVIN_S5_P5VP3V3
=PPVIN_S5_CPU_IMVP_ISNS
78
46 65 64
67
PPBUS_CPU_IMVP_ISNS
=PP3V3_S5_MCPPWRGD =PP3V3_FW_LATEVG =PP3V3_S5_P1V05ENETFET =PP3V3_S5_P3V3ENETFET =PP3V3_S5_DP_PORT_PWR
7
62
PPDCIN_G3H
69
=PP3V3_S3_FET
7 43
=PP3V42_G3H_SMCUSBMUX =PP3V42_G3H_SMBUS_SMC_BSA =PP3V42_G3H_LIDSWITCH =PP3V3_S5_SMC =PP3V3_S5_LPCPLUS =PPVIN_S5_SMCVREF =PP3V42_G3H_PWRCTL =PP3V42_G3H_CHGR =PP3V3_S5_RTC_D =PP3V42_G3H_BATT =PP3V42_G3H_TPAD =PP3V42_G3H_BMON_ISNS =PP3V42_G3H_CPUCOREISNS
=PP3V3_S3_WLAN =PP3V3_S3_MCP_GPIO =PP3V3_S3_VREFMRGN =PP3V3_S3_SMBUS_SMC_MGMT =PP3V3_S3_EXCARD =PP3V3_S3_P1V8S0
40 45 41 42 43 52 44
=PP5V_S3_REG
=PP3V3_S0_FET
26
50 46 46
7
=PP5V_S3_SYSLED =PP5V_S3_BTCAMERA =PP5V_S3_WLAN =PP5V_S3_IR
43 31 31 41
=PP5V_S3_DDRREG =PP5V_S3_GPUVCORE =PP5V_S3_RTUSB
79
69 68 69 22 24
=PP1V8R1V5_S0_FET
69
4771 mA 130 mA 500 mA
26 38 34 34
=PP1V8R1V5_S0_MCP_MEM
7
32
=PP1V0_FW_REG
49 62 66 51 82 44 39 39
PP1V0_FW
67
=PP1V0_FW_FWPHY 36
28 29
"GPU" Rails
47
=PP3V3_S0GPU_FET
PP3V3_S0GPU
1034 mA 31 21 27 45
=PP3V3_GPU_VDD33 =PP3V3_GPU_MIO
24
24
67
18 25 68
=PP1V05_S0_MCP_PEX_DVDD
=PP1V05_S0_MCP_PEX_DVDD0 =PP1V05_S0_MCP_PEX_DVDD1
PPVCORE_S0_MCP_REG
7
=PP3V3_GPU_PWRCTL =PP3V3_GPU_VCORELOGIC
78
=PP3V3_GPU_P1V8S0
67
17
PP1V05_S0_MCP_PEX_AVDD
24
MAKE_BASE=TRUE
=PP1V05_S0_MCP_PEX_AVDD0 =PP1V05_S0_MCP_PEX_AVDD1
17
82
=PP1V1_S0GPU_REG
PP1V1_S0GPU_REG
43
24 8
=PP1V05_S0_MCP_SATA_DVDD
=PP1V05_S0_MCP_SATA_DVDD0
20
PP1V05_S0_MCP_SATA_AVDD
=PP1V05_S0_MCP_SATA_AVDD0
20
=PP1V1_GPU_PEX_IOVDDQ =PP1V1_GPU_PEX_IOVDD =PP1V1_GPU_PEX_PLLXVDD =PP1V1_GPU_PLLVDD =PP1V1_GPU_H_PLLVDD =PP1V1_GPU_VID_PLLVDD =PP1V1_GPU_FBPLLAVDD =PP1V1_GPU_IFPCD_IOVDD
45 47
24
MAKE_BASE=TRUE 47 48 48
=PP1V05_S5_MCP
67
PP1V2R1V05_S5
49
241 mA max load
62
105 mA/241 mA 139 mA/ 0 mA
68
(1.1V for A01) 7
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE
49
7 76 79
=PP1V05_S5_MCP_VDD_AUXC =PP1V05_ENET_P1V05ENETFET =PP1V05_S5_P1V05S0FET
69
PPCPUVTT_S0
=PP1V8_GPUIFPX_REG
75 72 77
7
=PP1V8_GPU_IFPX
=PP1V05_S0_CPU =PP1V05_S0_SMC_LS =PP1V05_S0_MCP_FSB
77
6 10 11 12 13 62 43 9 14 22 24
B =PP1V8_S0GPU_ISNS
PP1V8_S0GPU_ISNS
83
=PP1V8_GPU_FB_VDD =PP1V8_GPU_FB_VDDQ =PP1V8_GPU_FBVDDQ =PP1V8_GPU_FBIO
18 19 21 25
64 27
=PPVTT_S3_DDR_BUF
PPVTTDDR_S3
7
73 74 9 73 74 71 72
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V MAKE_BASE=TRUE
21 24 24 25 64
=PPVTT_S0_DDR_LDO
78 46
PP0V9R0V75_S0_DDRVTT
=PPVCORE_GPU_REG
PPVCORE_GPU
21 22 24 54 58 59
=PP0V75_S0_MEM_VTT_A =PP0V75_S0_MEM_VTT_B =PPVTT_S0_VTTCLAMP
39 68 45
69 82
=PP1V8_GPU_REG
ENET Rails 45
7
=PP1V8_S0GPU_ISNS_R
PP1V2R1V05_ENET
47
7
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE
=PP1V05_ENET_MCP_PLL_MAC
51
PP1V8_S0GPU_ISNS_R MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.25V MAKE_BASE=TRUE
32
48
71
29
OR 0.75V
=PP1V05_ENET_FET
=PPVCORE_GPU 28
32
34
7
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.2V MAKE_BASE=TRUE
7
MIN_LINE_WIDTH=2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.9V MAKE_BASE=TRUE
25
80
7
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V MAKE_BASE=TRUE
81
Power Aliases
24
18 24
SYNC_MASTER=(MASTER)
33
SYNC_DATE=(MASTER)
NOTICE OF PROPRIETARY PROPERTY 34
=PP3V3_ENET_FET
83
PP3V3_ENET_PHY
7
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
=PP3V3_ENET_MCP_RMGT
18 24
=PP3V3_ENET_PHY
33
II NOT TO REPRODUCE OR COPY IT 22 24 46
86
=PP1V2_S0_REG
PP1V2_S0
7
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
=PP1V2_S0_GMUX
DRAWING NUMBER
D
83
APPLE INC.
6
5
4
3
2
REV.
051-7546
SCALE
SHT NONE
7
75
PP1V8_GPUIFPX
7
=PP2V5_S0_GMUX
75
45
86
PP2V5_S0
70
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.15 mm VOLTAGE=1.8V MAKE_BASE=TRUE
7
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE
4500 mA
70
34
67
=PPCPUVTT_S0_REG
66
70
22 24
6 13 47
7
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.1V MAKE_BASE=TRUE
17
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.2V MAKE_BASE=TRUE
8
C
68
17
44
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=2.5V MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE
80
8 24
=PP1V05_ENET_MCP_RMGT =PP1V05_ENET_PHY =PP2V5_S0_REG
75 76
=PP3V3_GPU_LVDS_DDC
32
=PP3V3_S0_P1V2P2V5
=PP3V3_GPU_SMBUS_SMC_0_S0 =PP3V3_S0_TPAD
86
6 75 76
8 24
7
11 12 46
7
MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V MAKE_BASE=TRUE
7
=PP1V05_S0_MCP_AVDD_UF =PP1V05_S0_MCP_PEX_DVDD =PP1V05_S0_MCP_PLL_UF =PP1V05_S0_MCP_SATA_DVDD =PP1V05_S0_MCP_HDMI_VDD =PP1V05_S0_VMON
50
7
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.00V MAKE_BASE=TRUE
7
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE
48
80
=PP3V3_S0_BATTCHARGERTMPSNSR
=PPVCORE_S0_MCP
68
PP1V05_S0_REG
=PP1V05_S0_FET
69
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.25V MAKE_BASE=TRUE
=PPMCPCORE_S0_REG
32
69
52
67
11 12
8 45
36 38
47
=PP1V5_S0_MEM_A =PP1V5_S0_MEM_B
=PP3V3_S0_GMUX =PP3V3_S0_DPMUX =PP3V3_S0_DPCONN =PP3V3_S0_MCP_GPIO =PP3V3_S0_HDCPROM =PP3V3R1V5_S0_MCP_HDA =PP3V3_S0_MCP_PLL_UF =PP3V3_S0_MCP_VPLL_UF =PP3V3_S0_MCP_DAC_UF =PP3V3_S0_MCP =PP3V3_S0_AUDIO =PP3V3_S0_ODD =PP3V3_S0_VMON =PP3V3_S0_SMBUS_MCP_1 =PP3V3_FC_CON
7 49
=PP3V3_FW_FWPHY
=PP3V3_FW_P1V0FW
=PPMCPDDR_ISNS_R =PP1V5_S0_CPU =PP1V5_S0_EXCARD =PP1V5_S0_VMON
47
9
PPVCORE_S0_CPU
=PP3V3_FW_REG
7
PPMCPDDR_ISNS
1182 mA
Chipset "VCore" Rails
65
30
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.5V MAKE_BASE=TRUE
29
=PP3V3_S0_SMBUS_MCP_0
7
=PPVCORE_S0_CPU
29
69
PP5V_S0
D
64
=PP1V5_FC_CON
81
38
28
MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.2mm VOLTAGE=1.5V MAKE_BASE=TRUE
37
38
69
PP1V8R1V5_S0_FET
28
=PP3V3_S0_EXCARD =PP3V3_S0_LVDSDDCMUX
A
=PPVP_FW_PORT1 =PPVP_FW_PHY_CPS_FET
8 18 20
7
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=12.6V MAKE_BASE=TRUE
7
=PP1V8R1V5_S0_MCP_FET =PPVIN_S0_DDRREG_LDO =PP1V5_S3_MEM_A =PP1V5_S3_MEM_B =PP1V5_S3_MEMRESET
69
69
=PP5V_S0_FAN_LT =PP5V_S0_FAN_RT =PP5V_S0_CPU_IMVP =PP5V_S0_CPUVTTS0 =PP5V_S0_KBDLED =PP5V_S0GPU_P1V1P1V8_GPU =PP5V_S0_LPCPLUS =PP5V_S0_ODD =PP5V_S0_HDD
=PPVCORE_S0_CPU_REG
PP1V8R1V5_S3
51
69
PPVP_FW
=PPBUS_S5_FW_FET
37
7 95
=PPSPD_S0_MEM_A =PPSPD_S0_MEM_B
40
MIN_LINE_WIDTH=0.60 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=5V MAKE_BASE=TRUE
62
18 25
MIN_LINE_WIDTH=0.8 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=1.5V MAKE_BASE=TRUE
5300 mA
78
=PP5V_S3_P1V05S0FET =PP5V_S3_MCPDDRFET =PP5V_S3_VTTCLAMP =PP5V_S3_AUDIO_PWR =PP5V_RT_REG
=PPDDR_S3_REG
64
69
64
=PP5V_S3_TPAD
65
PP3V3_S0 =PP3V3_S0_LPCPLUS =PP3V3_S0_SMC =PP3V3_S0_SMBUS_SMC_B_S0 =PP3V3_S0_MCPDDRISNS =PP3V3_S0_GPU1V8ISNS =PP3V3_S0_CPUTHMSNS =PP3V3_S0_GPUTHMSNS =PP3V3_S0_FAN_LT =PP3V3_S0_FAN_RT =PP3V3_S0_IMVP =PP3V3_S0_PWRCTL =PP3V3_S0_DDC_LCD =PP3V3_S0_XDP =PP3V3_S0_MCPCOREISNS
60
PP5V_S3
=PP3V3R1V8_S0_MCP_IFP_VDD
44 53 30
MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V MAKE_BASE=TRUE
61
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V MAKE_BASE=TRUE
B
190 mA
24 8
69
5V Rails 63
500 mA max supply
43 63 68
7
=PPMCPDDR_ISNS
=PP3V3_FW_REG =PP3V3_S3_SMBUS_SMC_A_S3 =PP3V3_S3_SMS =PP3V3_S3_REMTHMSNS =PP3V3_S3_TPAD
61
PP3V42_G3H
"FW" (FireWire) Rails
PP1V8_S0
7
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.42V MAKE_BASE=TRUE
C
PP3V3_S3 MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V MAKE_BASE=TRUE
1
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V MAKE_BASE=TRUE
23 44
24 16
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V MAKE_BASE=TRUE
=PP3V42_G3H_REG
=PP1V8_S0_REG
67
82
=PPDCIN_S5_CHGR 60
7 95
60
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V MAKE_BASE=TRUE
=PP18V5_DCIN_CONN
=PP3V3_S5_ROM =PP3V3_S5_MEMRESET =PP3V3_S3_P3V3S3FET =PP3V3_S5_LCD =PP3V3_S0_P3V3S0FET =PP3V3_GPU_P3V3GPUFET =PP3V3_S5_PWRCTL =PP3V3_S5_P1V05FET =PP3V3_S5_MCP =PP3V3_S5_MCP_GPIO =PP3V3_FW_LATEVG_ACTIVE
37
=PPVIN_S5_CPU_IMVP 60
=PP3V3_S5_MCP_A01
85
=PPVIN_S5_CPU_IMVP_ISNS_R =PPVIN_S0_P5VRTS0_MCPCORE =PPVIN_S3_DDRREG =PPVIN_S0GPU_P1V8P1V1 =PPVBAT_G3H_P3V42G3H =PPVIN_S0_P1V05S5
1.8V/DDR 1.5V Rails
PP3V3_S5 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE
66
=PPBUS_S5_FWPWRSW =PPVIN_GPU_GPUVCORE
46
=PP3V3_S5_REG
63
=PPVIN_S0_CPUVTTS0 =PPBUS_S0_LCDBKLT
D
63
2
3
4
5
www.laptop-schematics.com
8
A.0.0 OF
8
1
96
A
8
6
7
2
3
4
5
1
CPU signals
ZT0981
TP_IMVP6_CLKEN_L
STDOFF-4.5OD.98H-1.1-3.48-TH
ZT0984 ZT0985
STDOFF-4.5OD.98H-1.1-3.48-TH
ZT0983 STDOFF-4.5OD.98H-1.1-3.48-TH
D
1
Right CPU TM Hole
MEM_VTT_EN
26
TP_USB_EXTDN
ZT0930
=MCP_BSEL
14
=DDRVTT_EN
64 69
STDOFF-4.5OD.98H-1.1-3.48-TH
20 90
TP_USB_MINIP
USB_MINI_P
20 90
USB_MINI_N
20 90
MAKE_BASE=TRUE
=SPI_CS1_R_L_USE_MLB
21 44
TP_USB_MININ MAKE_BASE=TRUE
GPU signals PEG_D2R_P
89 70
=PEG_D2R_P
17
=PEG_D2R_N
17
D
MAKE_BASE=TRUE
2.0DIA-TALL-EMI-MLB-M97-M98
PEG_D2R_N
89 70
PEG_R2D_C_P
89 70
PEG_R2D_C_N
17
=PEG_R2D_C_N
17
83
GMUX_INT
=DVI_HPD_GMUX_INT
18
MAKE_BASE=TRUE
MAKE_BASE=TRUE
1
STDOFF-4.5OD.98H-1.1-3.48-TH
=PEG_R2D_C_P
MAKE_BASE=TRUE
SM
ZT0987
89 70
MAKE_BASE=TRUE
SH0901
1
20 90
USB_EXTD_N
MAKE_BASE=TRUE
MAKE_BASE=TRUE
ZT0986
USB_EXTD_P
MAKE_BASE=TRUE
MAKE_BASE=TRUE
TP_SPI_CS1_R_L_USE_MLB
STDOFF-4.5OD.98H-1.1-3.48-TH ZT0980 SH0903 STDOFF-4.5OD.98H-1.1-3.48-TH 2.0DIA-TALL-EMI-MLB-M97-M98
Bottom Left GPU TM Hole
TP_USB_EXTDP
62
62 87
MAKE_BASE=TRUE
SM 1
SM
Left CPU TM Hole
CPU_BSEL
87 10
2.0DIA-TALL-EMI-MLB-M97-M98
STDOFF-4.5OD.98H-1.1-3.48-TH Top GPU Right TM Hole
SH0900
SM
IMVP6_VID
MAKE_BASE=TRUE
2.0DIA-TALL-EMI-MLB-M97-M98
STDOFF-4.5OD.98H-1.1-3.48-TH
ZT0982
VR_PWRGD_CLKEN_L
MAKE_BASE=TRUE CPU_VID 87 11
SH0902
PCIE_CLK100M_FC_P
95 32
TP_PCIE_CLK100M_PE4P
R0903 17
MAKE_BASE=TRUE
21
PCIE_CLK100M_FC_N
TP_PCIE_CLK100M_PE4N
17
TP_PCIE_PE4_R2D_CP
17
TP_PCIE_PE4_R2D_CN
17
FC_CLKREQ_L 32 1.4DIA-SHORT-EMI-MLB-M97-M98SH0911 MAKE_BASE=TRUE SM 1.4DIA-SHORT-EMI-MLB-M97-M9832 FC_PRSNT_L SM
TP_PE4_CLKREQ_L
17
1
TP_PCIE_PE4_D2RP
95 32
0
MCP_SPKR
PCIE_FC_R2D_C_P
95 32
SMC_MCP_SAFE_MODE
42
5% 1/16W MF-LF 402
MAKE_BASE=TRUE MAKE_BASE=TRUE
R0900
Frame Holes
10
=PP1V8_GPU_FB_VDDQ
3R2P5
61 60
1
MAKE_BASE=TRUE
1% 1/16W MF-LF 402
ZT0915 GND_BATT_CHGND
SH0910
GPU_FB_A_VREF_DIV =PP1V8_GPU_FB_VREF_A
R0901 1.4DIA-SHORT-EMI-MLB-M97-M98
MAKE_BASE=TRUE
1% 1/16W MF-LF 402
=PP1V8_GPU_FB_VREF_B
SM
74
17
TP_USB_EXTCP TP_USB_EXTCN
17
PCIE_FC_D2R_N
95 32
TP_PCIE_PE4_D2RN
TP_CPU_PECI_MCP
17
TP_MCP_GPIO_17
PCIE_RESET_L
26 17
LCD_BKLT_EN
83
LVDS_BKL_ON
85
DP_IG_ML_P
89 80
=MCP_HDMI_TXC_P
18
=MCP_HDMI_TXC_N
18
Extra FSB Pull-ups
GND_CHASSIS_USB
DP_IG_ML_N DP_IG_ML_P
89 80
24 22 14 8
HDA_BITCLK
DP_IG_ML_N DP_IG_DDC_CLK
HDA_BIT_CLK
=MCP_HDMI_TXD_P
18
=MCP_HDMI_TXD_N
18
8
=PP5V_S3_AUDIO_PWR
=MCP_HDMI_DDC_CLK
18
DP_IG_DDC_DATA
=MCP_HDMI_DDC_DATA
18
NO STUFF
NO STUFF
R09501
R09701
R09901
5% 1/16W MF-LF 402 2
5% 1/16W MF-LF 402 2
1% 1/16W MF-LF 402 2
220
200
NO STUFF
ZT0965
1
R0960
3R2P5 1
GND_CHASSIS_CLUTCH
62
5% 1/16W MF-LF 2 402
ZT0960 3R2P5 1
GND_CHASSIS_SATA
ZT0990 3R2P5 1
87 62 14 10
OUT
87 14 10
OUT
87 14 13 10
OUT
87 14 10
OUT
87 14 10
OUT
Bosses for VRAM HS
2
DP_IG_HPD
150
=MCP_HDMI_HPD
18
ALL_EG_PGOOD
83
MAKE_BASE=TRUE
PM_ALL_GPU_PGOOD
68
1
MAKE_BASE=TRUE
ZT0951 4.0OD1.65H-M1.6X0.35
TP_LVDS_MUX_SEL_EG
LVDS_MUX_SEL_EG
83
EG_RESET_L
83
GPU_RESET_L
70
R0980
ZT0952
150
1% 1/16W MF-LF 2 402
4.0OD1.65H-M1.6X0.35
83 6
JTAG_GMUX_TDI
83 6
JTAG_GMUX_TMS
GMUX_JTAG_TDI
19
GMUX_JTAG_TMS
19
MAKE_BASE=TRUE MAKE_BASE=TRUE
1
JTAG_GMUX_TDO
83 6
GMUX_JTAG_TDO
LVDS_IG_BKL_ON
18
17
MAKE_BASE=TRUE
ZT0953
4.0OD1.65H-M1.6X0.35
IG_BKLT_EN
83
IG_LCD_PWR_EN
83
MAKE_BASE=TRUE
1
LVDS_IG_PANEL_PWR
18
57
AUD_IPHS_SWITCH_EN
2
19 59
MAKE_BASE=TRUE
=P3V3ENET_EN
34
34
CPU_DPRSTP_L FSB_BREQ0_L FSB_CPURST_L CPU_INTR CPU_NMI
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V
ETHERNET ALIASES
MAKE_BASE=TRUE
1
PP5V_S3_AUDIO_AMP
1
10K
54 56
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V
5% 1/16W MF-LF 402
MAKE_BASE=TRUE
1
NO STUFF
C
21 90
PP5V_S3_AUDIO
1
XW0901 R0902
MAKE_BASE=TRUE
NO STUFF
2 SM
MAKE_BASE=TRUE 80 76
32
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=PP1V05_S0_MCP_FSB
SL-3.1X2.7-6CIR-NSP
17
XW0900 SM
MAKE_BASE=TRUE 89 80
80 76
GND_CHASSIS_FAN
54
MAKE_BASE=TRUE
Exist in MRB but not Intel designs. Here for CYA. If found to be necessary, will move to page14.csa
ZT0950 TH
14
AUDIO ALIASES
MAKE_BASE=TRUE 89 80
FC_RESET_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
1
20 90
MAKE_BASE=TRUE
1
3R2P5
20 90
USB_EXTC_N
GMUX ALIASES
GND_CHASSIS_LVDS
ZT0945
USB_EXTC_P
CPU_PECI_MCP AUD_IP_PERIPHERAL_DET
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SH0913
3R2P5
C
29
SM
ZT0940 1
28
MEM_B_A
MAKE_BASE=TRUE
1.4DIA-SHORT-EMI-MLB-M97-M98
1
MEM_A_A
MAKE_BASE=TRUE
PCIE_FC_D2R_P MAKE_BASE=TRUE
SH0912
GPU_FB_B_VREF_DIV
TP_PE4_PRSNT_L
TP_MEM_B_A MAKE_BASE=TRUE
MAKE_BASE=TRUE
95 32
10
TP_MEM_A_A MAKE_BASE=TRUE
MAKE_BASE=TRUE
1
73
PCIE_FC_R2D_C_N
95 32
MAKE_BASE=TRUE
PM_SLP_RMGT_L
21
MAKE_BASE=TRUE
=P1V05ENET_EN
33
=PP3V3_ENET_PHY_VDDREG
33
=RTL8211_REGOUT
www.laptop-schematics.com
Thermal Module Holes
TP_PP3V3_ENET_PHY_VDDREG MAKE_BASE=TRUE
NC_RTL8211_REGOUT MAKE_BASE=TRUE
=RTL8211_ENSWREG
33
GND_CHASSIS_BATTCONN
B
B
MCP79 PCIe PRSNT# Straps
ZT0931 STDOFF-4.0OD3.0H-TH 1 VENICE
ZT0934
9
MAKE_BASE=TRUE
STDOFF-4.0OD3.0H-TH
9
NC_LVDS_B_DATAN
9
NC_LVDS_A_DATAP
STDOFF-4.0OD3.0H-TH 1
9
NC_LVDS_A_DATAN
ZT0935 1
1
VENICE
9
LVDS_A_DATA_P
9
LVDS_A_DATA_N
9
LVDS_IG_B_CLK_P LVDS_IG_B_CLK_N LVDS_IG_BKL_PWM
0
PCIE_FW_PRSNT_L
5% 1/16W MF-LF 402
18 89 18 89
0
NC_LVDS_IG_A_DATAN
LVDS_IG_A_DATA_N
18 89
LVDS_IG_B_DATA_P
18 89
LVDS_IG_B_DATA_N
18 89
MAKE_BASE=TRUE
ZT0989
OUT
GND
17
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.09MM VOLTAGE=0V
R0926 0
EG_CLKREQ_OUT_L
MCP_MII_PD
=MCP_MII_RXER
18
=MCP_MII_CRS
18
=MCP_MII_COL
18
MAKE_BASE=TRUE
STDOFF-4.5OD.98H-1.1-3.48-TH
NC_LVDS_IG_B_DATAP
1
IN
83
5% 1/16W MF-LF 402
MAKE_BASE=TRUE
1
A
18 89
Digital Ground
PEG_PRSNT_L MAKE_BASE=TRUE
ZT0988 LVDS_IG_A_DATA_P
17
NO STUFF
5% 1/16W MF-LF 402
NC_LVDS_IG_A_DATAP
OUT
MAKE_BASE=TRUE
R0927
18
MAKE_BASE=TRUE
STDOFF-4.5OD.98H-1.1-3.48-TH
Signal Aliases SYNC_MASTER=(MASTER)
MAKE_BASE=TRUE
NC_LVDS_IG_B_DATAN
ZT0991
1
R0930
MAKE_BASE=TRUE
9
NC_LVDS_A_DATAP
9
NC_LVDS_A_DATAN
LVDS_A_DATA_P
9
LVDS_A_DATA_N
9
5% 1/16W MF-LF 2 402
MAKE_BASE=TRUE
SYNC_DATE=(MASTER)
NOTICE OF PROPRIETARY PROPERTY
47K
STDOFF-4.5OD.98H-1.1-3.48-TH 1
20
Add other PRSNT# straps if needed. .
R0925
NO_TEST=TRUE
TP_LVDS_IG_B_CLKP MAKE_BASE=TRUE TP_LVDS_IG_B_CLKN MAKE_BASE=TRUE TP_LVDS_IG_BKL_PWM
STDOFF-4.0OD3.0H-TH
LVDS_B_DATA_N
These need work.
NO_TEST=TRUE
MAKE_BASE=TRUE
ZT0933
STDOFF-4.0OD3.0H-TH
9
NO_TEST=TRUE
MAKE_BASE=TRUE
VENICE
LVDS_B_DATA_P
20
=PP1V05_S0_MCP_SATA_AVDD1
NO_TEST=TRUE
MAKE_BASE=TRUE
ZT0932
1
NC_LVDS_B_DATAP
=PP1V05_S0_MCP_SATA_DVDD1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
MAKE_BASE=TRUE
II NOT TO REPRODUCE OR COPY IT 9
NC_LVDS_B_DATAP
9
NC_LVDS_B_DATAN
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
LVDS_B_DATA_P
9
LVDS_B_DATA_N
9
MAKE_BASE=TRUE
SIZE
DRAWING NUMBER
D
MAKE_BASE=TRUE
APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
9
1
96
A
8
6
7
2
3
4
5
1
OMIT
BI
87 14 7
BI
87 14 7
BI
87 14 7
BI
87 14 7
BI
87 14 7
BI
87 14 7
BI
87 14 7
BI
87 14 7
BI
87 14 7
BI
87 14 7
BI
87 14 7
BI
87 14 7
BI
87 14 7
BI
87 14 7
BI
87 14 7
C
BI
87 14 7
BI
87 14 7
BI
87 14 7
BI
87 14 7
BI
87 14 7
BI
87 14 7
BI
87 14 7
BI
87 14 7
BI
87 14 7
BI
87 14 7
BI
87 14 7
BI
87 14 7
BI
87 14
BI
87 14
BI
87 14
BI
87 14
BI
87 14 7
BI
87 14
IN
87 14
OUT
87 14
IN
87 14
IN
87 14 9
IN
87 14 9 87 14
IN IN
FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_REQ_L
K3 H2 K2 J3 L1
REQ0* REQ1* REQ2* REQ3* REQ4*
FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_ADSTB_L
Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1
A6 A20M* A5 FERR* C4 IGNNE*
CPU_STPCLK_L CPU_INTR CPU_NMI CPU_SMI_L
D5 C6 B4 A3 M4 N5 T2 V3 B2 F6 D2 D22 D3
F1
FSB_BREQ0_L CPU_IERR_L CPU_INIT_L
IN
BI
14 87
BI
14 87
BI
14 87
BI
14 87
BI
9 14 87
=PP1V05_S0_CPU
IERR* INIT*
D20 B3
LOCK*
H4
FSB_LOCK_L
RESET* RS0* RS1* RS2* TRDY*
C1 F3 F4 G3 G2
FSB_CPURST_L FSB_RS_L FSB_RS_L FSB_RS_L FSB_TRDY_L
HIT* HITM*
G6 E4
FSB_HIT_L FSB_HITM_L
BPM0* BPM1* BPM2* BPM3* PRDY* PREQ* TCK TDI TDO TMS TRST* DBR*
AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20
87
14 87
BI
6 8 10 11 12 13 62
1
R1002 54.9
1% 1/16W MF-LF 2 402
PLACE TESTPOINT ON FSB_IERR_L WITH A GND 0.1" AWAY
D
14 87
7 14 87
IN
9 13 14 87
IN
14 87
IN
14 87
IN
14 87
IN
14 87
OMIT
A17* A18* A19* A20* A21* A22* A23* A24* A25* A26* A27* A28* A29* A30* A31* A32* A33* A34* A35* ADSTB1*
CPU_A20M_L CPU_FERR_L CPU_IGNNE_L
TP_CPU_RSVD0 TP_CPU_RSVD1 TP_CPU_RSVD2 TP_CPU_RSVD3 TP_CPU_RSVD4 TP_CPU_RSVD5 TP_CPU_RSVD6 TP_CPU_RSVD7 TP_CPU_RSVD8
BR0*
FSB_DEFER_L FSB_DRDY_L FSB_DBSY_L
7 14 87
BI
STPCLK* LINT0 LINT1 SMI*
XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST_L XDP_DBRESET_L
BI
7 14 87
BI
7 14 87
BI
13 87
BI
13 87
BI
13 87
BI
13 87
BI
13 87
=PP1V05_S0_CPU
R10031
87 14 7
BI
87 14 7
BI
1% 1/16W MF-LF 402 2
87 14 7
BI
87 14 7
BI
87 14 7
BI
87 14 7
BI
54.9
13 87
6 10 13 87
87 14 7
BI
IN
6 10 13 87
87 14 7
BI
6 10 87
87 14 7
BI
IN
6 10 13 87
87 14 7
BI
IN
6 10 13 87
87 14 7
BI
87 14 7
BI
87 14 7
BI
87 14 7
BI
87 14 7
BI
87 14 7
BI
87 14 7
BI
OUT
OUT
13 26
1
R1004
5% 1/16W MF-LF 2 402
THERMAL
THERMTRIP*
RSVD0 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8
D21 A24 B25
CPU_PROCHOT_L CPU_THERMD_P CPU_THERMD_N
C7
PM_THRMTRIP_L
OUT OUT
48 95
OUT
48 95
OUT
14 43 87
H CLK
BCLK0 BCLK1
A22 A21
FSB_CLK_CPU_P FSB_CLK_CPU_N
IN
14 87
IN
14 87
62 13 12 11 10 8 6
14 43 62 87
PM_THRMTRIP# SHOULD CONNECT TO ICH AND GMCH WITHOUT T (NO STUB)
=PP1V05_S0_CPU 1
R1005 1K
1% 1/16W MF-LF 402 2
R1020
87 13 10 6
XDP_TDI
D16* D17* D18* D19* D20* D21* D22* D23* D24* D25* D26* D27* D28* D29* D30* D31* DSTBN1* DSTBP1* DINV1*
BI
R10061 XDP_TMS
N22 FSB_D_L K25 FSB_D_L P26 FSB_D_L 87 14 7 BI R23 FSB_D_L 87 14 7 BI L23 FSB_D_L 87 14 7 BI M24 FSB_D_L 87 14 7 BI L22 FSB_D_L 87 14 7 BI M23 FSB_D_L 87 14 7 BI P25 FSB_D_L 87 14 7 BI P23 FSB_D_L 87 14 7 BI P22 FSB_D_L 87 14 7 BI T24 FSB_D_L 87 14 7 BI R24 FSB_D_L 87 14 7 BI L25 FSB_D_L 87 14 7 BI T25 FSB_D_L 87 14 7 BI N25 FSB_D_L 87 14 7 BI FSB_DSTB_L_N L26 87 14 7 BI FSB_DSTB_L_P M26 87 14 7 BI N24 FSB_DINV_L 87 14 7 BI 0.5" MAX LENGTH FOR CPU_GTLREF AD26 87 27 CPU_GTLREF C23 CPU_TEST1 D25 CPU_TEST2 C24 TP_CPU_TEST3 AF26 CPU_TEST4 AF1 TP_CPU_TEST5 NOSTUFF A26 TP_CPU_TEST6 C1000 0.1uF C3 TP_CPU_TEST7 10% 16V B22 CPU_BSEL 87 9 OUT X5R 402 B23 CPU_BSEL 87 9 OUT C21 CPU_BSEL 87 9 OUT
BI
IN
B
87 13 10 6
D0* D1* D2* D3* D4* D5* D6* D7* D8* D9* D10* D11* D12* D13* D14* D15* DSTBN0* DSTBP0* DINV0*
87 14 7
BI
54.9
R1021 54.9
2.0K =PP1V05_S0_CPU
6 8 10 11 12 13 62
1% 1/16W MF-LF 402 2 1
1% 1/16W MF-LF 402
2 1% 1/16W MF-LF 402
PLACE C1000 CLOSE TO CPU_TEST4 PIN. MAKE SURE CPU_TEST4 IS REFERENCED TO GND
R1024
54.9 XDP_TDO 87 10 6 1% PLACEMENT_NOTE=Place R1024 near ITP connector (if present) 1/16W
FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L
E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25
87 14 7
68
PROCHOT* THERMDA THERMDC
6 8 10 11 12 13 62
87 14 7
BI
87 14 7
BI
87 13 10 6
XDP_TRST_L
649
2 OF 4
MISC
Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22
FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L
D48* D49* D50* D51* D52* D53* D54* D55* D56* D57* D58* D59* D60* D61* D62* D63* DSTBN3* DSTBP3* DINV3*
AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25
FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L
AF24 AC20
COMP0 COMP1 COMP2 COMP3
R26 U26 AA1 Y1
DPRSTP* DPSLP* DPWR* PWRGOOD SLP* PSI*
E5 B5 D24 D6 D7 AE6
87 87 87 87
BI
7 14 87
BI
7 14 87
BI
7 14 87
BI
7 14 87
BI
7 14 87
BI
7 14 87
BI
7 14 87
BI
7 14 87
BI
7 14 87
BI
7 14 87
BI
7 14 87
BI
7 14 87
BI
7 14 87
BI
7 14 87
BI
7 14 87
BI
7 14 87
BI
7 14 87
BI
7 14 87
BI
7 14 87
BI
7 14 87
BI
7 14 87
BI
7 14 87
BI
7 14 87
BI
7 14 87
BI
7 14 87
BI
7 14 87
BI
7 14 87
BI
7 14 87
BI
7 14 87
BI
7 14 87
BI
7 14 87
BI
7 14 87
BI
7 14 87
BI
7 14 87
BI
7 14 87
BI
7 14 87
BI
7 14 87
BI
7 14 87
C
LAYOUT NOTE: COMP0,2 CONNECT WITH ZO=27.4OHM, MAKE TRACE LENGTH SHORTER THAN 0.5". COMP1,3 CONNECT WITH ZO=55OHM, MAKE TRACE LENGTH SHORTER THAN 0.5".
R1016 27.4 1% 1/16W MF-LF 402
1% 1/16W MF-LF 402
R1018
R1019
1% 1/16W MF-LF 402
54.9
CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_DPRSTP_L CPU_DPSLP_L FSB_DPWR_L CPU_PWRGD FSB_CPUSLP_L CPU_PSI_L
R1017
54.9
IN
9 14 62 87
IN
14 87
IN
14 87
IN
13 14 87
IN
14 87
OUT
B
27.4
1% 1/16W MF-LF 402
62
0
54.9
R1023
FCBGA
D32* D33* D34* D35* D36* D37* D38* D39* D40* D41* D42* D43* D44* D45* D46* D47* DSTBN2* DSTBP2* DINV2*
R1030
R1022 XDP_TCK
PENRYN
NOSTUFF
MF-LF 402
87 13 10 6
GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL0 BSEL1 BSEL2
U1000
NOSTUFF
R10121
1% 1/16W MF-LF 402
1K
5% 1/16W MF-LF 402 2
1% 1/16W MF-LF 402
5% 1/16W MF-LF 402
NOSTUFF 1
R1007 1K
5% 1/16W MF-LF 2 402
CPU FSB SYNC_MASTER=M87_MLB
A
SYNC_DATE=10/17/2007
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
7
6
5
4
3
2
REV.
051-7546
SCALE
SHT NONE
8
www.laptop-schematics.com
BI
87 14 7
H5 F21 E1
BI
DATA GRP 2
87 14 7
DEFER* DRDY* DBSY*
FSB_ADS_L FSB_BNR_L FSB_BPRI_L
DATA GRP 3
BI
H1 E2 G5
DATA GRP 0
BI
87 14 7
ADS* BNR* BPRI*
DATA GRP 1
BI
87 14 7
CONTROL
87 14 7
XDP/ITP SIGNALS
BI
A3* A4* PENRYN FCBGA A5* 1 OF 4 A6* A7* A8* A9* A10* A11* A12* A13* A14* A15* A16* ADSTB0* ADDR GROUP0
87 14 7
U1000
FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_ADSTB_L
ADDR GROUP1
BI
ICH
BI
87 14 7
RESERVED
D
87 14 7
J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1
A.0.0 OF
10
1
96
A
6
7
(CPU CORE POWER) =PPVCORE_S0_CPU
D
A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18
C
B
OMIT
U1000 PENRYN FCBGA 3 OF 4
VCC
VCC
AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20
Low Voltage:
Ultra Low Voltage:
44.0 A (Design Target)
23.0 A (Design Target)
17.0 A (Design Target)
41.0 A (HFM) 30.4 A (LFM) 25.5 A (SuperLFM)
21.0 A (HFM) 18.7 A (LFM) TBD A (SuperLFM)
TBD TBD
A (HFM) A (LFM)
27.4 A (Auto-Halt/Stop-Grant HFM) 17.0 A (Auto-Halt/Stop-Grant SuperLFM)
TBD TBD
A (Auto-Halt/Stop-Grant HFM) A (Auto-Halt/Stop-Grant SuperLFM)
TBD TBD
A (Auto-Halt/Stop-Grant HFM) A (Auto-Halt/Stop-Grant LFM)
27.4 A (Sleep HFM) 16.8 A (Sleep SuperLFM)
TBD TBD
A (Sleep HFM) A (Sleep SuperLFM)
TBD TBD
A (Sleep HFM) A (Sleep LFM)
25.0 A (Deep Sleep HFM) 16.0 A (Deep Sleep SuperLFM)
TBD TBD
A (Deep Sleep HFM) A (Deep Sleep SuperLFM)
TBD TBD
A (Deep Sleep HFM) A (Deep Sleep LFM)
11.5 A (Deeper Sleep)
TBD
A (Deeper Sleep)
TBD
A (Deeper Sleep)
TBD
A (Enhanced Deeper Sleep)
TBD
A (Enhanced Deeper Sleep)
9.4 A (Enhanced Deeper Sleep)
(CPU IO POWER 1.05V) =PP1V05_S0_CPU
VCCP
G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21
6 8 10 12 13 62
4500 mA (before VCC stable) 2500 mA (after VCC stable)
(CPU INTERNAL PLL POWER 1.5V) =PP1V5_S0_CPU
B26 VCCA C26 VID0 VID1 VID2 VID3 VID4 VID5 VID6
AD6 AF5 AE5 AF4 AE3 AF3 AE2
8 11 12 46
Standard Voltage:
8 12
130 mA CPU_VID CPU_VID CPU_VID CPU_VID CPU_VID CPU_VID CPU_VID
OUT
9 87
OUT
9 87
OUT
9 87
OUT
9 87
OUT
9 87
OUT
9 87
OUT
9 87
=PPVCORE_S0_CPU
8 11 12 46
1
R1100 100
1% 1/16W MF-LF
2 402
PLACEMENT_NOTE=Place within 1 inch of CPU, no stub. VCCSENSE AF7
CPU_VCCSENSE_P
VSSSENSE AE7
CPU_VCCSENSE_N
OUT
62 87
OUT
62 87
1
R1101 100
1% 1/16W MF-LF 2 402 PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.
2
3
4
5
A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3 B1
P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5
OMIT
U1000 PENRYN FCBGA 4 OF 4
VSS
1
VSS
D
www.laptop-schematics.com
8
V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6
C
AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25
B
CPU Power & Ground SYNC_MASTER=M87_MLB
A
SYNC_DATE=10/17/2007
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
8
7
SCALE
SHT NONE
Current numbers from Merom for Santa Rosa EMTS, doc #22221.
6
5
4
3
2
REV.
051-7546
A.0.0 OF
11
1
96
A
8
6
7
3
4
5
2
1
D
D
46 11 8
=PPVCORE_S0_CPU
www.laptop-schematics.com
CPU VCORE HF AND BULK DECOUPLING 4x 330uF, 20x 22uF 0805
CRITICAL
CRITICAL
C1250 1 20% 2.0V 2 POLY-TANT D2T-SM2
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
C1200
C1201
C1202
C1203
C1204
C1205
C1206
C1207
C1208
C1209
20% 6.3V X5R-CERM 603
20% 6.3V X5R-CERM 603
20% 6.3V X5R-CERM 603
20% 6.3V X5R-CERM 603
20% 6.3V X5R-CERM 603
20% 6.3V X5R-CERM 603
20% 6.3V X5R-CERM 603
20% 6.3V X5R-CERM 603
20% 6.3V X5R-CERM 603
22UF
330UF
3
CRITICAL 1
C1251 1
330UF
20% 2.0V 2 POLY-TANT D2T-SM2
22UF
20% 2 6.3V X5R-CERM 603
3
22UF
22UF
22UF
22UF
22UF
22UF
22UF
CRITICAL 22UF
PLACEMENT_NOTE=Place in CPU center cavity. PLACEMENT_NOTE=Place in CPU center cavity.
CRITICAL
CRITICAL
C1252 1
C1253 1
330UF
C
20% 2.0V 2 POLY-TANT D2T-SM2
330UF
3
20% 2.0V 2 POLY-TANT D2T-SM2
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
C1210
C1211
C1212
C1213
C1214
C1215
C1216
C1217
C1218
C1219
22UF
22UF
22UF
22UF
22UF
22UF
22UF
22UF
22UF
22UF
20% 6.3V X5R-CERM 603
3
20% 6.3V X5R-CERM 603
20% 6.3V X5R-CERM 603
20% 6.3V X5R-CERM 603
20% 6.3V X5R-CERM 603
20% 6.3V X5R-CERM 603
20% 6.3V X5R-CERM 603
20% 6.3V X5R-CERM 603
20% 6.3V X5R-CERM 603
20% 6.3V X5R-CERM 603
C
PLACEMENT_NOTE=Place in CPU center cavity. PLACEMENT_NOTE=Place in CPU center cavity.
VCCP (CPU I/O) DECOUPLING 62 13 11 10 8 6
=PP1V05_S0_CPU
1x 470uF, 6x 0.1uF 0402
CRITICAL 1
C1235 1 20% 2.5V 2 POLY D2T
C1236 0.1UF
470UF
20% 2 10V CERM 402
3
1
C1237 0.1UF
20% 2 10V CERM 402
1
C1238 0.1UF
20% 2 10V CERM 402
1
C1239 0.1UF
20% 2 10V CERM 402
1
C1240 0.1UF
20% 2 10V CERM 402
1
C1241 0.1UF
20% 2 10V CERM 402
WF: Consider sharing bulk cap with NB Vtt?
VCCA (CPU AVdd) DECOUPLING
B 11 8
=PP1V5_S0_CPU
C1280 1 10uF
B
1x 10uF, 1x 0.01uF
20% 6.3V 2 X5R 603
1
C1281 0.01UF
10% 2 16V CERM 402 PLACEMENT_NOTE=Place near CPU pin B26.
CPU Decoupling & VID SYNC_MASTER=M87_MLB
A
SYNC_DATE=10/17/2007
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
12
1
96
A
8
6
7
2
3
4
5
1
Mini-XDP Connector NOTE: This is not the standard XDP pinout.
D
Use with 920-0620 adapter board to support CPU, MCP debugging.
D
MCP79-specific pinout =PP3V3_S0_XDP =PP1V05_S0_CPU XDP
CRITICAL XDP_CONN
R13151 54.9
J1300
1% 1/16W MF-LF 402 2
87 10 87 10
87 10 87 10
BI BI
BI IN
87 10
IN
87 10
IN
C
LTH-030-01-G-D-NOPEGS F-ST-SM
XDP_BPM_L XDP_BPM_L
OBSFN_A0 OBSFN_A1
XDP_BPM_L XDP_BPM_L
OBSDATA_A0 OBSDATA_A1
XDP_BPM_L XDP_BPM_L
OBSDATA_A2 OBSDATA_A3
TP_XDP_OBSFN_B0 TP_XDP_OBSFN_B1
OBSFN_B0 OBSFN_B1
TP_XDP_OBSDATA_B0 TP_XDP_OBSDATA_B1
87 14 10
IN
CPU_PWRGD
1
1K
OBSDATA_B0 OBSDATA_B1
TP_XDP_OBSDATA_B2 TP_XDP_OBSDATA_B3
XDP
R1399
OBSDATA_B2 OBSDATA_B3
XDP_PWRGD
2
XDP_OBS20
5% 1/16W MF-LF 402 23 19 21 6
IN OUT
90 45 21 7
BI
90 45 21 7
BI
87 10 6
OUT
PM_LATRIGGER_L JTAG_MCP_TCK SMBUS_MCP_0_DATA SMBUS_MCP_0_CLK XDP_TCK
www.laptop-schematics.com
8 6 62 12 11 10 8 6
PWRGD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3 SDA SCL TCK1 TCK0
NC
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
24
23
26
25
28
27
30
29
32
31
34
33
36
35
38
37
40
39
42
41
44
43
46
45
48
47
50
49
52
51
54
53
56
55
58
57
60
59
1
0.1uF
OBSDATA_C0 OBSDATA_C1
MCP_DEBUG MCP_DEBUG
BI
19 90
BI
19 90
OBSDATA_C2 OBSDATA_C3
MCP_DEBUG MCP_DEBUG
BI
19 90
OBSFN_D0 OBSFN_D1
JTAG_MCP_TDI JTAG_MCP_TMS
OUT
6 21 23
OUT
6 21 23
OBSDATA_D0 OBSDATA_D1
MCP_DEBUG MCP_DEBUG
BI
19 90
BI
19 90
OBSDATA_D2 OBSDATA_D3
MCP_DEBUG MCP_DEBUG
BI
19 90
BI
19 90
IN OUT
BI
6 6 21
19 90
C
XDP
R1303 1
1K
5% 1/16W MF-LF 402
2
FSB_CPURST_L
IN
9 10 14 87
PLACEMENT_NOTE=Place close to CPU to minimize stub.
C1301 0.1uF
10% 16V 2 X5R 402
B
JTAG_MCP_TDO_CONN JTAG_MCP_TRST_L
FSB_CLK_ITP_P ITPCLK/HOOK4 IN 14 87 FSB_CLK_ITP_N ITPCLK#/HOOK5 IN 14 87 VCC_OBS_CD 87 XDP_CPURST_L RESET#/HOOK6 XDP_DBRESET_L DBR#/HOOK7 OUT 10 26 NOTE: XDP_DBRESET_L must be pulled-up to 3.3V. XDP_TDO_CONN TDO IN 6 XDP_TRST_L TRSTn OUT 6 10 87 XDP_TDI TDI OUT 6 10 87 XDP_TMS TMS OUT 6 10 87 XDP_PRESENT# XDP
XDP
C1300 1
OBSFN_C0 OBSFN_C1
10% 2 16V X5R 402
B
998-1571
Direction of XDP module Please avoid any obstructions on even-numbered side of J1300
eXtended Debug Port(MiniXDP) SYNC_MASTER=M99_MLB
A
SYNC_DATE=01/08/2008
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
13
1
96
A
8
6
7
2
3
4
5
1
OMIT
U1400 MCP79-TOPO-B
C
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10
BI
87 10
BI
87 10
BI
87 10
24 22 14 9 8
=PP1V05_S0_MCP_FSB
R14101
R14151
1% 1/16W MF-LF 402 2
5% 1/16W MF-LF 402 2
54.9
B
62
1
R1416
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10 7
BI
87 10
BI
87 10 9
BI
62
5% 1/16W MF-LF 2 402
87 87 43 10
IN
87 10
IN
PM_THRMTRIP_L CPU_FERR_L
87 10
BI
87 10
BI
87 10 7
BI
87 10 7
BI
87 10 7
NO STUFF 1
R1420 1K
5% 1/16W MF-LF 402 2 9
IN
9
IN
9
IN
NO STUFF 1
R1421 1K
5% 1/16W MF-LF 402 2
IN
87 10
OUT
9
OUT
87 62 43 10
OUT
NO STUFF 1
R1422 1K
FSB_DSTB_L_P FSB_DSTB_L_N FSB_DINV_L
T40 CPU_DSTBP0# U40 CPU_DSTBN0# V41 CPU_DBI0#
FSB_DSTB_L_P FSB_DSTB_L_N FSB_DINV_L
W39 CPU_DSTBP1# W37 CPU_DSTBN1# V35 CPU_DBI1#
FSB_DSTB_L_P FSB_DSTB_L_N FSB_DINV_L
N37 CPU_DSTBP2# L36 CPU_DSTBN2# N35 CPU_DBI2#
FSB_DSTB_L_P FSB_DSTB_L_N FSB_DINV_L
M39 CPU_DSTBP3# M41 CPU_DSTBN3# J41 CPU_DBI3#
FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L
AC34 AE38 AE34 AC37 AE37 AE35 AB35 AF35 AG35 AG39 AE33 AG37 AG38 AG34 AN38 AL39 AG33 AL33 AJ33 AN36 AJ35 AJ37 AJ36 AJ38 AL37 AL34 AN37 AJ34 AL38 AL35 AN34 AR39 AN35
FSB_ADSTB_L FSB_ADSTB_L
AE36 CPU_ADSTB0# AK35 CPU_ADSTB1#
FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_REQ_L
AC38 AA33 AC39 AC33 AC35
CPU_REQ0# CPU_REQ1# CPU_REQ2# CPU_REQ3# CPU_REQ4#
FSB_ADS_L FSB_BNR_L FSB_BREQ0_L FSB_BREQ1_L FSB_DBSY_L FSB_DRDY_L FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_TRDY_L
AD42 AD43 AE40 AL32 AD39 AD41 AB42 AD40 AC43 AE41
CPU_ADS# CPU_BNR# CPU_BR0# CPU_BR1# CPU_DBSY# CPU_DRDY# CPU_HIT# CPU_HITM# CPU_LOCK# CPU_TRDY#
CPU_PECI_MCP CPU_PROCHOT_L
E41 AJ41 AG43 AH40
CPU_PECI CPU_PROCHOT# CPU_THERMTRIP# CPU_FERR#
5% 1/16W MF-LF 2 402
=MCP_BSEL =MCP_BSEL =MCP_BSEL
CPU_A3# CPU_A4# CPU_A5# CPU_A6# CPU_A7# CPU_A8# CPU_A9# CPU_A10# CPU_A11# CPU_A12# CPU_A13# CPU_A14# CPU_A15# CPU_A16# CPU_A17# CPU_A18# CPU_A19# CPU_A20# CPU_A21# CPU_A22# CPU_A23# CPU_A24# CPU_A25# CPU_A26# CPU_A27# CPU_A28# CPU_A29# CPU_A30# CPU_A31# CPU_A32# CPU_A33# CPU_A34# CPU_A35#
F42 CPU_BSEL2 D42 CPU_BSEL1 F41 CPU_BSEL0
(MCP_BSEL) (MCP_BSEL) (MCP_BSEL)
Y43 W42 Y40 W41 Y39 V42 Y41 Y42 P42 U41 R42 T39 T42 T41 R41 T43 W35 AA37 W33 W34 AA36 AA34 AA38 AA35 U38 U36 U35 U33 U34 W38 R33 U37 N34 N33 R34 R35 P35 R39 R37 R38 L37 L39 L38 N36 N38 J39 J38 J37 L42 M42 P41 N41 N40 M40 H40 K42 H41 L41 H43 H42 K41 J40 H39 M43
FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L
CPU_BPRI# AA41 CPU_DEFER# AA40
FSB_BPRI_L FSB_DEFER_L
OUT
10 87
OUT
10 87
BCLK_OUT_CPU_P G42 BCLK_OUT_CPU_N G41
FSB_CLK_CPU_P FSB_CLK_CPU_N
OUT
10 87
OUT
10 87
BCLK_OUT_ITP_P AL43 BCLK_OUT_ITP_N AL42
FSB_CLK_ITP_P FSB_CLK_ITP_N
OUT
13 87
OUT
13 87
CPU_D0# CPU_D1# CPU_D2# CPU_D3# CPU_D4# CPU_D5# CPU_D6# CPU_D7# CPU_D8# CPU_D9# CPU_D10# CPU_D11# CPU_D12# CPU_D13# CPU_D14# CPU_D15# CPU_D16# CPU_D17# CPU_D18# CPU_D19# CPU_D20# CPU_D21# CPU_D22# CPU_D23# CPU_D24# CPU_D25# CPU_D26# CPU_D27# CPU_D28# CPU_D29# CPU_D30# CPU_D31# CPU_D32# CPU_D33# CPU_D34# CPU_D35# CPU_D36# CPU_D37# CPU_D38# CPU_D39# CPU_D40# CPU_D41# CPU_D42# CPU_D43# CPU_D44# CPU_D45# CPU_D46# CPU_D47# CPU_D48# CPU_D49# CPU_D50# CPU_D51# CPU_D52# CPU_D53# CPU_D54# CPU_D55# CPU_D56# CPU_D57# CPU_D58# CPU_D59# CPU_D60# CPU_D61# CPU_D62# CPU_D63#
BCLK_OUT_NB_P AL41 BCLK_OUT_NB_N AK42
87 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
BI
7 10 87
D
www.laptop-schematics.com
D
BI
FSB
BGA (1 OF 11) 87 10 7
C
B
FSB_CLK_MCP_P FSB_CLK_MCP_N Loop-back clock for delay matching.
R14301 49.9
1% 1/16W MF-LF 402 2
1
R1435 49.9
1% 1/16W MF-LF 2 402
A
87 10
OUT
87 10
OUT
87 10
OUT
87
87
49.9
1% 1/16W MF-LF 402 2
1
R1436
AC41 CPU_RS0# AB41 CPU_RS1# AC42 CPU_RS2#
PP1V05_S0_MCP_PLL_FSB 24 270 mA (A01) 206 mA 20 mA 29 mA 15 mA 87
R14311
FSB_RS_L FSB_RS_L FSB_RS_L
87
MCP_BCLK_VML_COMP_VDD MCP_BCLK_VML_COMP_GND MCP_CPU_COMP_VCC MCP_CPU_COMP_GND
AG27 AH27 AG28 AH28
+V_DLL_DLCELL_AVDD +V_PLL_MCLK +V_PLL_FSB +V_PLL_CPU
AM39 BCLK_VML_COMP_VDD AM40 BCLK_VML_COMP_GND AM43 CPU_COMP_VCC AM42 CPU_COMP_GND
49.9
1% 1/16W MF-LF 2 402
BCLK_IN_N AK41 BCLK_IN_P AJ40
CPU_A20M# CPU_IGNNE# CPU_INIT# CPU_INTR CPU_NMI CPU_SMI#
AF41 AH39 AH42 AF42 AG41 AH41
CPU_PWRGD AH43 CPU_RESET# H38 CPU_SLP# CPU_DPSLP# CPU_DPWR# CPU_STPCLK# CPU_DPRSTP#
AM33 AN33 AM32 AG42 AN32
CPU_A20M_L CPU_IGNNE_L CPU_INIT_L CPU_INTR CPU_NMI CPU_SMI_L CPU_PWRGD FSB_CPURST_L FSB_CPUSLP_L CPU_DPSLP_L FSB_DPWR_L CPU_STPCLK_L CPU_DPRSTP_L
OUT
10 87
OUT
10 87
OUT
10 87
OUT
9 10 87
OUT
9 10 87
OUT
10 87
=PP1V05_S0_MCP_FSB NO STUFF
8 9 14 22 24
1
R1440 150
MCP CPU Interface
5% 1/16W MF-LF 2 402 OUT
OUT
9 10 13 87
OUT
10 87
OUT
10 87
OUT
10 87
OUT
10 87
OUT
9 10 62 87
SYNC_MASTER=T18_MLB
SYNC_DATE=06/18/2008
NOTICE OF PROPRIETARY PROPERTY
10 13 87
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
8
7
6
SCALE
SHT NONE
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
5
4
3
2
REV.
051-7546
A.0.0 OF
14
1
96
A
6
7
5
2
3
4
OMIT
OMIT
U1400
U1400
MCP79-TOPO-B
MCP79-TOPO-B
C
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28 88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
B
BI
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
BI
88 28
OUT
88 28
OUT
88 28
OUT
88 28
OUT
88 28
OUT
88 28
OUT
88 28
OUT
88 28
OUT
MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ
AL8 AL9 AP9 AN9 AL6 AL7 AN6 AN7 AR6 AR7 AV6 AW5 AN10 AR5 AU6 AV5 AU7 AU8 AW9 AP11 AW6 AY5 AU9 AV9 AU11 AV11 AV13 AW13 AR11 AT11 AR14 AU13 AR26 AU25 AT27 AU27 AP25 AR25 AP27 AR27 AP29 AR29 AP31 AR31 AV27 AN29 AV29 AN31 AU31 AR33 AV37 AW37 AT31 AV31 AT37 AU37 AW39 AV39 AR37 AR38 AV38 AW38 AR35 AP35
MDQ0_63 MDQ0_62 MDQ0_61 MDQ0_60 MDQ0_59 MDQ0_58 MDQ0_57 MDQ0_56 MDQ0_55 MDQ0_54 MDQ0_53 MDQ0_52 MDQ0_51 MDQ0_50 MDQ0_49 MDQ0_48 MDQ0_47 MDQ0_46 MDQ0_45 MDQ0_44 MDQ0_43 MDQ0_42 MDQ0_41 MDQ0_40 MDQ0_39 MDQ0_38 MDQ0_37 MDQ0_36 MDQ0_35 MDQ0_34 MDQ0_33 MDQ0_32 MDQ0_31 MDQ0_30 MDQ0_29 MDQ0_28 MDQ0_27 MDQ0_26 MDQ0_25 MDQ0_24 MDQ0_23 MDQ0_22 MDQ0_21 MDQ0_20 MDQ0_19 MDQ0_18 MDQ0_17 MDQ0_16 MDQ0_15 MDQ0_14 MDQ0_13 MDQ0_12 MDQ0_11 MDQ0_10 MDQ0_9 MDQ0_8 MDQ0_7 MDQ0_6 MDQ0_5 MDQ0_4 MDQ0_3 MDQ0_2 MDQ0_1 MDQ0_0
MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM
AN5 AU5 AR10 AN13 AN27 AW29 AV35 AR34
MDQM0_7 MDQM0_6 MDQM0_5 MDQM0_4 MDQM0_3 MDQM0_2 MDQM0_1 MDQM0_0
MDQS0_7_P MDQS0_7_N MDQS0_6_P MDQS0_6_N MDQS0_5_P MDQS0_5_N MDQS0_4_P MDQS0_4_N MDQS0_3_P MDQS0_3_N MDQS0_2_P MDQS0_2_N MDQS0_1_P MDQS0_1_N MDQS0_0_P MDQS0_0_N
MEMORY PARTITION 0
D
88 28
BGA (3 OF 11)
MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N
AL10 AL11 AR8 AR9 AW7 AW8 AP13 AR13 AV25 AW25 AU30 AU29 AT35 AU35 AU39 AT39
MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L
MRAS0# AV17 MCAS0# AP17 MWE0# AR17
MEM_A_BA MEM_A_BA MEM_A_BA
MBA0_2 AP23 MBA0_1 AP19 MBA0_0 AW17
MA0_14 MA0_13 MA0_12 MA0_11 MA0_10 MA0_9 MA0_8 MA0_7 MA0_6 MA0_5 MA0_4 MA0_3 MA0_2 MA0_1 MA0_0
1
MEM_A_A MEM_A_A MEM_A_A MEM_A_A MEM_A_A MEM_A_A MEM_A_A MEM_A_A MEM_A_A MEM_A_A MEM_A_A MEM_A_A MEM_A_A MEM_A_A MEM_A_A
AR23 AU15 AN23 AW21 AN19 AV21 AR22 AU21 AP21 AR21 AN21 AV19 AU19 AT19 AR19
BI
28 88
88 29
BI
BI
28 88
88 29
BI
BI
28 88
88 29
BI
BI
28 88
88 29
BI
BI
28 88
88 29
BI
BI
28 88
88 29
BI
BI
28 88
88 29
BI
BI
28 88
88 29
BI
BI
28 88
88 29
BI
BI
28 88
88 29
BI
BI
28 88
88 29
BI
BI
28 88
88 29
BI
BI
28 88
88 29
BI
BI
28 88
88 29
BI
BI
28 88
88 29
BI
BI
28 88
88 29
BI
88 29
BI
88 29
BI
88 29
BI
88 29
BI
88 29
BI
OUT
28 88
88 29
BI
OUT
28 88
88 29
BI
OUT
28 88
88 29
BI
88 29
BI
88 29
BI
88 29
BI
88 29
BI
88 29
BI
OUT
28 88
88 29
BI
OUT
28 88
88 29
BI
OUT
28 88
88 29
BI
88 29
BI
88 29
BI
88 29
BI
88 29
BI
88 29
BI
88 29
BI
88 29
BI
88 29
BI
OUT
28 88
OUT
28 88
OUT
28 88
OUT
28 88
OUT
28 88
OUT
28 88
OUT
28 88
OUT
28 88
OUT
28 88
OUT
28 88
88 29
BI
88 29
BI
88 29
BI
88 29
BI
88 29
BI
88 29
BI
88 29
BI
88 29
BI
88 29
BI
88 29
BI
28 88
OUT
28 88
OUT
28 88
OUT
28 88
MEMORY CONTROL 0A TP_MEM_A_CLK2P TP_MEM_A_CLK2N
MCLK0A_2_P AW33 MCLK0A_2_N AV33
BI
28 88
OUT
OUT
88 29
88 29
BI
88 29
BI
88 29
BI
88 29
BI
88 29
BI
88 29
BI
88 29
BI
88 29
BI
MCLK0A_1_P BA24 MCLK0A_1_N AY24
MEM_A_CLK_P MEM_A_CLK_N
OUT
28 88
88 29
BI
OUT
28 88
88 29
BI
MCLK0A_0_P BB20 MCLK0A_0_N BC20
MEM_A_CLK_P MEM_A_CLK_N
88 29 28 88
BI
OUT OUT
28 88
MCS0A_1# AT15 MCS0A_0# AR18
MEM_A_CS_L MEM_A_CS_L
MODT0A_1 AP15 MODT0A_0 AV15
MEM_A_ODT MEM_A_ODT
MCKE0A_1 AU23 MCKE0A_0 AT23
MEM_A_CKE MEM_A_CKE
88 29
BI
88 29
BI
OUT
28 88
88 29
OUT
OUT
28 88
88 29
OUT
88 29
OUT
OUT
28 88
88 29
OUT
OUT
28 88
88 29
OUT
88 29
OUT
OUT
28 88
88 29
OUT
OUT
28 88
88 29
OUT
MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ
AT4 AT3 AV2 AV3 AR4 AR3 AU2 AU3 AY4 AY3 BB3 BC3 AW4 AW3 BA3 BB2 BB5 BA5 BA8 BC8 BB4 BC4 BA7 AY8 BA9 BB10 BB12 AW12 BB8 BB9 AY12 BA12 BC32 AW32 BA35 AY36 BA32 BB32 BA34 AY35 BC36 AW36 BA39 AY40 BA36 BB36 BA38 AY39 BB40 AW40 AV42 AV41 BA40 BC40 AW42 AW41 AT40 AT41 AP41 AN40 AU40 AU41 AR41 AP42
MDQ1_63 MDQ1_62 MDQ1_61 MDQ1_60 MDQ1_59 MDQ1_58 MDQ1_57 MDQ1_56 MDQ1_55 MDQ1_54 MDQ1_53 MDQ1_52 MDQ1_51 MDQ1_50 MDQ1_49 MDQ1_48 MDQ1_47 MDQ1_46 MDQ1_45 MDQ1_44 MDQ1_43 MDQ1_42 MDQ1_41 MDQ1_40 MDQ1_39 MDQ1_38 MDQ1_37 MDQ1_36 MDQ1_35 MDQ1_34 MDQ1_33 MDQ1_32 MDQ1_31 MDQ1_30 MDQ1_29 MDQ1_28 MDQ1_27 MDQ1_26 MDQ1_25 MDQ1_24 MDQ1_23 MDQ1_22 MDQ1_21 MDQ1_20 MDQ1_19 MDQ1_18 MDQ1_17 MDQ1_16 MDQ1_15 MDQ1_14 MDQ1_13 MDQ1_12 MDQ1_11 MDQ1_10 MDQ1_9 MDQ1_8 MDQ1_7 MDQ1_6 MDQ1_5 MDQ1_4 MDQ1_3 MDQ1_2 MDQ1_1 MDQ1_0
MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM
AT5 BA2 AY7 BA11 BB34 BB38 AY43 AR42
MDQM1_7 MDQM1_6 MDQM1_5 MDQM1_4 MDQM1_3 MDQM1_2 MDQM1_1 MDQM1_0
MDQS1_7_P MDQS1_7_N MDQS1_6_P MDQS1_6_N MDQS1_5_P MDQS1_5_N MDQS1_4_P MDQS1_4_N MDQS1_3_P MDQS1_3_N MDQS1_2_P MDQS1_2_N MDQS1_1_P MDQS1_1_N MDQS1_0_P MDQS1_0_N
MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N
AT2 AT1 AY2 AY1 BB6 BA6 BA10 AY11 BB33 BA33 BB37 BA37 BA43 AY42 AT42 AT43
MRAS1# AW16 MCAS1# BA15 MWE1# BA16
MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L
MBA1_2 BB29 MBA1_1 BB18 MBA1_0 BB17
MEM_B_BA MEM_B_BA MEM_B_BA
BA29 BA14 AW28 BC28 BA17 BB28 AY28 BA28 AY27 BA27 BA26 BB26 BA25 BB25 BA18
MEM_B_A MEM_B_A MEM_B_A MEM_B_A MEM_B_A MEM_B_A MEM_B_A MEM_B_A MEM_B_A MEM_B_A MEM_B_A MEM_B_A MEM_B_A MEM_B_A MEM_B_A
MA1_14 MA1_13 MA1_12 MA1_11 MA1_10 MA1_9 MA1_8 MA1_7 MA1_6 MA1_5 MA1_4 MA1_3 MA1_2 MA1_1 MA1_0
BI
29 88
BI
29 88
BI
29 88
BI
29 88
BI
29 88
BI
29 88
BI
29 88
BI
29 88
BI
29 88
BI
29 88
BI
29 88
BI
29 88
BI
29 88
BI
29 88
BI
29 88
BI
29 88
OUT
29 88
OUT
29 88
OUT
29 88
OUT
29 88
OUT
29 88
OUT
29 88
OUT
29 88
OUT
29 88
OUT
29 88
OUT
29 88
OUT
29 88
OUT
29 88
OUT
29 88
OUT
29 88
OUT
29 88
OUT
29 88
OUT
29 88
OUT
29 88
OUT
29 88
OUT
29 88
OUT
29 88
D
www.laptop-schematics.com
BGA (2 OF 11)
MEMORY PARTITION 1
8
C
MEMORY CONTROL 1A MCLK1A_2_P BA42 MCLK1A_2_N BB42
TP_MEM_B_CLK2P TP_MEM_B_CLK2N
MCLK1A_1_P BB22 MCLK1A_1_N BA22
MEM_B_CLK_P MEM_B_CLK_N
OUT
29 88
OUT
29 88
MCLK1A_0_P BA19 MCLK1A_0_N AY19
MEM_B_CLK_P MEM_B_CLK_N
OUT
29 88
OUT
29 88
MCS1A_1# BB14 MCS1A_0# BB16
MEM_B_CS_L MEM_B_CS_L
OUT
29 88
OUT
29 88
MODT1A_1 BB13 MODT1A_0 AY15
MEM_B_ODT MEM_B_ODT
OUT
29 88
OUT
29 88
MCKE1A_1 AY31 MCKE1A_0 BB30
MEM_B_CKE MEM_B_CKE
OUT
29 88
OUT
29 88
B
MCP Memory Interface SYNC_MASTER=T18_MLB
A
SYNC_DATE=06/18/2008
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
15
1
96
A
8
6
7
3
4
5
2
1
OMIT
U1400 MCP79-TOPO-B
BB24 MCLK0B_1_P BC24 MCLK0B_1_N
TP_MEM_A_CLK3P TP_MEM_A_CLK3N
BA21 MCLK0B_0_P BB21 MCLK0B_0_N
TP_MEM_A_CS_L TP_MEM_A_CS_L
AU17 MCS0B_0# AR15 MCS0B_1#
TP_MEM_A_ODT TP_MEM_A_ODT
AN17 MODT0B_0 AN15 MODT0B_1
TP_MEM_A_CKE TP_MEM_A_CKE
AV23 MCKE0B_0 AN25 MCKE0B_1
PP1V05_S0_MCP_PLL_CORE 24 17 mA 87 mA (A01) 12 mA 19 mA 39 mA
=PP1V8R1V5_S0_MCP_MEM
R16101 40.2
1% 1/16W MF-LF 402 2
88 88
MCP_MEM_COMP_VDD MCP_MEM_COMP_GND
T27 U28 U27 T28
+V_PLL_XREF_XS +V_PLL_DP +V_PLL_CORE +V_VPLL
TP_MEM_B_CLK5P TP_MEM_B_CLK5N
MCLK1B_1_P AY23 MCLK1B_1_N BA23
TP_MEM_B_CLK4P TP_MEM_B_CLK4N
MCLK1B_0_P BA20 MCLK1B_0_N AY20
TP_MEM_B_CLK3P TP_MEM_B_CLK3N
MCS1B_0# BC16 MCS1B_1# BA13
TP_MEM_B_CS_L TP_MEM_B_CS_L
MODT1B_0 AY16 MODT1B_1 BC13
TP_MEM_B_ODT TP_MEM_B_ODT
MCKE1B_0 BA30 MCKE1B_1 BA31
TP_MEM_B_CKE TP_MEM_B_CKE
MRESET0# AY32
AN41 MEM_COMP_VDD AM41 MEM_COMP_GND
R16111 40.2
C
MCLK1B_2_P BA41 MCLK1B_2_N BB41
AA22 AP12 G30 P10 T10 T6 V10 V34 W5 AA39 AB22 AB7 AD22 AE20 AF24 AG24 AH35 AK7 AM28 AT25 AP30 AR36 AU10 F28 BC21 AY9 BC9 D34 F24 G32 H31 K7 M38 M5 M6 M7 M9 N39 N8 P33 P34 P37 P4 P40 P7 R36 R40 R43 R5 T18 T20 AK11 T24 T26
1% 1/16W MF-LF 402 2
B
A
GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18 GND19 GND20 GND21 GND22 GND23 GND24 GND25 GND26 GND27 GND28 GND29 GND30 GND31 GND32 GND33 GND34 GND35 GND36 GND37 GND38 GND39 GND40 GND41 GND42 GND43 GND44 GND45 GND46 GND47 GND48 GND49 GND50 GND51 GND52 GND53 GND54
+VDD_MEM1 +VDD_MEM2 +VDD_MEM3 +VDD_MEM4 +VDD_MEM5 +VDD_MEM6 +VDD_MEM7 +VDD_MEM8 +VDD_MEM9 +VDD_MEM10 +VDD_MEM11 +VDD_MEM12 +VDD_MEM13 +VDD_MEM14 +VDD_MEM15 +VDD_MEM16 +VDD_MEM17 +VDD_MEM18 +VDD_MEM19 +VDD_MEM20 +VDD_MEM21 +VDD_MEM22 +VDD_MEM23 +VDD_MEM24 +VDD_MEM25 +VDD_MEM26 +VDD_MEM27 +VDD_MEM28 +VDD_MEM29 +VDD_MEM30 +VDD_MEM31 +VDD_MEM32 +VDD_MEM33 +VDD_MEM34 +VDD_MEM35 +VDD_MEM36 +VDD_MEM37 +VDD_MEM38 +VDD_MEM39 +VDD_MEM40 +VDD_MEM41 +VDD_MEM42 +VDD_MEM43 +VDD_MEM44 +VDD_MEM45 GND55 GND56 GND57 GND58 GND59 GND60 GND61 GND62 GND63 GND64
AM17 AM19 AM21 AM23 AM25 AM27 AM29 AN16 BC29 AN20 AN24 AT17 AP16 AN22 AP20 AP24 AV16 AR16 AR20 AR24 AW15 AP22 AP18 AU16 AN18 AU24 AT21 AY29 AV24 AU20 AU22 AW27 BC17 AV20 AY17 AY18 AM15 AU18 AY25 AY26 AW19 AW24 BC25 AL30 AM31
D
MCP_MEM_RESET_L OUT TP or NC for DDR2.
=PP1V8R1V5_S0_MCP_MEM 4771 mA (A01, DDR3)
www.laptop-schematics.com
24 16 8
TP_MEM_A_CLK4P TP_MEM_A_CLK4N
MEMORY CONTROL 1B
D
AU33 MCLK0B_2_P AU34 MCLK0B_2_N
MEMORY CONTROL 0B
BGA (4 OF 11)
TP_MEM_A_CLK5P TP_MEM_A_CLK5N
30
8 16 24
C
B
T33 T34 T35 T37 T38 T7 T9 U18 U20 U22
MCP Memory Misc SYNC_MASTER=T18_MLB
SYNC_DATE=06/18/2008
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
8
7
6
SCALE
SHT NONE
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
5
4
3
2
REV.
051-7546
A.0.0 OF
16
1
96
A
8
7
6
3
4
5
2
1
OMIT
U1400 MCP79-TOPO-B BGA (5 OF 11)
9
IN
9
IN
9
IN
9
IN
9
IN
9
IN
9
IN
9
IN
9
IN
9
IN
9
IN
9
IN
9
IN
9
IN
9
IN
9
IN
9
IN
9
IN
9
IN
9
IN
9
IN
9
IN
9
IN
9
IN
9
IN
9
IN
9
IN
9
IN
9
IN
9
IN
9
IN
=PEG_D2R_P =PEG_D2R_N =PEG_D2R_P =PEG_D2R_N =PEG_D2R_P =PEG_D2R_N =PEG_D2R_P =PEG_D2R_N =PEG_D2R_P =PEG_D2R_N =PEG_D2R_P =PEG_D2R_N =PEG_D2R_P =PEG_D2R_N =PEG_D2R_P =PEG_D2R_N =PEG_D2R_P =PEG_D2R_N =PEG_D2R_P =PEG_D2R_N =PEG_D2R_P =PEG_D2R_N =PEG_D2R_P =PEG_D2R_N =PEG_D2R_P =PEG_D2R_N =PEG_D2R_P =PEG_D2R_N =PEG_D2R_P =PEG_D2R_N =PEG_D2R_P =PEG_D2R_N
PE0_RX0_P PE0_RX0_N PE0_RX1_P PE0_RX1_N PE0_RX2_P PE0_RX2_N PE0_RX3_P PE0_RX3_N PE0_RX4_P PE0_RX4_N PE0_RX5_P PE0_RX5_N PE0_RX6_P PE0_RX6_N PE0_RX7_P PE0_RX7_N PE0_RX8_P PE0_RX8_N PE0_RX9_P PE0_RX9_N PE0_RX10_P PE0_RX10_N PE0_RX11_P PE0_RX11_N PE0_RX12_P PE0_RX12_N PE0_RX13_P PE0_RX13_N PE0_RX14_P PE0_RX14_N PE0_RX15_P PE0_RX15_N
PE0_TX0_P PE0_TX0_N PE0_TX1_P PE0_TX1_N PE0_TX2_P PE0_TX2_N PE0_TX3_P PE0_TX3_N PE0_TX4_P PE0_TX4_N PE0_TX5_P PE0_TX5_N PE0_TX6_P PE0_TX6_N PE0_TX7_P PE0_TX7_N PE0_TX8_P PE0_TX8_N PE0_TX9_P PE0_TX9_N PE0_TX10_P PE0_TX10_N PE0_TX11_P PE0_TX11_N PE0_TX12_P PE0_TX12_N PE0_TX13_P PE0_TX13_N PE0_TX14_P PE0_TX14_N PE0_TX15_P PE0_TX15_N
=PEG_R2D_C_P =PEG_R2D_C_N =PEG_R2D_C_P =PEG_R2D_C_N =PEG_R2D_C_P =PEG_R2D_C_N =PEG_R2D_C_P =PEG_R2D_C_N =PEG_R2D_C_P =PEG_R2D_C_N =PEG_R2D_C_P =PEG_R2D_C_N =PEG_R2D_C_P =PEG_R2D_C_N =PEG_R2D_C_P =PEG_R2D_C_N =PEG_R2D_C_P =PEG_R2D_C_N =PEG_R2D_C_P =PEG_R2D_C_N =PEG_R2D_C_P =PEG_R2D_C_N =PEG_R2D_C_P =PEG_R2D_C_N =PEG_R2D_C_P =PEG_R2D_C_N =PEG_R2D_C_P =PEG_R2D_C_N =PEG_R2D_C_P =PEG_R2D_C_N =PEG_R2D_C_P =PEG_R2D_C_N
C5 D4 C4 B4 A4 A3 B3 B2 C1 D1 D2 E1 E2 F2 F3 F4 G3 H4 H3 H2 H1 J1 J2 J3 K2 K3 L4 L3 M4 M3 M2 M1
OUT
9
OUT
9
OUT
9
OUT
9
OUT
9
OUT
9
OUT
9
OUT
9
OUT
9
OUT
9
OUT
9
OUT
9
OUT
9
OUT
9
OUT
9
OUT
9
OUT
9
OUT
9
OUT
9
OUT
9
OUT
9
OUT
9
OUT
9
OUT
9
OUT
9
OUT
9
OUT
9
OUT
9
OUT
9
OUT
9
OUT
9
OUT
9
D
PE0_REFCLK_P E11 PE0_REFCLK_N D11
PEG_CLK100M_P PEG_CLK100M_N
OUT
70 89
OUT
70 89
D5 PEB_CLKREQ#/GPIO_49 D9 PEB_PRSNT# Int PU
PE1_REFCLK_P G11 PE1_REFCLK_N F11
PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_N
OUT
31 89
OUT
31 89
FW_CLKREQ_L PCIE_FW_PRSNT_L
Int PU E8 PEC_CLKREQ#/GPIO_50 C10 PEC_PRSNT# Int PU
PE2_REFCLK_P J11 PE2_REFCLK_N J10
PCIE_CLK100M_FW_P PCIE_CLK100M_FW_N
OUT
36 89
OUT
36 89
EXCARD_CLKREQ_L PCIE_EXCARD_PRSNT_L
Int PU M15 PED_CLKREQ#/GPIO_51 B10 PED_PRSNT# Int PU
PE3_REFCLK_P G13 PE3_REFCLK_N F13
PCIE_CLK100M_EXCARD_P PCIE_CLK100M_EXCARD_N
OUT
32 89
OUT
32 89
TP_PE4_CLKREQ_L TP_PE4_PRSNT_L
L16 PEE_CLKREQ#/GPIO_16 L18 PEE_PRSNT#/GPIO_46
PE4_REFCLK_P J13 PE4_REFCLK_N H13
TP_PCIE_CLK100M_PE4P TP_PCIE_CLK100M_PE4N
OUT
AUD_IP_PERIPHERAL_DET GMUX_JTAG_TCK_L
M16 PEF_CLKREQ#/GPIO_17 M18 PEF_PRSNT#/GPIO_47
PE5_REFCLK_P L14 PE5_REFCLK_N K14
TP_PCIE_CLK100M_PE5P TP_PCIE_CLK100M_PE5N
9
IN
TP_MCP_GPIO_18 GMUX_JTAG_TDO
M17 PEG_CLKREQ#/GPIO_18 M19 PEG_PRSNT#/GPIO_48
PE6_REFCLK_P N14 PE6_REFCLK_N M14
TP_PCIE_CLK100M_PE6P TP_PCIE_CLK100M_PE6N
32 31 23
IN
PCIE_WAKE_L
F17 PE_WAKE# Int
89 31
IN
89 31
IN
89 36
IN
89 36
IN
89 32 7
IN
89 32 7
IN
9
31
IN
31
IN
36
IN
9
IN
32
IN
32
IN
83
Int PU
MINI_CLKREQ_L PCIE_MINI_PRSNT_L
9
9
Int PU C9 PE0_PRSNT_16#
PEG_PRSNT_L
IN
9
B
F7 E7 D7 C7 E6 F6 E5 F5 E4 E3 C3 D3 G5 H5 J7 J6 J5 J4 L11 L10 L9 L8 L7 L6 N11 N10 N9 P9 N7 N6 N5 N4
IN
9 9
8
Int PU Int PU
Int PU
Int PU
PEX_RST0# K11
PCIE_RESET_L
OUT
9 26
PE1_TX0_P D8 PE1_TX0_N C8
PCIE_MINI_R2D_C_P PCIE_MINI_R2D_C_N
OUT
31 89
OUT
31 89
PCIE_FW_D2R_P PCIE_FW_D2R_N
H9 PE1_RX1_P G9 PE1_RX1_N
PE1_TX1_P B8 PE1_TX1_N A8
PCIE_FW_R2D_C_P PCIE_FW_R2D_C_N
OUT
36 89
OUT
36 89
PCIE_EXCARD_D2R_P PCIE_EXCARD_D2R_N
F9 PE1_RX2_P E9 PE1_RX2_N
PE1_TX2_P A7 PE1_TX2_N B7
PCIE_EXCARD_R2D_C_P PCIE_EXCARD_R2D_C_N
OUT
32 89
OUT
32 89
TP_PCIE_PE4_D2RP TP_PCIE_PE4_D2RN
H7 PE1_RX3_P G7 PE1_RX3_N
PE1_TX3_P B6 PE1_TX3_N C6
TP_PCIE_PE4_R2D_CP TP_PCIE_PE4_R2D_CN
+DVDD0_PEX1 +DVDD0_PEX2 +DVDD0_PEX3 +DVDD0_PEX4 +DVDD0_PEX5 +DVDD0_PEX6 +DVDD0_PEX7 +DVDD0_PEX8
=PP1V05_S0_MCP_PEX_DVDD1 T19 +DVDD1_PEX1 U19 +DVDD1_PEX2
24
PP1V05_S0_MCP_PLL_PEX 84 mA (A01)
T16 +V_PLL_PEX
MCP_PEX_CLK_COMP NO STUFF
A11 PEX_CLK_COMP
89
A
9
K9 PE1_RX0_P J9 PE1_RX0_N
Minimum 1.025V for Gen2 support
8
9
PCIE_MINI_D2R_P PCIE_MINI_D2R_N
T17 W19 U17 V19 W16 W17 W18 U16
C
Int PU
Int PU PU (S5)
=PP1V05_S0_MCP_PEX_DVDD0 57 mA (A01, DVDD0 & 1)
www.laptop-schematics.com
C
IN
PCI EXPRESS
D
9
+AVDD0_PEX1 +AVDD0_PEX2 +AVDD0_PEX3 +AVDD0_PEX4 +AVDD0_PEX5 +AVDD0_PEX6 +AVDD0_PEX7 +AVDD0_PEX8 +AVDD0_PEX9 +AVDD0_PEX10 +AVDD0_PEX11 +AVDD0_PEX12 +AVDD0_PEX13
Y12 AA12 AB12 M12 P12 R12 N12 T12 U12 AC12 AD12 V12 W12
=PP1V05_S0_MCP_PEX_AVDD0 206 mA (A01, AVDD0 & 1)
B
9 9
8
Minimum 1.025V for Gen2 support
=PP1V05_S0_MCP_PEX_AVDD1
8
+AVDD1_PEX1 M13 +AVDD1_PEX2 N13 +AVDD1_PEX3 P13
MCP PCIe Interfaces SYNC_MASTER=T18_MLB
1
R1710
If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX. If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.
2.37K 1% 1/16W MF-LF 2 402
SYNC_DATE=06/18/2008
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
PLACEMENT_NOTE=Place within 12.7mm of U1400
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
8
7
6
SCALE
SHT NONE
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
5
4
3
2
REV.
051-7546
A.0.0 OF
17
1
96
A
8
6
7
2
3
4
5
1
OMIT
U1400 MCP79-TOPO-B
24 18 8
=PP3V3_ENET_MCP_RMGT
91 33
IN
91 33
IN
91 33
IN
91 33
IN
91 33
IN
91 33
IN
9
IN
9
IN
9
IN
ENET_RXD ENET_RXD ENET_RXD ENET_RXD
C23 B23 E24 A24
49.9
1% 1/16W MF-LF 402 2
24
+V_DUAL_RMGT1 U23 +V_DUAL_RMGT2 V23
A23 RGMII_RXC/MII_RXCLK C22 RGMII_RXCTL/MII_RXDV
=MCP_MII_RXER =MCP_MII_COL =MCP_MII_CRS
F23 MII_RXER/GPIO_36 B26 MII_COL/GPIO_20/MSMB_DATA B22 MII_CRS/GPIO_21/MSMB_CLK
91
RGMII_MDC D21 RGMII_MDIO C21
MCP_MII_COMP_VDD MCP_MII_COMP_GND
C27 MII_COMP_VDD B27 MII_COMP_GND
TP_MCP_RGB_DAC_RSET TP_MCP_RGB_DAC_VREF
MII_RESET# J23
25
C39 RGB_DAC_RSET B38 RGB_DAC_VREF
C 89 25
OUT
89 25
OUT
MCP_TV_DAC_RSET MCP_TV_DAC_VREF
E36 TV_DAC_RSET A35 TV_DAC_VREF
=PP3V3_S5_MCP_GPIO
47K
IN
25
OUT
MCP_CLK27M_XTALIN MCP_CLK27M_XTALOUT
C38 XTALIN_TV D38 XTALOUT_TV
TV C Y Comp
44
BI 80
Interface Mode
B
MCP Signal
TMDS/HDMI
DisplayPort
=MCP_HDMI_TXC_P/N =MCP_HDMI_TXD_P/N =MCP_HDMI_TXD_P/N =MCP_HDMI_TXD_P/N =MCP_HDMI_DDC_CLK =MCP_HDMI_DDC_DATA =MCP_HDMI_HPD DP_IG_AUX_CH_P/N
TMDS_IG_TXC_P/N TMDS_IG_TXD_P/N TMDS_IG_TXD_P/N TMDS_IG_TXD_P/N TMDS_IG_DDC_CLK TMDS_IG_DDC_DATA TMDS_IG_HPD TP_DP_IG_AUX_CHP/N
DP_IG_ML_P/N DP_IG_ML_P/N DP_IG_ML_P/N DP_IG_ML_P/N DP_IG_DDC_CLK DP_IG_DDC_DATA DP_IG_HPD DP_IG_AUX_CH_P/N
NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used. NOTE: 20K pull-down required on DP_HPD_DET. NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used. NOTE: HDMI port requires level-shifting. IFP interface can be used to provide HDMI or dual-channel TMDS without level-shifters. LVDS: Power +VDD_IFPx at 1.8V Dual-channel TMDS: Power +VDD_IFPx at 3.3V
IN
/ / / /
9
OUT
9
OUT
9
OUT
9
OUT
9
OUT
9
OUT
9
OUT
9
OUT
9
OUT
9
OUT
9
OUT
89 80
OUT
89 80
OUT
9
IN
9
IN 25 8
25
25 8
89 25
OUT
89 25
OUT
LVDS_IG_BKL_PWM LVDS_IG_BKL_ON LVDS_IG_PANEL_PWR
E16 GPIO_6/FERR*/IGPU_GPIO_6 B15 GPIO_7/NFERR*/IGPU_GPIO_7
(See below)
=MCP_HDMI_TXC_P =MCP_HDMI_TXC_N
G39 LCD_BKL_CTL/GPIO_57 E37 LCD_BKL_ON/GPIO_59 F40 LCD_PANEL_PWR/GPIO_58 D35 HDMI_TXC_P/ML0_LANE3_P E35 HDMI_TXC_N/ML0_LANE3_N
=MCP_HDMI_TXD_P =MCP_HDMI_TXD_N =MCP_HDMI_TXD_P =MCP_HDMI_TXD_N =MCP_HDMI_TXD_P =MCP_HDMI_TXD_N
G35 F35 F33 G33 J33 H33
DP_IG_AUX_CH_P DP_IG_AUX_CH_N
D43 DP_AUX_CH0_P C43 DP_AUX_CH0_N
=DVI_HPD_GMUX_INT (See below) =MCP_HDMI_HPD
C31 HPLUG_DET2/GPIO_22 F31 HPLUG_DET3
=PP3V3R1V8_S0_MCP_IFP_VDD 190 mA (A01, 1.8V) PP3V3_S0_MCP_VPLL 16 mA (A01)
8 mA 8 mA
=PP1V05_S0_MCP_HDMI_VDD 95 mA (A01) MCP_HDMI_RSET MCP_HDMI_VPROBE
33 91
OUT
33 91
OUT
33 91
ENET_CLK125M_TXCLK ENET_TX_CTRL
OUT
33 91
OUT
33 91
ENET_MDC ENET_MDIO
OUT
33 91
BI
RGMII
1
MII
0
NOTE: All Apple products set strap to MII, RGMII products will enable feature via software. This avoids a leakage issue since MCP79 requires a S5 pull-up.
33 91
HDMI_TXD0_P/ML0_LANE2_P HDMI_TXD0_N/ML0_LANE2_N HDMI_TXD1_P/ML0_LANE1_P HDMI_TXD1_N/ML0_LANE1_N HDMI_TXD2_P/ML0_LANE0_P HDMI_TXD2_N/ML0_LANE0_N
M27 +VDD_IFPA M26 +VDD_IFPB M28 +V_PLL_IFPAB M29 +V_PLL_HDMI T25 +VDD_HDMI J31 HDMI_RSET J30 HDMI_VPROBE
MCP_CLK25M_BUF0_R
OUT
34 91
ENET_RESET_L
OUT
33 91
RGB_DAC_RED B39 RGB_DAC_GREEN A39 RGB_DAC_BLUE B40
TP_MCP_RGB_RED TP_MCP_RGB_GREEN TP_MCP_RGB_BLUE
RGB_DAC_HSYNC A40 RGB_DAC_VSYNC A41
TP_MCP_RGB_HSYNC TP_MCP_RGB_VSYNC
Component Pr TV_DAC_RED Y TV_DAC_GREEN Pb TV_DAC_BLUE
CRT_IG_R_C_PR CRT_IG_G_Y_Y CRT_IG_B_COMP_PB
A36 B36 C36
TV_DAC_HSYNC/GPIO_44 D36 TV_DAC_VSYNC/GPIO_45 C37
5% 1/16W MF-LF 402 2
LPCPLUS_GPIO DP_IG_CA_DET
33 91
OUT
IFPA_TXC_P B35 IFPA_TXC_N C35 IFPA_TXD0_P IFPA_TXD0_N IFPA_TXD1_P IFPA_TXD1_N IFPA_TXD2_P IFPA_TXD2_N IFPA_TXD3_P IFPA_TXD3_N
=PP3V3_S0_MCP_GPIO
R18601 100K 5% 1/16W MF-LF 402 2
8 19 21
1
R1861 100K
5% 1/16W MF-LF 2 402
MCP_DDC_CLK0 MCP_DDC_DATA0
DDC_CLK0 B31 DDC_DATA0 A31
FLAT PANEL
R1820
25
Interface ENET_TXD
OUT
PP3V3_S0_MCP_DAC 25 103 mA 206 mA (A01) 103 mA
+V_RGB_DAC J32 +V_TV_DAC K32
RGB ONLY
25
24
T23 +V_DUAL_MACPLL
DACS
1% 1/16W MF-LF 402 2
IN
TP_ENET_PWRDWN_L
RGMII_PWRDWN/GPIO_37 G23
49.9
1
ENET_TXD ENET_TXD ENET_TXD ENET_TXD
B24 C24 C25 D25
RGMII_TXCTL/MII_TXEN C26
R18111
20 8
Network Interface Select MCP_MII_VREF
BUF_25MHZ E23 91
D
=PP1V05_ENET_MCP_RMGT 8 24 131 mA (A01)
RGMII_TXC/MII_TXCLK D24
J22 RGMII_INTR/GPIO_35
PP1V05_ENET_MCP_PLL_MAC 5 mA (A01)
=PP3V3_ENET_MCP_RMGT 8 18 24 83 mA (A01)
MII_VREF E28 RGMII_TXD0 RGMII_TXD1 RGMII_TXD2 RGMII_TXD3
ENET_CLK125M_RXCLK ENET_RX_CTRL
TP_ENET_INTR_L
R18101
RGMII_RXD0 RGMII_RXD1 RGMII_RXD2 RGMII_RXD3
LAN
D
+3.3V_DUAL_RMGT1 J24 +3.3V_DUAL_RMGT2 K24
Okay to float all RGB_DAC signals. DDC_CLK0/DDC_DATA0 pull-ups still required.
25
25 25
TV DAC Disable: OUT
25 89
OUT
25 89
OUT
25 89
CRT_IG_HSYNC CRT_IG_VSYNC
OUT
25 89
OUT
25 89
LVDS_IG_A_CLK_P LVDS_IG_A_CLK_N
OUT
83 89
OUT
83 89
OUT
83 89
OUT
83 89
OUT
83 89
OUT
83 89
OUT
83 89
OUT
83 89
OUT
9 89
OUT
9 89
OUT
9 89
OUT
9 89
OUT
83 89
OUT
83 89
OUT
83 89
OUT
83 89
OUT
83 89
OUT
83 89
OUT
9 89
OUT
9 89
LVDS_IG_DDC_CLK LVDS_IG_DDC_DATA
OUT
80
=MCP_HDMI_DDC_CLK =MCP_HDMI_DDC_DATA
OUT
MCP_IFPAB_RSET MCP_IFPAB_VPROBE
OUT
25 89
OUT
25 89
LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N
B32 A32 D32 C32 D33 C33 B34 C34
C
RGB DAC Disable: 25 25
Okay to float all TV_DAC signals. Okay to float XTALIN_TV and XTALOUT_TV. DDC_CLK0/DDC_DATA0 pull-ups still required.
WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases LVDS_IG_B_CLK_P LVDS_IG_B_CLK_N
IFPB_TXC_P L31 IFPB_TXC_N K31 IFPB_TXD4_P IFPB_TXD4_N IFPB_TXD5_P IFPB_TXD5_N IFPB_TXD6_P IFPB_TXD6_N IFPB_TXD7_P IFPB_TXD7_N
LVDS_IG_B_DATA_P LVDS_IG_B_DATA_N LVDS_IG_B_DATA_P LVDS_IG_B_DATA_N LVDS_IG_B_DATA_P LVDS_IG_B_DATA_N LVDS_IG_B_DATA_P LVDS_IG_B_DATA_N
J29 H29 L29 K29 L30 K30 N30 M30
DDC_CLK2/GPIO_23 C30 DDC_DATA2/GPIO_24 B30 DDC_CLK3 D31 DDC_DATA3 E31 IFPAB_RSET E32 IFPAB_VPROBE G31
BI
BI
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BGA (6 OF 11)
B
80
9 9
1
R1850 10K
GPIOs 57-59 (if LCD panel is used):
5% 1/16W MF-LF 2 402
In MCP79 these pins have undocumented internal pull-ups (~10K to 3.3V S0). To ensure pins are low by default, pull-downs (1K or stronger) must be used.
A
MCP Ethernet & Graphics SYNC_MASTER=T18_MLB
SYNC_DATE=06/18/2008
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
=DVI_HPD_GMUX_INT: Alias to DVI_HPD for systems using IFP for DVI. Alias to GMUX_INT for systems with GMUX. Alias to HPLUG_DET2 for other systems. Pull-down (20k) required in all cases.
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
8
7
6
SCALE
SHT NONE
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
5
4
3
2
REV.
051-7546
A.0.0 OF
18
1
96
A
8
6
7
2
3
4
5
1
OMIT
U1400
21 18 8
=PP3V3_S0_MCP_GPIO
MCP79-TOPO-B BGA (7 OF 11)
59 9
D
OUT OUT
19
IN
90 13
BI
90 13
BI
90 13
BI
90 13
BI
90 13
BI
90 13
BI
90 13
BI
90 13
BI
C
MCP_DEBUG MCP_DEBUG MCP_DEBUG MCP_DEBUG MCP_DEBUG MCP_DEBUG MCP_DEBUG MCP_DEBUG TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD
AC3 AE10 AC4 AE11 AB3 AC6 AB2 AC7 AC8 AA2 AC9 AC10 AC11 AA1 AA5 Y5 W3 W6 W4 W7 V3 W8 V2 W9 U3 W11 U2 U5 U1 U6 T5 U7
TP_PCI_INTW_L TP_PCI_INTX_L TP_PCI_INTY_L TP_PCI_INTZ_L
P2 N3 N2 N1
TP_PCI_TRDY_L 44 42
IN
36
IN
44 42
BI
PM_CLKRUN_L FW_PME_L TP_LPC_DRQ0_L LPC_SERIRQ
PCI_REQ0# PCI_REQ1#/FANRPM2 PCI_REQ2#/GPIO_40/RS232_DSR# PCI_REQ3#/GPIO_38/RS232_CTS# PCI_REQ4#/GPIO_52/RS232_SIN# PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31
TP_PCI_GNT0_L TP_PCI_GNT1_L GMUX_JTAG_TMS GMUX_JTAG_TDI MCP_RS232_SOUT_L
PCI_CBE0# PCI_CBE1# PCI_CBE2# PCI_CBE3#
AA3 AA6 AA11 W10
TP_PCI_C_BE_L TP_PCI_C_BE_L TP_PCI_C_BE_L TP_PCI_C_BE_L
PCI_DEVSEL# PCI_FRAME# PCI_IRDY# PCI_PAR PCI_PERR#/GPIO_43/RS232_DCD# PCI_SERR# PCI_STOP#
AA9 Y4 AA10 Y1 AB9 AA7 Y2
TP_PCI_DEVSEL_L TP_PCI_FRAME_L TP_PCI_IRDY_L TP_PCI_PAR TP_PCI_PERR_L TP_PCI_SERR_L TP_PCI_STOP_L PM_LATRIGGER_L
PCI_PME#/GPIO_30 T1
90 19 90 19
OUT
9
OUT
9
OUT
19
OUT
13 23
OUT
26
19 19
MCP_RS232_SOUT_L
R1989
8.2K
1
2
PCI_REQ0_L PCI_REQ1_L CRTMUX_SEL_TV_L MCP_RS232_SIN_L
R1990 R1991 R1992 R1994
8.2K 8.2K 8.2K 8.2K
1 1 1 1
2 2 2 2
5%
1/16W MF-LF 402
5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF MF-LF
402 402 402 402
D
Int PU (S5) MEM_VTT_EN_R TP_PCI_RESET1_L
PCI_RESET0# R10 PCI_RESET1# R11
PCI_CLK0 R6 PCI_CLK1 R7 PCI_CLK2 R8
TP_PCI_CLK0 TP_PCI_CLK1 PCI_CLK33M_MCP_R
90
1
R1910 22
C
5% 1/16W MF-LF 2 402
PCI_CLKIN R9
PCI_INTW# PCI_INTX# PCI_INTY# PCI_INTZ#
Y3 PCI_TRDY#
PU
PCI_CLK33M_MCP
90
LPC_FRAME# AD4 LPC_PWRDWN#/GPIO_54/EXT_NMI# AE12
AD11 PCI_CLKRUN#/GPIO_42 AE2 LPC_DRQ1#/GPIO_19 Int AE1 LPC_DRQ0# Int PU AE6 LPC_SERIRQ Int PU
19
R3 U10 R4 U11 P3
PCI_GNT0# PCI_GNT1#/FANCTL2 PCI_GNT2#/GPIO_41/RS232_DTR# PCI_GNT3#/GPIO_39/RS232_RTS# PCI_GNT4#/GPIO_53/RS232_SOUT#
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19
T2 V9 T3 U9 T4
PCI
90 19
PCI_REQ0_L PCI_REQ1_L CRTMUX_SEL_TV_L AUD_IPHS_SWITCH_EN MCP_RS232_SIN_L
LPC
90 19
LPC_FRAME_R_L LPC_PWRDWN_L
44
LPC_RESET0# AE5
LPC_RESET_L
AD3 AD2 AD1 AD5
LPC_AD_R LPC_AD_R LPC_AD_R LPC_AD_R
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
PLACEMENT_NOTE=Place close to pin R8
R1960
R1950 R1951 R1952 R1953
22
1
LPC_FRAME_L
2 5%
22 22 22 22
1 1 1 1
2 2 2 2
5% 5% 5% 5%
1/16W MF-LF 402
1/16W 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF MF-LF
402 402 402 402
LPC_AD LPC_AD LPC_AD LPC_AD
42 44 83 90
OUT
42 44
OUT
26 83 90
BI
42 44 83 90
BI
42 44 83 90
BI
42 44 83 90
BI
LPC_CLK33M_SMC_R
LPC_CLK0 AE9
OUT
OUT
42 44 83 90
26 90
U24 U26 U39 U4 U8 V16 V17 V18 V20 V22 V24 V26 V27 V28 V33 V37 V4 V40 V7 W20 W22 W24 W36 W40 W43 Y16 Y17 Y18 Y19 Y20 Y22 Y24 Y25
B
A
GND65 GND66 GND67 GND68 GND69 GND70 GND71 GND72 GND73 GND74 GND75 GND76 GND77 GND78 GND79 GND80 GND81 GND82 GND83 GND84 GND85 GND86 GND87 GND88 GND89 GND90 GND91 GND92 GND93 GND94 GND95 GND96 GND97
GND
1
GND98 GND99 GND100 GND101 GND102 GND103 GND104 GND105 GND106 GND107 GND108 GND109 GND110 GND111 GND112 GND113 GND114 GND115 GND116 GND117 GND118 GND119 GND120 GND121 GND122 GND123 GND124 GND125 GND126 GND127 GND128 GND129 GND130
R1961
Y26 Y27 AB18 H34 AB20 AB21 AB23 AB24 AB25 AB26 AB27 AB28 AB34 AB37 AB4 AB40 AC22 AC36 AC40 AB33 AC5 AD16 AD17 AD18 AD19 AD20 AD24 AD25 AD26 AD27 AD28 AD33 AD34
10K
5% 1/16W MF-LF 2 402
Strap for Boot ROM Selection (See HDA_SDOUT)
B
MCP PCI & LPC SYNC_MASTER=T18_MLB
SYNC_DATE=06/18/2008
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
19
1
96
A
8
6
7
2
3
4
5
1
OMIT
U1400 MCP79-TOPO-B
89 39
OUT
89 39
OUT
89 39
IN
89 39
IN
SATA_HDD_R2D_C_P SATA_HDD_R2D_C_N
USB0_P C29 USB0_N D29
SATA_HDD_D2R_N SATA_HDD_D2R_P
AJ5 SATA_A0_RX_N AJ4 SATA_A0_RX_P
USB1_P C28 USB1_N D28
D
USB2_P A28 USB2_N B28 OUT
89 39
OUT
89 39 89 39
SATA_ODD_R2D_C_P SATA_ODD_R2D_C_N SATA_ODD_D2R_N SATA_ODD_D2R_P
IN IN
TP_SATA_C_R2D_CP TP_SATA_C_R2D_CN TP_SATA_C_D2RN TP_SATA_C_D2RP
USB4_P K27 USB4_N L27 USB5_P J26 USB5_N J27
AK2 SATA_B0_TX_P AJ3 SATA_B0_TX_N AJ2 SATA_B0_RX_N AJ1 SATA_B0_RX_P
AM4 SATA_B1_TX_P AL3 SATA_B1_TX_N
TP_SATA_D_D2RN TP_SATA_D_D2RP
AL4 SATA_B1_RX_N AK3 SATA_B1_RX_P
TP_SATA_E_D2RN TP_SATA_E_D2RP
USB3_P F29 USB3_N G29
AJ9 SATA_A1_RX_N AK9 SATA_A1_RX_P
TP_SATA_D_R2D_CP TP_SATA_D_R2D_CN
TP_SATA_E_R2D_CP TP_SATA_E_R2D_CN
C
AJ11 SATA_A1_TX_P AJ10 SATA_A1_TX_N
AN1 SATA_C0_TX_P AM1 SATA_C0_TX_N
USB6_P F27 USB6_N G27
SATA USB
89 39
USB7_P D27 USB7_N E27 USB8_P K25 USB8_N L25 USB9_P H25 USB9_N J25 USB10_P F25 USB10_N G25
TP_USB_10P TP_USB_10N
USB11_P K23 USB11_N L23
TP_USB_11P TP_USB_11N
AP3 SATA_C1_TX_P AP2 SATA_C1_TX_N
TP_SATA_F_D2RN TP_SATA_F_D2RP
AN3 SATA_C1_RX_N AN2 SATA_C1_RX_P
USB_OC0#/GPIO_25 USB_OC1#/GPIO_26 USB_OC2#/GPIO_27/MGPIO USB_OC3#/GPIO_28/MGPIO
8
PP1V05_S0_MCP_PLL_SATA 84 mA (A01) =PP1V05_S0_MCP_SATA_DVDD0 43 mA (A01, DVDD0 & 1)
Minimum 1.025V for Gen2 support
AE16 +V_PLL_SATA
AF19 AG16 AG17 AG19
+DVDD0_SATA1 +DVDD0_SATA2 +DVDD0_SATA3 +DVDD0_SATA4
AH17 +DVDD1_SATA1 AH19 +DVDD1_SATA2 8
=PP1V05_S0_MCP_SATA_AVDD0 127 mA (A01, AVDD0 & 1)
Minimum 1.025V for Gen2 support
AJ12 AN11 AK12 AK13 AL12 AM11 AM12 AN12 AL13
+AVDD0_SATA1 +AVDD0_SATA2 +AVDD0_SATA3 +AVDD0_SATA4 +AVDD0_SATA5 +AVDD0_SATA6 +AVDD0_SATA7 +AVDD0_SATA8 +AVDD0_SATA9
AN14 AL14 AM13 AM14
+AVDD1_SATA1 +AVDD1_SATA2 +AVDD1_SATA3 +AVDD1_SATA4
=PP1V05_S0_MCP_SATA_AVDD1
9
MCP_SATA_TERMP
89
40 90
BI
9 90
BI
9 90
BI
9 90
BI
9 90
BI
31 90
BI
31 90
BI
41 90
BI
41 90
BI
50 90
BI
50 90
BI
31 90
BI
31 90
BI
40 90
BI
40 90
BI
32 90
BI
32 90
BI
9 90
BI
9 90
+V_PLL_USB L28
D
=PP3V3_S5_MCP_GPIO
1
R2051 8.2K
5% 1/16W MF-LF 2 402
R20501 8.2K 5% 1/16W MF-LF 402 2
1
R2053 8.2K
5% 1/16W MF-LF 2 402
C
R20521 8.2K 5% 1/16W MF-LF 402 2
USB_EXTA_OC_L USB_EXTB_OC_L USB_EXTC_OC_L EXCARD_OC_L PP3V3_S0_MCP_PLL_USB 19 mA (A01) 90
8 18
IN
40
IN
40
IN IN
32 43
24
MCP_USB_RBIAS_GND
R20601 E12 SATA_LED#
=PP1V05_S0_MCP_SATA_DVDD1
9
B
40 90
BI
L21 K21 J21 H21
USB_RBIAS_GND A27
24
BI
AM2 SATA_C0_RX_N AM3 SATA_C0_RX_P
TP_SATA_F_R2D_CP TP_SATA_F_R2D_CN
TP_MCP_SATALED_L
External A USB_EXTA_P USB_EXTA_N AirPort (PCIe Mini-Card) USB_MINI_P USB_MINI_N External D USB_EXTD_P USB_EXTD_N Camera USB_CAMERA_P USB_CAMERA_N IR USB_IR_P USB_IR_N Geyser Trackpad/Keyboard USB_TPAD_P USB_TPAD_N Bluetooth USB_BT_P USB_BT_N External B USB_EXTB_P USB_EXTB_N ExpressCard USB_EXCARD_P USB_EXCARD_N External C USB_EXTC_P USB_EXTC_N
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BGA (8 OF 11) AJ7 SATA_A0_TX_P AJ6 SATA_A0_TX_N
AE3 SATA_TERMP
GND131 GND132 GND133 GND134 GND135 GND136 GND137 GND138 GND139 GND140 GND141 GND142 GND143 GND144 GND145 GND146 GND147 GND148 GND149 GND150 GND151 GND152 GND153 GND154 GND155 GND156 GND157 GND158 GND159 GND160
AD35 AD37 AD38 AE22 AE24 AE39 AE4 AD6 AF16 AF17 AF18 AF20 AF22 AF26 AF27 AF28 AF33 AF34 AF37 AF40 AG18 AG20 AG22 AG26 AG36 AG40 AH18 AH20 AH22 AH24
806 1% 1/16W MF-LF 402 2
B
1
R2010 2.49K
1% 1/16W MF-LF 2 402
If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA. If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.
MCP SATA & USB SYNC_MASTER=T18_MLB
A
SYNC_DATE=06/18/2008
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
8
7
6
SCALE
SHT NONE
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
5
4
3
2
REV.
051-7546
A.0.0 OF
20
1
96
A
8
6
7
2
3
4
5
1
OMIT
U1400
=PP3V3R1V5_S0_MCP_HDA 8 21 24 7 mA (A01)
MCP79-TOPO-B BGA (9 OF 11)
90 54
HDA_SDIN0
IN
G15 HDA_SDATA_IN0
Int PD TP_MLB_RAM_SIZE
R2160 8.2K
5% 1/16W MF-LF 2 402
HDA
D
1
HDA_SDATA_OUT F15
HDA_BITCLK E15
HDA_BIT_CLK_R
90 21
1
Int PD TP_MLB_RAM_VENDOR (MXM_OK for MXM systems)
=PP3V3R1V5_S0_MCP_HDA
24 21 8
J15 HDA_SDATA_IN2/GPIO_3/PS2_KB_DATA
HDA_RESET# K15
HDA_SYNC_R
90 21
1
PP3V3_G3_RTC 44 9 43 42 37 34
1% 1/16W MF-LF 402 2
OUT IN
1
R2121 49.9K
1% 1/16W MF-LF 2 402
42 23
IN
42 23
IN
MCP_HDA_PULLDN_COMP
A15 HDA_PULLDN_COMP
PP1V05_S0_MCP_PLL_NV 37 mA (A01) 20 mA 17 mA =SPI_CS1_R_L_USE_MLB SMC_ADAPTER_EN TP_SB_A20GATE TP_MCP_KBDRSTIN_L SMC_WAKE_SCI_L SMC_RUNTIME_SCI_L
K13 L13 C19 C18
SM_INTRUDER_L
B20 INTRUDER#
IN
PM_DPRSLPVR
M22 CPU_DPRSLPVR
42 23
IN
26 23
IN
PM_PWRBTN_L PM_SYSRST_DEBOUNCE_L
C16 PWRBTN# D16 RSTBTN#
RTC_RST_L
C20 RTC_RST#
M25 LID# M24 LLB#
IN
26
IN
MCP_CPU_VLD
C17 CPU_VLD
JTAG_MCP_TDI JTAG_MCP_TDO JTAG_MCP_TMS JTAG_MCP_TRST_L JTAG_MCP_TCK
E19 F19 J19 J18 G19
MCP_CLK25M_XTALIN MCP_CLK25M_XTALOUT
A16 XTALIN B16 XTALOUT
RTC_CLK32K_XTALIN RTC_CLK32K_XTALOUT
A19 XTALIN_RTC B19 XTALOUT_RTC
IN OUT
23 13 6
IN
13 6
IN
13 6
IN
26
IN
26
OUT
26
IN
26
OUT
(S5)
R21501 10K 5% 1/16W MF-LF 402 2
D20 PWRGD_SB E20 PS_PWRGD
SMB_CLK0 SMB_DATA0 SMB_CLK1/MSMB_CLK SMB_DATA1/MSMB_DATA SMB_ALERT#/GPIO_64
(MGPIO2) (MGPIO3)
FANRPM0/GPIO_60 FANCTL0/GPIO_61 FANRPM1/GPIO_63 FANCTL1/GPIO_62
SMBUS_MCP_0_CLK SMBUS_MCP_0_DATA SMBUS_MCP_1_CLK SMBUS_MCP_1_DATA AP_PWR_EN
B12 A12 D12 C12
MEM_EVENT_L ODD_PWR_EN_L SMC_IG_THROTTLE_L ARB_DETECT
JTAG_TDI Int JTAG_TDO JTAG_TMS Int JTAG_TRST# JTAG_TCK
OUT
C2172
PU
SPI_CS0/GPIO_10 SPI_CLK/GPIO_11 SPI_DI/GPIO_8 SPI_DO/GPIO_9
PU
10PF
5% 50V 2 CERM 402
9
OUT
OUT
48 95
OUT
48 95
OUT
21 65
OUT
21 65
OUT
21 65
IN OUT IN
100K 5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 2 402
21 90
R2141 10K
5% 1/16W MF-LF 2 402
SPI0
1
0
SPI1
1
1
NOTE: MCP79 does not support FWH, only LPC ROMs. So Apple designs will not use LPC for BootROM override. =PP3V3_S0_MCP BOOT_MODE_SAFE
NOTE: MCP79 rev A01 does not support SPI1 option. Rev B01 will.
8 22 24
1
R2142 10K
5% 1/16W MF-LF 2 402
R2180
BUF_SIO_CLK Frequency
10K 5% 1/16W MF-LF 2 402
Frequency 9
R2181
7 13 45 90
10K 5% 1/16W MF-LF 2 402
7 13 45 90
45 90 21 31 34
Connects to SMC for automatic recovery.
ARB_DETECT
39
31 MHz
0
0
42 MHz
0
1
25 MHz
1
0
1 MHz
1
1
21 43
OUT
26
OUT
44 90
OUT
44 90
IN
44 90
OUT
44 90
OUT
26 90
NOTE: Straps not provided on this page.
8
R2154 100K
5% 1/16W MF-LF 1 402
AP_PWR_EN
21
21 31 34
21 59
MCP HDA & MISC
21 28 29 42
MCP_VID MCP_VID MCP_VID
21 43
21
1
R2155
5% 1/16W MF-LF 2 402
5% 50V 2 CERM 402
Frequency SPI_DO SPI_CLK
21 28 29 42
2
R2147
10PF
SPI Frequency Select
8 18 19
1
C2173
0
1% 1/16W MF-LF 2 402
5% 1/16W MF-LF 2 402
MCP_GPIO_4 AUD_I2C_INT_L MEM_EVENT_L SMC_IG_THROTTLE_L
14.31818 MHz
1K
10K
21 90
1
R2190
R2143
21 90
USER mode: Normal SAFE mode: For ROMSIP recovery
1
R2156
21 65
SYNC_MASTER=T18_MLB
NOTICE OF PROPRIETARY PROPERTY
21 65
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
1
R2157
22K
22K
22K
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 2 402
SYNC_DATE=06/18/2008
21 65
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
7
6
5
4
3
2
REV.
051-7546
SCALE
SHT NONE
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
8
HDA_SYNC
24 MHz
1
1
21 90
C
1
=PP3V3_S3_MCP_GPIO
10K
1
B
5% 1/16W MF-LF 2 402
R2140
0
21
10K
1
0
PCI
R1961 and R2160 selects SPI0 ROM by default, LPC+ debug card pulls LPC_FRAME# high for SPI1 ROM override.
45 90
BI OUT
R2163
1
LPC_FRAME#
0
MCP_TEST_MODE_EN
100K
C2171
54 90
7 34 37 42 44 68 81 83
BI
1
1
OUT
21 59
40 42 43 68
OUT
PM_CLK32K_SUSCLK_R TP_MCP_BUF_SIO_CLK
TEST_MODE_EN K22 PKG_TEST L22
5% 50V CERM 2 402
1
HDA_SYNC
5% 1/16W MF-LF 402
OUT
OUT
SPI_CS0_R_L SPI_CLK_R SPI_MISO SPI_MOSI_R
C14 D13 C15 B14
SUS_CLK/GPIO_34 B18 BUF_SIO_CLK AE7
10PF
5% 50V CERM 2 402
54 90
HDA_SDOUT
LPC
1
MCP_CPUVDD_EN
R2151
For EMI Reduction on HDA interface
10PF
OUT
OUT
L19 K19 G21 F21 M23
1
HDA Output Caps
C2170
HDA_RST_L
MCP_SPKR
CPUVDD_EN D17
=PP3V3_S0_MCP_GPIO
A
2
I/F
SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L IN
1
1
9 90
BOOT_MODE_USER
Int PU (S5) Int PU
26
B
HDA_RST_R_L HDA_SYNC_R
OUT
21
MCP_VID MCP_VID MCP_VID
MCP_VID0/GPIO_13 L20 MCP_VID1/GPIO_14 M20 MCP_VID2/GPIO_15 M21
Int PU (S5) Int PU (S5)
PM_RSMRST_L MCP_PS_PWRGD
6
HDA_SDOUT_R HDA_BIT_CLK_R
BIOS Boot Select
2
MCP_THMDIODE_P MCP_THMDIODE_N
SPKR C13
IN
23 13 6
PM_SLP_S3_L PM_SLP_RMGT_L PM_SLP_S4_L
THERM_DIODE_P B11 THERM_DIODE_N C11
A20GATE Int PU KBRDRSTIN# Int PU SIO_PME# Int PU (S5) EXT_SMI/GPIO_32# Int PU
87 62
IN
SLP_S3# G17 SLP_RMGT# J17 SLP_S5# H17
L24 GPIO_1/PWRDN_OK/SPI_CS1 L26 GPIO_12/SUS_STAT#/ACCLMTR
42 23
42
MCP_GPIO_4 AUD_I2C_INT_L
AE18 +V_PLL_NV_H AE17 +V_PLL_SP_SPREF
TP_MCP_LID_L PM_BATLOW_L
23
HDA_DOCK_EN#/GPIO_4/PS2_MS_CLK K17 HDA_DOCK_RST#/GPIO_5/PS2_MS_DATA L17
MISC
24
49.9K
22
54 90
5% 1/16W MF-LF 402 90
C
22
R2173 HDA_SYNC L15
OUT
R2172 1
1% 1/16W MF-LF 2 402
HDA_SDOUT
HDA_BIT_CLK
2
Int PD
49.9
2
5% 1/16W MF-LF 402
HDA_RST_R_L
90 21
R2110
R21201
22
5% 1/16W MF-LF 402
1
26 22
22
1
R2171
J14 HDA_SDATA_IN1/GPIO_2/PS2_KB_CLK
D
R2170 HDA_SDOUT_R
90 21
www.laptop-schematics.com
+V_DUAL_HDA1 J16 +V_DUAL_HDA2 K16
A.0.0 OF
21
1
96
A
8
7
6
OMIT
OMIT
U1400
U1400
B
A
=PPVCORE_S0_MCP 23065 mA (A01, 1.2V) 16996 mA (A01, 1.0V)
BGA (10 OF 11)
46 24 8
AV40 BA1 BA4 AW31 AY6 L35 BC33 BC37 BC41 AY14 BC5 C2 D10 D14 D15 D18 D19 D22 D23 D26 D30 D37 D6 E13 E17 E21 E25 E29 E33 F12 F16 F32 F8 G10 G12 G14 G16 BC12 G22 G24 AW20 G34 G4 G43 G6 G8 H11 H15 AW35 H23 AN8 G40 J12 J8 K10 K12 K18 K26 K37 K4 K40 K8 AU1 L40 L43 L5 M10 M34 M35 M37 Y28 Y33 Y34 Y35 Y37 Y38 AB17 AB16 AN26 AD7 M11 AA4 AB19 AY13 P11 Y6 T11 V11 Y11 AH16 T22
26 21
PP3V3_G3_RTC 10 uA (G3) 80 uA (S0)
AA25 AC23 U25 AH12 AG10 AG5 Y21 Y23 AA16 AA26 AA27 AA28 AC16 AC17 AC18 AC19 AC20 AC21 AA17 AC24 AC25 AC26 AC27 AC28 AD21 AD23 W27 V25 AA18 AE19 AE21 AE23 AE25 AE26 AE27 AE28 AF10 AF11 AA19 AF2 AF21 AF23 AF25 AF3 AF4 AF7 AH23 AF9 AA20 AG11 AG12 AG21 AG23 AG25 AG3 AG4 AA21 AG6 AG7 AG8 AG9 AH1 AH10 AH11 W26 AH2 AA23 W28 AH25 AH21 AH3 AH4 AH5 AH6 AH7 AH9 AA24 W21 W23 W25 AF12
+VDD_CORE1 +VDD_CORE2 +VDD_CORE3 +VDD_CORE4 +VDD_CORE5 +VDD_CORE6 +VDD_CORE7 +VDD_CORE8 +VDD_CORE9 +VDD_CORE10 +VDD_CORE11 +VDD_CORE12 +VDD_CORE13 +VDD_CORE14 +VDD_CORE15 +VDD_CORE16 +VDD_CORE17 +VDD_CORE18 +VDD_CORE19 +VDD_CORE20 +VDD_CORE21 +VDD_CORE22 +VDD_CORE23 +VDD_CORE24 +VDD_CORE25 +VDD_CORE26 +VDD_CORE27 +VDD_CORE28 +VDD_CORE29 +VDD_CORE30 +VDD_CORE31 +VDD_CORE32 +VDD_CORE33 +VDD_CORE34 +VDD_CORE35 +VDD_CORE36 +VDD_CORE37 +VDD_CORE38 +VDD_CORE39 +VDD_CORE40 +VDD_CORE41 +VDD_CORE42 +VDD_CORE43 +VDD_CORE44 +VDD_CORE45 +VDD_CORE46 +VDD_CORE47 +VDD_CORE48 +VDD_CORE49 +VDD_CORE50 +VDD_CORE51 +VDD_CORE52 +VDD_CORE53 +VDD_CORE54 +VDD_CORE55 +VDD_CORE56 +VDD_CORE57 +VDD_CORE58 +VDD_CORE59 +VDD_CORE60 +VDD_CORE61 +VDD_CORE62 +VDD_CORE63 +VDD_CORE64 +VDD_CORE65 +VDD_CORE66 +VDD_CORE67 +VDD_CORE68 +VDD_CORE69 +VDD_CORE70 +VDD_CORE71 +VDD_CORE72 +VDD_CORE73 +VDD_CORE74 +VDD_CORE75 +VDD_CORE76 +VDD_CORE77 +VDD_CORE78 +VDD_CORE79 +VDD_CORE80 +VDD_CORE81
A20 +VBAT
POWER
C
GND
D
GND253 GND254 GND255 GND256 GND257 GND258 GND259 GND260 GND261 GND262 GND263 GND264 GND265 GND266 GND267 GND268 GND269 GND270 GND271 GND272 GND273 GND274 GND275 GND276 GND277 GND278 GND279 GND280 GND281 GND282 GND283 GND284 GND285 GND286 GND287 GND288 GND289 GND290 GND291 GND292 GND293 GND294 GND295 GND296 GND297 GND298 GND299 GND300 GND301 GND302 GND303 GND304 GND305 GND306 GND307 GND308 GND309 GND310 GND311 GND312 GND313 GND314 GND315 GND316 GND317 GND318 GND319 GND320 GND321 GND322 GND323 GND324 GND325 GND326 GND327 GND328 GND329 GND330 GND331 GND332 GND333 GND334 GND335 GND336 GND337 GND338 GND339 GND340 GND341 GND342 GND343
1
MCP79-TOPO-B
BGA (11 OF 11) GND161 GND162 GND163 GND164 GND165 GND166 GND167 GND168 GND169 GND170 GND171 GND172 GND173 GND174 GND175 GND176 GND177 GND178 GND179 GND180 GND181 GND182 GND183 GND184 GND185 GND186 GND187 GND188 GND189 GND190 GND191 GND192 GND193 GND194 GND195 GND196 GND197 GND198 GND199 GND200 GND201 GND202 GND203 GND204 GND205 GND206 GND207 GND208 GND209 GND210 GND211 GND212 GND213 GND214 GND215 GND216 GND217 GND218 GND219 GND220 GND221 GND222 GND223 GND224 GND225 GND226 GND227 GND228 GND229 GND230 GND231 GND232 GND233 GND234 GND235 GND236 GND237 GND238 GND239 GND240 GND241 GND242 GND243 GND244 GND245 GND246 GND247 GND248 GND249 GND250 GND251 GND252
2
+VTT_CPU1 +VTT_CPU2 +VTT_CPU3 +VTT_CPU4 +VTT_CPU5 +VTT_CPU6 +VTT_CPU7 +VTT_CPU8 +VTT_CPU9 +VTT_CPU10 +VTT_CPU11 +VTT_CPU12 +VTT_CPU13 +VTT_CPU14 +VTT_CPU15 +VTT_CPU16 +VTT_CPU17 +VTT_CPU18 +VTT_CPU19 +VTT_CPU20 +VTT_CPU21 +VTT_CPU22 +VTT_CPU23 +VTT_CPU24 +VTT_CPU25 +VTT_CPU26 +VTT_CPU27 +VTT_CPU28 +VTT_CPU29 +VTT_CPU30 +VTT_CPU31 +VTT_CPU32 +VTT_CPU33 +VTT_CPU34 +VTT_CPU35 +VTT_CPU36 +VTT_CPU37 +VTT_CPU38 +VTT_CPU39 +VTT_CPU40 +VTT_CPU41 +VTT_CPU42 +VTT_CPU43 +VTT_CPU44 +VTT_CPU45 +VTT_CPU46 +VTT_CPU47 +VTT_CPU48 +VTT_CPU49 +VTT_CPU50 +VTT_CPU51 +VTT_CPU52
R32 AC32 E40 J36 N32 T32 U32 V32 W32 P31 AF32 AE32 AH32 AJ32 AK31 AK32 AD32 AL31 AB32 B41 B42 C40 C41 C42 D39 D40 D41 E38 E39 F37 F38 F39 G36 G37 G38 H35 H37 J34 J35 K33 K34 K35 L32 L33 L34 M31 M32 M33 N31 P32 Y32 AA32
+VTT_CPUCLK AG32
=PP1V05_S0_MCP_FSB 8 9 14 24 1139 mA 1182 mA (A01)
D
C
43 mA
=PP3V3_S0_MCP +3.3V_1 +3.3V_2 +3.3V_3 +3.3V_4 +3.3V_5 +3.3V_6 +3.3V_7 +3.3V_8
AD10 AE8 AB10 AD9 Y10 AB11 AA8 Y9
+3.3V_DUAL1 +3.3V_DUAL2 +3.3V_DUAL3 +3.3V_DUAL4
G18 H19 J20 K20
+3.3V_DUAL_USB1 +3.3V_DUAL_USB2 +3.3V_DUAL_USB3 +3.3V_DUAL_USB4
G26 H27 J28 K28
www.laptop-schematics.com
MCP79-TOPO-B AH26 AH33 AH34 AH37 AH38 AJ39 AJ8 AK10 AK33 AK34 AK37 AK4 AK40 AL36 AL40 AL5 AM10 AM16 AM18 AM20 AM22 AM24 AM26 AM30 AM34 AM35 AM37 AM38 AM5 AM6 AM7 AM9 AP26 AN28 AN30 AN39 AN4 Y7 AP10 AU26 AP14 AU14 AP28 AP32 AP34 AP36 AP37 AP4 AP40 AP7 AW23 AR28 AR32 AR40 AT10 AR12 AT13 AT29 AT33 AT6 AT7 AT9 AY21 AY22 L12 AU12 AU28 AP33 AU32 AR30 AU36 AU38 AU4 G28 F20 AV28 AV32 AV36 AV4 AV7 AW11 G20 AR43 AW43 AY10 AV12 AY30 AY33 AY34 AY37 AY38 AY41
3
4
5
8 21 24
450 mA (A01)
B
=PP3V3_S5_MCP 16 mA
8 24
266 mA (A01)
250 mA
=PP1V05_S5_MCP_VDD_AUXC 8 24 105 mA (A01)
+VDD_AUXC1 T21 +VDD_AUXC2 U21 +VDD_AUXC3 V21
MCP Power & Ground SYNC_MASTER=T18_MLB
SYNC_DATE=06/18/2008
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
8
7
6
SCALE
SHT NONE
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
5
4
3
2
REV.
051-7546
A.0.0 OF
22
1
96
A
8
7
6
3
4
5
2
1
D
www.laptop-schematics.com
D
3.3V Interface Pull-ups These internal pull-ups are missing in Revs A01 & A01P. 44 8
C
19 13
OUT
PM_LATRIGGER_L
32 31 17
OUT
PCIE_WAKE_L
21 13 6
OUT
JTAG_MCP_TDI
21 13 6
OUT
JTAG_MCP_TMS
26 21
OUT
PM_SYSRST_DEBOUNCE_L
21
OUT
TP_MCP_LID_L MCP_LID_L MAKE_BASE=TRUE
42 21
OUT
SMC_WAKE_SCI_L
42 21
OUT
SMC_RUNTIME_SCI_L
42 21
OUT
PM_PWRBTN_L
42 21
OUT
PM_BATLOW_L
=PP3V3_S5_MCP_A01
MCP_A01&MCP_A01P&MCP_A01Q R2400 10K 1 2 5% 1/16W MF-LF MCP_A01&MCP_A01P&MCP_A01Q R2401 10K 1 2 5% 1/16W MF-LF MCP_A01&MCP_A01P&MCP_A01Q R2402 10K 1 2 5% 1/16W MF-LF MCP_A01&MCP_A01P&MCP_A01Q R2403 10K 1 2 5% 1/16W MF-LF MCP_A01&MCP_A01P&MCP_A01Q R2404 10K 1 2 5% 1/16W MF-LF MCP_A01&MCP_A01P&MCP_A01Q R2405 10K 1 2 5%
402 402 402
C
402
1/16W MF-LF 402
MCP_A01&MCP_A01P&MCP_A01Q R2410 10K 1 2 5% 1/16W MF-LF MCP_A01&MCP_A01P&MCP_A01Q R2411 10K 1 2 5% 1/16W MF-LF MCP_A01&MCP_A01P&MCP_A01Q R2412 10K 1 2 5% 1/16W MF-LF MCP_A01&MCP_A01P&MCP_A01Q R2413 10K 1 2 5%
402
402 402 402
1/16W MF-LF 402
B
B
MCP79 A01 Silicon Support SYNC_MASTER=T18_MLB
A
SYNC_DATE=03/31/2008
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
23
1
96
A
8
D
C2500 1
C2501 1
C2502 1
C2503 1
20% 4V X5R 2 402
20% 4V X5R 2 402
20% 4V X5R 2 402
20% 4V X5R 2 402
4.7UF
4.7UF
4.7UF
1
4.7UF
C2504
1
1UF
C2505
1
1UF
10% 2 10V X5R 402-1
C2506
1
1UF
10% 2 10V X5R 402-1
MCP PCIE (DVDD) Power 8
1
NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF) Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)
=PPVCORE_S0_MCP 23065 mA (A01, 1.2V) 16996 mA (A01, 1.0V)
(No IG vs. EG data)
2
3
4
5
C2507
1
1UF
10% 2 10V X5R 402-1
C2508
1
0.1UF
10% 2 10V X5R 402-1
C2509 0.1UF
20% 2 10V CERM 402
20% 2 10V CERM 402
1
C2510 0.1UF
20% 2 10V CERM 402
1
C2511
1
0.1UF
C2512 0.1UF
20% 10V 2 CERM 402
20% 2 10V CERM 402
1
C2513 0.1UF
20% 2 10V CERM 402
MCP SATA (DVDD) Power
=PP1V05_S0_MCP_PEX_DVDD 57 mA (A01)
8
L2570
=PP1V05_S0_MCP_SATA_DVDD 43 mA (A01)
8
=PP1V05_S0_MCP_AVDD_UF 333 mA (A01)
30-OHM-5A 1
2
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF) Apple: 5x 2.2uF 0402 (11 uF) PP1V05_S0_MCP_PEX_AVDD 8 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM 206 mA (A01) VOLTAGE=1.05V
0603
C2515
1
1
4.7UF
1UF
20% 4V X5R 2 402
22 8
C2516
1
C2517
1
1UF
10% 2 10V X5R 402-1
C2518
1
0.1uF
C2520
0.1uF
20% 2 10V CERM 402
10% 2 10V X5R 402-1
C2519
1
1
4.7UF
MCP 1.05V AUX Power
MCP 1.05V RMGT Power
=PP1V05_S5_MCP_VDD_AUXC 105 mA (A01)
=PP1V05_ENET_MCP_RMGT 131 mA (A01)
18 8
C2521
1
0.1uF
20% 4V X5R 2 402
20% 2 10V CERM 402
C2570 2.2UF
20% 2 10V CERM 402
20% 2 6.3V CERM 402-LF
C2525
1
1
0.1uF
MCP FSB (VTT) Power
C2528
0.1uF
20% 10V 2 CERM 402
22 14 9 8
C2526
1
1
4.7uF
20% 10V 2 CERM 402
2
1
20% 2 6.3V CERM 402-LF
8
C
1
C2530
1
2.2UF
C2531
1
2.2UF
20% 2 6.3V CERM 402-LF
C2532 2.2UF
20% 2 6.3V CERM 402-LF
20% 2 6.3V CERM 402-LF
1
C2533 2.2UF
20% 2 6.3V CERM 402-LF
1
C2534 2.2UF
20% 2 6.3V CERM 402-LF
1
C2535 2.2UF
20% 2 6.3V CERM 402-LF
1
=PP1V05_S0_MCP_PLL_UF 562 mA (A01)
R2580 0.2
1
1% 1/6W MF 402-HF
C2536
20% 2 6.3V CERM 402-LF
4.7UF
20% 4V X5R 2 402
2.2UF
20% 2 6.3V CERM 402-LF
1
MCP 3.3V Power =PP3V3_S0_MCP 450 mA (A01)
C2541
1
0.1UF
20% 4V X5R 2 402
C2542
1
0.1UF
20% 2 10V CERM 402
C2543
1
0.1UF
20% 2 10V CERM 402
C2544
1
0.1UF
20% 2 10V CERM 402
C2545 0.1UF
20% 2 10V CERM 402
20% 2 10V CERM 402
NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF) Apple: 4x 2.2uF 0402 (8.8 uF)
1
C2546 0.1UF
20% 2 10V CERM 402
1
C2547 0.1UF
20% 2 10V CERM 402
1
C2548
=PP3V3_S0_MCP_PLL_UF 19 mA (A01)
2
30-OHM-1.7A 1
2
1
2.2UF
2.2UF
20% 2 6.3V CERM 402-LF
B MCP 3.3V AUX/USB Power =PP3V3_S5_MCP 266 mA (A01)
C2551
20% 2 6.3V CERM 402-LF
1
C2552 2.2UF
20% 2 6.3V CERM 402-LF
1
20% 4V X5R 2 402
C2573 2.2UF
20% 2 6.3V CERM 402-LF
1
C2574 2.2UF
20% 2 6.3V CERM 402-LF
1
C2576 2.2UF
20% 6.3V 2 CERM 402-LF
C
C2581 2.2UF
20% 2 6.3V CERM 402-LF
24 18 8
=PP3V3_ENET_MCP_RMGT 83 mA (A01)
2 0402
C2584 1
C2555
4.7UF
20% 4V X5R 2 402
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) Apple: 1x 2.2uF 0402 (2.2 uF) 1
C2583 0.1UF
20% 2 10V CERM 402
PP1V05_S0_MCP_PLL_SATA 20 84 mA (A01)
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V 1
C2585 0.1UF
20% 2 10V CERM 402
B L2586
30-OHM-1.7A 1
2 0402
C2560
1
L2584
1
20% 2 6.3V CERM 402-LF
MCP 3.3V Ethernet Power
PP1V05_S0_MCP_PLL_PEX 17 84 mA (A01)
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
30-OHM-1.7A
2.2UF
20% 2 6.3V CERM 402-LF
C2564
C2586 1
2.2UF
20% 2 6.3V CERM 402-LF
=PP3V3R1V5_S0_MCP_HDA 7 mA (A01)
4.7UF
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) Apple: 1x 2.2uF 0402 (2.2 uF) PP3V3_S0_MCP_PLL_USB 20 MIN_LINE_WIDTH=0.4 MM 19 mA (A01) MIN_NECK_WIDTH=0.2 MM 1
2.2UF
2.2UF
MCP 3.3V/1.5V HDA Power
C2582 1
20% 2 10V CERM 402
VOLTAGE=3.3V
C2553
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) Apple: 1x 2.2uF 0402 (2.2 uF) 1
C2549 0.1UF
20% 2 10V CERM 402
0402
C2550
1
0.1UF
L2555
8
1
4.7UF
20% 2 6.3V CERM 402-LF
20% 4V X5R 2 402
PP1V05_S0_MCP_PLL_CORE 16 87 mA (A01)
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V 1
C2587 0.1UF
20% 2 10V CERM 402
L2588
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) Apple: 1x 2.2uF 0402 (2.2 uF)
30-OHM-1.7A 1
PP1V05_S0_MCP_PLL_NV 21 37 mA (A01)
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
2 0402
1
C2562
C2588 1
2.2UF
4.7UF
MCP79 Ethernet VRef
20% 2 6.3V CERM 402-LF
24 18 8
20% 4V X5R 2 402
1
C2589 0.1UF
20% 2 10V CERM 402
1
C2590 0.1UF
20% 2 10V CERM 402
=PP3V3_ENET_MCP_RMGT
R25911
MCP Standard Decoupling
1.47K
A
1% 1/16W MF-LF 402 2
L2595
8
1
L2582
1
4.7UF
21 8
1
30-OHM-1.7A
=PP1V8R1V5_S0_MCP_MEM 4771 mA (A01, DDR3)
C2540 1
22 8
C2572
PP1V05_S0_MCP_PLL_FSB 14 270 mA (A01)
0402
22 21 8
2.2UF
20% 2 6.3V CERM 402-LF
1
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
2
C2580 1
2.2UF
MCP Memory Power 16 8
C2575 2.2UF
20% 10V 2 CERM 402
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF) Apple: 7x 2.2uF 0402 (15.4 uF)
=PP1V05_S0_MCP_FSB 1182 mA (A01)
C2571
VOLTAGE=1.05V
C2529 0.1uF
20% 4V X5R 2 402
1
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF) Apple: 2x 2.2uF 0402 (4.4 uF) PP1V05_S0_MCP_SATA_AVDD 8 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM 127 mA (A01)
L2575
30-OHM-5A 0603
1
=PP1V05_ENET_MCP_PLL_MAC 5 mA (A01)
30-OHM-1.7A 1
2 0402
C2595 1 4.7UF
20% 4V X5R 2 402
SYNC_MASTER=T18_MLB
MCP_MII_VREF
R25901
C2596
1.47K
1% 1/16W MF-LF 402 2
0.1UF
20% 2 10V CERM 402
SYNC_DATE=06/18/2008
NOTICE OF PROPRIETARY PROPERTY
PP1V05_ENET_MCP_PLL_MAC 18 5 mA (A01)
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V 1
1
OUT
18
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
C2591
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
0.1UF
II NOT TO REPRODUCE OR COPY IT
20% 10V 2 CERM 402
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
7
6
5
4
3
2
REV.
051-7546
SCALE
SHT NONE
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
8
D
www.laptop-schematics.com
MCP Core Power 46 22 8
6
7
A.0.0 OF
24
1
96
A
8
6
7
5
2
3
4
1
WF: Checklist says 0-ohm resistor placeholder for ferrite bead. NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) Apple: 1x 2.2uF 0402 (2.2 uF)
L2650
8
1
30-OHM-1.7A
=PP3V3_S0_MCP_DAC_UF 206 mA (A01)
1
C2610
2 0402
NV: 1x 4.7uF 0603, 2x 0.1uF 0402 (4.9 uF) Apple: 2x 2.2uF 0402 (4.4 uF) PP3V3_S0_MCP_DAC 18 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM 206 mA (A01) VOLTAGE=3.3V NO STUFF
2.2UF
1
20% 2 6.3V CERM 402-LF
D
18 8
C2650 2.2UF
20% 2 6.3V CERM 402-LF
1
R2651 0
5% 1/16W MF-LF 2 402
D
=PP1V05_S0_MCP_HDMI_VDD 95 mA (A01)
C2615 1
1
4.7UF
89 18
C
MCP_HDMI_RSET MCP_HDMI_VPROBE NO STUFF
C2620 1 0.1UF
20% 10V CERM 2 402
8
=PP3V3_S0_MCP_VPLL_UF 16 mA (A01)
C2616 2.2UF
20% 4V X5R 2 402
89 18
www.laptop-schematics.com
18 8
NO STUFF
=PP3V3R1V8_S0_MCP_IFP_VDD 190 mA (A01, 1.8V)
20% 6.3V 402-LF
2 CERM
89 18 89 18
1
R2620
MCP_IFPAB_RSET MCP_IFPAB_VPROBE NO STUFF
C2630 1
1K
1% 1/16W MF-LF 2 402
0.1UF
20% 10V CERM 2 402
18
TP_MCP_RGB_RED
18
TP_MCP_RGB_GREEN
18
TP_MCP_RGB_BLUE
18
TP_MCP_RGB_HSYNC
NC_MCP_RGB_HSYNC MAKE_BASE=TRUE
18
TP_MCP_RGB_VSYNC
NC_MCP_RGB_VSYNC
89 18
CRT_IG_R_C_PR
NC_CRT_IG_R_C_PR MAKE_BASE=TRUE
89 18
CRT_IG_G_Y_Y
NC_CRT_IG_G_Y_Y
89 18
CRT_IG_B_COMP_PB
NC_CRT_IG_B_COMP_PB MAKE_BASE=TRUE
89 18
CRT_IG_HSYNC
NC_CRT_IG_HSYNC MAKE_BASE=TRUE
89 18
CRT_IG_VSYNC
NC_CRT_IG_VSYNC MAKE_BASE=TRUE
NO STUFF 1
R2630 1K
1% 1/16W MF-LF 2 402
WF: Checklist says 0-ohm resistor placeholder for ferrite bead. NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) L2640 Apple: ??? 30-OHM-1.7A PP3V3_S0_MCP_VPLL 18 MIN_LINE_WIDTH=0.4 MM 1 2 MIN_NECK_WIDTH=0.2 MM 16 mA (A01)
C2640 1
1
4.7UF
C2641
NC_MCP_RGB_GREEN MAKE_BASE=TRUE
NC_MCP_RGB_BLUE MAKE_BASE=TRUE
MAKE_BASE=TRUE
C
MAKE_BASE=TRUE
18
TP_MCP_RGB_DAC_RSET
NC_MCP_RGB_DAC_RSET MAKE_BASE=TRUE
18
TP_MCP_RGB_DAC_VREF
NC_MCP_RGB_DAC_VREF MAKE_BASE=TRUE
89 18
MCP_TV_DAC_RSET
NC_MCP_TV_DAC_RSET MAKE_BASE=TRUE
89 18
MCP_TV_DAC_VREF
NC_MCP_TV_DAC_VREF MAKE_BASE=TRUE
VOLTAGE=3.3V
0402
NC_MCP_RGB_RED MAKE_BASE=TRUE
0.1uF
20% 6.3V 2 CERM 603
20% 2 10V CERM 402
18
MCP_CLK27M_XTALIN
NC_MCP_CLK27M_XTALIN MAKE_BASE=TRUE
18
MCP_CLK27M_XTALOUT
NC_MCP_CLK27M_XTALOUT MAKE_BASE=TRUE
B
B
HDCP ROM WF: Open question on which packge option(s) nVidia can support. 8
=PP3V3_S0_HDCPROM
R26901
C2690 1 20% 10V CERM 2 402
10K
OMIT VCC
0.1UF
8
5% 1/16W MF-LF 402 2
U2695 AT24C08 1 A0
SOIC
2 A1
SDA SCL
5 6
=I2C_HDCPROM_SDA =I2C_HDCPROM_SCL
WP
7
HDCPROM_WP
BI IN
45 45
3 A2
GND 4
MCP Graphics Support SYNC_MASTER=AMASON_M98_MLB
A
SYNC_DATE=06/18/2008
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
8
7
6
SCALE
SHT NONE
Current numbers from email Xiaowei Lin provided 11/12/2007 3:22pm (no official document number).
5
4
3
2
REV.
051-7546
A.0.0 OF
25
1
96
A
6
7
RTC Power Sources
LPC Reset (Unbuffered)
VIN
U2801
R2881
MIC5232-2.8YD5 TSOT-23-5 3
D C2802
EN
VOUT
5
NC
4
PP3V3_G3_RTC
1
R2801
1UF
1
2
R2802 1.0M 1
R2811 10M
21
OUT
IN
PCIE_RESET_L
0
1
1
MCP 25MHz Crystal IN
0
1
2
1
MCP_CLK25M_XTALOUT_R
R2816 1M
CRITICAL
21
OUT
1
25.0000M
SM-3.2X2.5MM
NC NC
IN
MEM_VTT_EN_R
C
0
MINI_RESET_L
2
OUT
31
OUT
32
OUT
9
LPC_CLK33M_SMC
OUT
42 90
LPC_CLK33M_LPCPLUS
OUT
44 90
EXCARD_RESET_L
33
MEM_VTT_EN
2
R2825
2 IN
33
PLACEMENT_NOTE=Place close to U1400 1
LPC_CLK33M_SMC_R
5% 50V CERM 402
2
5% 1/16W MF-LF 402
MCP S0 PWRGD & CPU_VLD
R2826 1
33
5% 1/16W MF-LF 402
R2827 =PP3V3_S5_MCPPWRGD
33
2
PLACEMENT_NOTE=Place close to U1400
2 LPC_CLK33M_GMUX 5% 1/16W MF-LF 402 PLACEMENT_NOTE=Place close to U1400 1
MCPSEQ_SMC 1
85
5% 1/16W MF-LF 402
1
12pF
B
OUT
5% 1/16W MF-LF 402
90 19
8
27
R2894
2
C2816 1
MCP_CLK25M_XTALIN
OUT
R2870 19
Y2815
5% 1/16W MF-LF 402 2
83
5% 1/16W MF-LF 402
3
2
5% 1/16W MF-LF 402
2 4
0
1
0
1
PCA9557D_RESET_L
2
BKLT_PLT_RST_L
2
R2895
2
5% 50V CERM 402
R2815 NO STUFF
0
1
12pF
1
OUT
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
C2815
MCP_CLK25M_XTALOUT
36
=GMUX_PCIE_RESET_L
R2893 12pF 5% 50V CERM 402
21
OUT
R2891
C2811 1
2
MAKE_BASE=TRUE
1
RTC_CLK32K_XTALIN
FW_RESET_L
D
GMUX_PCIE_RESET_L
2
5% 1/16W MF-LF 402
2
5% 50V CERM 402
32.768K
7X1.5X1.4-SM
42
5% 1/16W MF-LF 402
R2890 1
0
1
CRITICAL
5% 1/16W MF-LF 402 2
C
OUT
R2892 17 9
12pF
Y2810
SMC_LRESET_L
PCIE Reset (Unbuffered)
C2810
RTC_CLK32K_XTALOUT_R
5% 1/16W MF-LF 402
1
2
5% 1/16W MF-LF 402
4
1
NO STUFF
44
C2800
2% 2 3.3V XHHG SM
5% 1/10W MF-LF 603
0
33
1
PLACEMENT_NOTE=Place close to U1400
0.08F
NO STUFF
R2810
OUT
PP3V3_G3_SUPERCAP
10% 6.3V CERM 2 402
RTC Crystal
DEBUG_RESET_L
R2883
5% 1/16W MF-LF 2 402
C28011
10
5% 1/16W MF-LF 402 2
RTC_CLK32K_XTALOUT
2
5% 1/16W MF-LF 402
100
2
33
1
21 22
R2800
GND
2
IN
PLACEMENT_NOTE=Place close to U1400
LPC_RESET_L
1
RTC_DISCHARGE_R
21
IN
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
2
10% 10V X5R 402
90 83 19
1
1UF
1
Platform Reset Connections
=PP3V3_S5_RTC_D 1
8
2
3
4
5
www.laptop-schematics.com
8
C2850
OUT
83
OUT
42 90
B
0.1UF
20% 10V 2 CERM 402
R2829 90 21
IN
PM_CLK32K_SUSCLK_R
MCPSEQ_SMC 68 42
62
IN
ALL_SYS_PWRGD
IN
VR_PWRGOOD_DELAY
A
TC7SZ08AFEAPE SOT665
U2850Y
R2853
S0_AND_IMVP_PGOOD
1
0
2
MCP_PS_PWRGD
OUT
21
MCP_CPU_VLD
OUT
21
22
1 PLACEMENT_NOTE=Place close to U1400
PM_CLK32K_SUSCLK
2
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
B
MCPSEQ_SMC
MCPSEQ_MIX
R2852 1
MCPSEQ_MIX
R2851 1
0
5% 1/16W MF-LF 402 21
IN
2
2
Reset Button
MCPSEQ_SMC
R2850
MCP_CPUVDD_EN
1 PLACEMENT_NOTE=Place close to U1400
A
0
5% 1/16W MF-LF 402
0
42
IN
PM_SYSRST_L XDP
2
5% 1/16W MF-LF 402
13 10
IN
XDP_DBRESET_L
R2896
R2899
1
1
0
5% 1/16W MF-LF 402
MCPSEQ_SMC represents MCP79 ’MLB’ power sequencing connections, but results in MCP79 ROMSIP sequence happening after CPU powers up.
2
OMIT
R28971 0
33
5% 1/16W MF-LF 402
PM_SYSRST_DEBOUNCE_L NO STUFF 1
OUT
SB Misc
21 23
SYNC_MASTER=T18_MLB
C2899
SYNC_DATE=12/17/2007
NOTICE OF PROPRIETARY PROPERTY
1UF
10% 2 10V X5R 402
5% 1/16W MF-LF 402 2
MCPSEQ_MIX is cross between MLB and internal power sequencing, which results in earlier ROMSIP and MCP FSB I/O interface initialization.
10K pull-up to 3.3V S0 inside MCP
2
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
SILK_PART=FP SYS RESET
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
SMC 99ms delay from ALL_SYS_PWRGD to IMVP_VR_ON plus IMVP6 delay for VR_PWRGOOD_DELAY should guarantee CPU_VLD does not go high before CPUVDD_EN (which is 40-100ms after PS_PWRGD assertion).
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
NOTE: If CPU_VLD deasserts during S0 MCP79 will take system to S5 immediately.
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
26
1
96
A
8
6
7
2
3
4
5
1
Page Notes MEM A VREF DQ DAC channel Min DAC code Max DAC code Max sink I Max source I Nominal Vref Min Vref Max Vref Vref Stepping (per DAC LSB)
Signal aliases required by this page: - =I2C_VREFDACS_SCL - =I2C_VREFDACS_SDA - =I2C_PCA9557D_SCL - =I2C_PCA9557D_SDA
D
BOM options provided by this page: VREFMRGN NO_VREFMRGN
MEM A VREF CA
A 0x00 0x87 -3.75 mA 5 mA 0.75 V 0.375 V 1.250 V 6.5 mV
MEM B VREF DQ
B 0x00 0x87 -3.75 mA 5 mA 0.75 V 0.375 V 1.250 V 6.5 mV
MEM B VREF CA
A 0x00 0x87 -3.75 mA 5 mA 0.75 V 0.375 V 1.250 V 6.5 mV
B 0x00 0x87 -3.75 mA 5 mA 0.75 V 0.375 V 1.250 V 6.5 mV
CPU FSB VREF C 0x00 0x55 -0.91 mA 0.52 mA 0.70 V 0.091 V 1.044 V 11.2 mV
FRAME BUFFER VREF D 0x00 0xFF -59.04 mA 51.15 mA 1.248 V 1.042 V 1.426 V 1.5 mV
SO-DIMM A and SO-DIMM B Vref settings should be margined separately (i.e. not simultaneously) due to current limitation of TPS51116 regulator. =PPVTT_S3_DDR_BUF 64 8
D
10mA max load
R2903 1
A2
V+
UCSP A1 VREFMRGN
0.1UF
20% 10V 2 CERM 402
=PP3V3_S3_VREFMRGN 8
A3
27
B4
R2901
C2901 0.1UF
20% 2 10V CERM 402 C2
V+
=I2C_VREFDACS_SCL
6 SCL
BI
=I2C_VREFDACS_SDA
7 SDA 9 A0
ADDR=0x98(WR)/0x99(RD)
C
10 A1
VREFMRGN_DQ_SODIMMB_BUF
27
B4
VOUTB 2
VREFMRGN_CA_SODIMM
VOUTC 4
VREFMRGN_CPUFSB
VOUTD 5
VREFMRGN_FRAMEBUF
100K 5% 1/16W MF-LF 402 1
A2
C2904
V+
A3
VREFMRGN_CA_SODIMMA_BUF
27
C2
V+
1
VREFMRGN_CA_SODIMMB_BUF
100K
A2
V+
0.1UF A3
1
27
1
100K
U2901
45
IN BI
B4
PCA9557
1 2
SCL SDA THRM 17
PAD
NC
7
27
27
VREFMRGN_CA_SODIMMB_EN
11
VREFMRGN
49.9 2
GPU_FB_A_VREF_DIV
OUT
9
OUT
9
OUT
10 87
Place close to U8400, U8450
VREFMRGN
49.9 2
GPU_FB_B_VREF_DIV
B
Place close to U8500, U8550
1
5% 1/16W MF-LF 402
VREFMRGN_DQ_SODIMMA_EN
1
100
1% 1/16W MF-LF 402
VREFMRGN_CPUFSB_EN
100K
27
10
27
R2913
VREFMRGN_CPUFSB_EN VREFMRGN_CA_SODIMMA_EN
9
Place close to J3200.126
VREFMRGN
CPU_GTLREF
2
Place close to U1000.AD26
VREFMRGN
1
A0 A1 5 A2 4
2
R2914 VREFMRGN_CPUFSB_BUF
C4
V-
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm
27
VREFMRGN_DQ_SODIMMB_EN
12
27
VREFMRGN_FRAMEBUF_EN
13
27
14
NC
RESET* 15
PCA9557D_RESET_L IN
26
GND 8
45
C3
29
1% 1/16W MF-LF 402
VREFMRGN
MAX4253 UCSP C1
100
VREFMRGN
2
16
VCC
3
=I2C_PCA9557D_SCL =I2C_PCA9557D_SDA
V+
5% 1/16W MF-LF 402
U2904
B1
VREFMRGN
PP0V75_S3_MEM_VREFCA_B
R2917
VREFMRGN_FRAMEBUF_EN
R2915
C2
VREFMRGN
2
VREFMRGN_FRAMEBUF_BUF
B
VREFMRGN
200
R2916 1
A4
V-
Place close to J3100.126
1% 1/16W MF-LF 402
UCSP A1
B4
VREFMRGN
VREFMRGN
MAX4253
VREFMRGN
20% 2 10V CERM 402
2
1% 1/16W MF-LF 402
2
C2905
5% 1/16W MF-LF 402
U2904
B1
VREFMRGN
1
VREFMRGN_CA_SODIMMB_EN
R2908
1
28
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.1 mm
VREFMRGN
2
B4
100
C
PP0V75_S3_MEM_VREFCA_A
R2912
27
VREFMRGN
2
1% 1/16W MF-LF 402
C4
V-
200
R2911 VREFMRGN
MAX4253
UCSP C1 VREFMRGN
ADDR=0x30(WR)/0x31(RD)
Place close to J3200.1
1% 1/16W MF-LF 402
1
5% 1/16W MF-LF 402
U2903
B1
C3
1
VREFMRGN_CA_SODIMMA_EN
100K
6
1
A4
V-
R2907
P0 P1 P2 P3 P4 P5 P6 P7
2
R2910
UCSP A1 VREFMRGN
0.1UF
QFN
29
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm
VREFMRGN
1% 1/16W MF-LF 402
MAX4253
B4
20% 2 10V CERM 402
100
R2909 VREFMRGN
U2903
B1
20% 10V 2 CERM 402
0.1UF
PP0V75_S3_MEM_VREFDQ_B
1% 1/16W MF-LF 402
VREFMRGN_DQ_SODIMMB_EN
R2902
GND 3
C2902
VREFMRGN
2
VREFMRGN_DQ_SODIMM
VREFMRGN
1
1
C4
V-
Place close to J3100.1
1% 1/16W MF-LF 402
1
45
IN
DAC5574
45
C3
200
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm
VREFMRGN
2
R2906
MAX4253
UCSP C1 VREFMRGN
VREFMRGN 8 U2900 VDD 1 MSOP VOUTA
5% 1/16W MF-LF 402
U2902
B1
VREFMRGN
1
20% 2 6.3V CERM 402-LF
100
R2905 1
100K
2
1
2.2UF
1
VREFMRGN_DQ_SODIMMA_EN
VREFMRGN
C2900
28
1% 1/16W MF-LF 402
2
VREFMRGN 1
VREFMRGN_DQ_SODIMMA_BUF
A4
V-
PP0V75_S3_MEM_VREFDQ_A
R2904
MAX4253
2
C2903
2
1% 1/16W MF-LF 402
U2902
B1
VREFMRGN 1
200
VREFMRGN
www.laptop-schematics.com
Power aliases required by this page: - =PP3V3_S3_VREFMRGN - =PP3V3_S5_VREFMRGN - =PPVTT_S3_DDR_BUF
FSB/DDR3/FRAMEBUF Vref Margining SYNC_MASTER=DDR
A
SYNC_DATE=07/22/2008
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
Required zero ohm resistors when no VREF margining circuit stuffed
PART NUMBER
QTY
116S0004
1
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
RES,MTL FILM,0,5%,0402,SM,LF
R2903
CRITICAL
NO_VREFMRGN
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
116S0004
1
RES,MTL FILM,0,5%,0402,SM,LF
R2905
CRITICAL
NO_VREFMRGN
116S0004
1
RES,MTL FILM,0,5%,0402,SM,LF
R2909
CRITICAL
NO_VREFMRGN
116S0004
1
RES,MTL FILM,0,5%,0402,SM,LF
R2911
CRITICAL
NO_VREFMRGN
SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
27
1
96
A
8
6
7 =PP1V5_S0_MEM_A
8
=PP1V5_S3_MEM_A
1
DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)
Page Notes 8
2
3
4
5
Power aliases required by this page: - =PP1V5_S0_MEM_A - =PP1V5_S3_MEM_A
1
Signal aliases required by this page:
1
C3100 10UF
- =I2C_SODIMMA_SCL
20% 2 6.3V X5R 603
- =I2C_SODIMMA_SDA BOM options provided by this page:
1
C3111
1
0.1UF
20% 2 10V CERM 402
20% 2 10V CERM 402
- =PPSPD_S0_MEM_A (2.5 - 3.3V)
1
C3112 0.1UF
1
C3113 0.1UF
20% 2 10V CERM 402
20% 2 10V CERM 402
1
C3114 0.1UF
20% 10V 2 CERM 402
1
C3115 0.1UF
20% 2 10V CERM 402
1
C3116
1
0.1UF
C3117
1
0.1UF
20% 10V 2 CERM 402
C3118 0.1UF
20% 2 10V CERM 402
20% 2 10V CERM 402
1
C3119 0.1UF
20% 2 10V CERM 402
1
C3120 0.1UF
20% 2 10V CERM 402
1
C3121 0.1UF
20% 2 10V CERM 402
1
C3122
1
0.1UF
C3123 0.1UF
20% 2 10V CERM 402
20% 2 10V CERM 402
C3101 10UF
20% 2 6.3V X5R 603
27
D
PP0V75_S3_MEM_VREFDQ_A
(NONE)
C3130
1
C3131
2
0.1UF
20% 6.3V CERM 402-LF
2
20% 10V CERM 402
1
MEM_A_CKE
73 75 77
88 15
C
IN
88 15
IN
88 15
IN
88 15
IN
88 15
IN
88 15
IN
88 15
IN
88 15
IN
88 15
IN
88 15
IN
88 15
IN
88 15
IN
88 15
IN
88 15
IN
88 15
IN
MEM_A_BA MEM_A_A MEM_A_A MEM_A_A MEM_A_A MEM_A_A MEM_A_A
79 81 83 85 87 89 91 93 95 97 99
MEM_A_CLK_P MEM_A_CLK_N
101
MEM_A_A MEM_A_BA
107
MEM_A_WE_L MEM_A_CAS_L
113
MEM_A_A MEM_A_CS_L
119 121
103 105 109 111 115 117
123 125 127 88 15
BI
88 15
BI
88 15
BI
88 15
BI
88 15
BI
88 15
BI
MEM_A_DQ MEM_A_DQ
129
MEM_A_DQS_N MEM_A_DQS_P
135
MEM_A_DQ MEM_A_DQ
141 143
131 133 137 139
145 147 149
88 15
BI
88 15
BI
MEM_A_DQ MEM_A_DQ
88 15
IN
MEM_A_DM
153 155
88 15
BI
157
88 15
BI
MEM_A_DQ MEM_A_DQ
88 15
BI
88 15
BI
MEM_A_DQ MEM_A_DQ
163 165
151
B
159 161
167 88 15
BI
88 15
BI
MEM_A_DQS_N MEM_A_DQS_P
169 171 173
88 15
BI
88 15
BI
MEM_A_DQ MEM_A_DQ
175 177 179
88 15
BI
88 15
BI
MEM_A_DQ MEM_A_DQ
181 183 185 187
88 15
IN
MEM_A_DM
88 15
BI
88 15
BI
MEM_A_DQ MEM_A_DQ
189 191 193 195
8
MEM_A_SA
197 199
MEM_A_SA
201
=PPSPD_S0_MEM_A
203 1 1
A
C3140 2.2UF
2
20% 6.3V CERM 402-LF
2
1
R3140
J3100
74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122
MEM_A_CKE
IN
15 88
88 15 88 15
MEM_A_A MEM_A_A MEM_A_A MEM_A_A MEM_A_A MEM_A_A
IN
9
IN
15 88
88 15
BI BI
IN
IN
15 88
88 15
BI
IN
15 88
88 15
BI
IN
15 88
88 15
BI
IN
15 88
88 15
BI
MEM_A_A MEM_A_A
IN
15 88
88 15
BI
IN
15 88
88 15
BI
MEM_A_CLK_P MEM_A_CLK_N
IN
15 88
88 15
BI
IN
15 88
88 15
BI
MEM_A_BA MEM_A_RAS_L
IN
15 88
88 15
BI
IN
15 88
88 15
BI
MEM_A_CS_L MEM_A_ODT
IN
15 88
88 15
BI
IN
15 88
88 15
BI
MEM_A_ODT
IN
15 88
88 15
BI
88 15
BI
3 5
MEM_A_DQ MEM_A_DQ
7 9 11
MEM_A_DM
13 15
MEM_A_DQ MEM_A_DQ
17 19 21
MEM_A_DQ MEM_A_DQ
23 25 27
MEM_A_DQS_N MEM_A_DQS_P
29 31
MEM_A_DQ MEM_A_DQ
33
MEM_A_DQ MEM_A_DQ
39
MEM_A_DQS_N MEM_A_DQS_P
45
MEM_A_DQ MEM_A_DQ
51 53
35 37 41 43 47 49
124
55
126 128 130 132 134 136 138 140
MEM_A_DQ MEM_A_DQ MEM_A_DM
BI
15 88
BI
15 88
IN
BI
15 88
BI
15 88
MEM_A_DQ MEM_A_DQ
BI
15 88
BI
15 88
MEM_A_DQS_N MEM_A_DQS_P
BI
15 88
BI
15 88
MEM_A_DQ MEM_A_DQ
BI
15 88
BI
15 88
MEM_A_DQ MEM_A_DQ
BI
15 88
BI
15 88
170 172
MEM_A_DM
IN
174
MEM_A_DQ MEM_A_DQ
BI
15 88
BI
15 88
MEM_A_DQ MEM_A_DQ
BI
15 88
BI
15 88
146 148 150 152 154 156 158 160 162 164 166
BI
88 15
BI
57 59
MEM_A_DQ MEM_A_DQ
61 IN
MEM_A_DM
63 65
88 15
BI
67
88 15
BI
MEM_A_DQ MEM_A_DQ
88 15
15 88
MEM_A_DQ MEM_A_DQ
142 144
88 15
69 71
VREFDQ VSS VSS DQ4 DQ0 DQ5 CRITICAL DQ1 VSS VSS DQS0* DM0 DQS0 F-RT-THB VSS VSS DQ2 DQ6 DQ3 DQ7 VSS VSS DQ8 DQ12 DQ9 DQ13 VSS VSS DQS1* DM1 DQS1 RESET* VSS VSS DQ10 DQ14 DQ11 DQ15 VSS VSS DQ16 DQ20 DQ17 DQ21 VSS VSS DQS2* DM2 DQS2 VSS DQ22 VSS DQ18 DQ23 DQ19 VSS DQ28 VSS DQ24 DQ29 DQ25 VSS DQS3* VSS DM3 DQS3 VSS VSS DQ26 DQ30 DQ27 DQ31 VSS VSS
J3100
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
MEM_A_DQ MEM_A_DQ
BI
15 88
BI
15 88
MEM_A_DQS_N MEM_A_DQS_P
BI
15 88
BI
15 88
MEM_A_DQ MEM_A_DQ
BI
15 88
BI
15 88
MEM_A_DQ MEM_A_DQ
BI
15 88
MEM_A_DM MEM_RESET_L
IN
15 88
IN
29 30
MEM_A_DQ MEM_A_DQ
BI
15 88
BI
15 88
MEM_A_DQ MEM_A_DQ
BI
15 88
BI
15 88
MEM_A_DM
IN
MEM_A_DQ MEM_A_DQ
BI
15 88
BI
15 88
MEM_A_DQ MEM_A_DQ
BI
15 88
BI
15 88
MEM_A_DQS_N MEM_A_DQS_P
BI
15 88
BI
15 88
MEM_A_DQ MEM_A_DQ
BI
15 88
BI
15 88
BI
15 88
C
15 88
KEY
516-0196
B
168
176 178 180 182 184 186 188
15 88
PP0V75_S3_MEM_VREFCA_A
1
C3135
1
2.2UF
MEM_A_DQS_N MEM_A_DQS_P
BI
15 88
BI
15 88
MEM_A_DQ MEM_A_DQ
BI
15 88
BI
15 88
2
20% 6.3V CERM 402-LF
27
C3136 0.1UF
2
20% 10V CERM 402
190 192 194 196 198 200 202
MEM_EVENT_L =I2C_SODIMMA_SDA =I2C_SODIMMA_SCL
OUT
21 29 42
BI IN
"Factory" (top) slot
45 45
204
=PP0V75_S0_MEM_VTT_A
8
DDR3 SO-DIMM Connector A
R3141
10K
10K
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
2
CKE0 CKE1 VDD VDD NC A15 BA2 A14 F-RT-THB VDD VDD A12/BC* A11 A9 A7 VDD VDD A8 A6 A5 A4 VDD VDD A3 A2 A0 A1 VDD VDD CK0 CK1 CK0* CK1* VDD VDD A10/AP BA1 BA0 RAS* VDD VDD WE* S0* CAS* ODT0 VDD VDD A13 ODT1 S1* NC VDD VDD TEST VREFCA VSS VSS DQ32 DQ36 DQ33 DQ37 VSS VSS DQS4* DM4 DQS4 VSS VSS DQ38 DQ34 DQ39 DQ35 VSS VSS DQ44 DQ40 DQ45 DQ41 VSS VSS DQS5* DM5 DQS5 VSS VSS DQ42 DQ46 DQ43 DQ47 VSS VSS DQ48 DQ52 DQ49 DQ53 VSS VSS DQS6* DM6 DQS6 VSS VSS DQ54 DQ50 DQ55 DQ51 VSS VSS DQ60 DQ56 DQ61 DQ57 VSS VSS DQS7* DM7 DQS7 VSS VSS DQ58 DQ62 DQ63 DQ59 VSS VSS SA0 EVENT* VDDSPD SDA SA1 SCL VTT VTT (SYMBOL 2 OF 2)
IN
DDR3-SODIMM-DUAL-M97-3
88 15
KEY
www.laptop-schematics.com
2.2UF
(SYMBOL 1 OF 2)
1
DDR3-SODIMM-DUAL-M97-3
D
C3110 0.1UF
- =PP0V75_S0_MEM_VTT_A
SYNC_MASTER=DDR
SYNC_DATE=07/22/2008
516-0196
NOTICE OF PROPRIETARY PROPERTY
SPD ADDR=0xA0(WR)/0xA1(RD)
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
28
1
96
A
8
6
7 =PP1V5_S0_MEM_B
8
=PP1V5_S3_MEM_B
1
DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)
Page Notes 8
2
3
4
5
Power aliases required by this page: - =PP1V5_S0_MEM_B - =PP1V5_S3_MEM_B
1
Signal aliases required by this page:
1
C3200 10UF
- =I2C_SODIMMB_SCL
20% 2 6.3V X5R 603
- =I2C_SODIMMB_SDA BOM options provided by this page:
1
C3211
1
0.1UF
20% 2 10V CERM 402
- =PPSPD_S0_MEM_B (2.5 - 3.3V)
20% 2 10V CERM 402
1
C3212 0.1UF
20% 2 10V CERM 402
1
C3213 0.1UF
20% 2 10V CERM 402
1
C3214 0.1UF
20% 2 10V CERM 402
1
C3215 0.1UF
20% 10V 2 CERM 402
1
C3216
1
0.1UF
C3217
1
0.1UF
20% 2 10V CERM 402
C3218 0.1UF
20% 2 10V CERM 402
20% 2 10V CERM 402
1
C3219 0.1UF
20% 2 10V CERM 402
1
C3220 0.1UF
20% 2 10V CERM 402
1
C3221 0.1UF
20% 2 10V CERM 402
1
C3222 0.1UF
20% 2 10V CERM 402
1
C3223 0.1UF
20% 2 10V CERM 402
C3201 10UF
20% 2 6.3V X5R 603
27
D
PP0V75_S3_MEM_VREFDQ_B
(NONE)
C3230
1
C3231
2
0.1UF
20% 6.3V CERM 402-LF
2
20% 10V CERM 402
1 73 75 77 88 15
C
88 15
IN
88 15
IN
88 15
IN
88 15
IN
88 15
IN
88 15
IN
88 15
IN
88 15
IN
88 15
IN
88 15
IN
88 15
IN
88 15
IN
88 15
IN
88 15
MEM_B_BA
IN
MEM_B_A MEM_B_A MEM_B_A MEM_B_A MEM_B_A MEM_B_A
IN
79 81 83 85 87 89 91 93 95 97 99
MEM_B_CLK_P MEM_B_CLK_N
101
MEM_B_A MEM_B_BA
107
MEM_B_WE_L MEM_B_CAS_L
113
MEM_B_A MEM_B_CS_L
119 121
103 105 109 111 115 117
123 125 127 88 15
BI
88 15
BI
88 15
BI
88 15
BI
88 15
BI
88 15
BI
MEM_B_DQ MEM_B_DQ
129
MEM_B_DQS_N MEM_B_DQS_P
135
MEM_B_DQ MEM_B_DQ
141 143
131 133 137 139
145 147 149
88 15
BI
88 15
BI
MEM_B_DQ MEM_B_DQ
88 15
IN
MEM_B_DM
153 155
88 15
BI
157
88 15
BI
MEM_B_DQ MEM_B_DQ
88 15
BI
88 15
BI
MEM_B_DQ MEM_B_DQ
163 165
151
B
159 161
167 88 15
BI
88 15
BI
MEM_B_DQS_N MEM_B_DQS_P
169 171 173
88 15
BI
88 15
BI
MEM_B_DQ MEM_B_DQ
175 177 179
1
R3240
88 15
BI
88 15
BI
MEM_B_DQ MEM_B_DQ
181 183 185 187
88 15
IN
MEM_B_DM
88 15
BI
88 15
BI
MEM_B_DQ MEM_B_DQ
189
10K
2
5% 1/16W MF-LF 402
191 193 195
8
MEM_B_SA
197 199
MEM_B_SA
201
=PPSPD_S0_MEM_B
203 1 1
A
C3240
2
R3241 10K
2.2UF 20% 6.3V CERM 402-LF
2
5% 1/16W MF-LF 402
205 207 209 211
CKE0 CKE1 VDD VDD NC A15 BA2 A14 VDD F-RT-BGA3 VDD A12/BC* A11 A9 A7 VDD VDD A8 A6 A5 A4 VDD VDD A3 A2 A1 A0 VDD VDD CK0 CK1 CK0* CK1* VDD VDD A10/AP BA1 BA0 RAS* VDD VDD WE* S0* CAS* ODT0 VDD VDD A13 ODT1 S1* NC VDD VDD TEST VREFCA VSS VSS DQ32 DQ36 DQ33 DQ37 VSS VSS DQS4* DM4 DQS4 VSS VSS DQ38 DQ39 DQ34 DQ35 VSS DQ44 VSS DQ40 DQ45 DQ41 VSS VSS DQS5* DM5 DQS5 VSS VSS DQ42 DQ46 DQ43 DQ47 VSS VSS DQ48 DQ52 DQ49 DQ53 VSS VSS DQS6* DM6 DQS6 VSS VSS DQ54 DQ50 DQ55 DQ51 VSS VSS DQ60 DQ56 DQ61 DQ57 VSS DQS7* VSS DM7 DQS7 VSS VSS DQ58 DQ62 DQ59 DQ63 VSS VSS SA0 EVENT* VDDSPD SDA SA1 SCL VTT VTT
J3200 (2 OF 2)
MEM_B_CKE
IN
DDR3-SODIMM
88 15
KEY
MTG PINS
MTG MTG MTG MTG
PIN PIN PIN PIN
74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122
IN
15 88
88 15 88 15
MEM_B_A MEM_B_A MEM_B_A MEM_B_A MEM_B_A MEM_B_A
IN
9
IN
15 88
88 15
BI BI
IN
IN
15 88
88 15
BI
IN
15 88
88 15
BI
IN
15 88
88 15
BI
IN
15 88
88 15
BI
MEM_B_A MEM_B_A
IN
15 88
88 15
BI
IN
15 88
88 15
BI
MEM_B_CLK_P MEM_B_CLK_N
IN
15 88
88 15
BI
IN
15 88
88 15
BI
MEM_B_BA MEM_B_RAS_L
IN
15 88
88 15
BI
IN
15 88
88 15
BI
MEM_B_CS_L MEM_B_ODT
IN
15 88
88 15
BI
IN
15 88
88 15
BI
MEM_B_ODT
IN
15 88
88 15
BI
88 15
BI
MEM_B_DQ MEM_B_DQ
7 9 11
MEM_B_DM
13 15
MEM_B_DQ MEM_B_DQ
17 19 21
MEM_B_DQ MEM_B_DQ
23 25 27
MEM_B_DQS_N MEM_B_DQS_P
29 31
MEM_B_DQ MEM_B_DQ
33
MEM_B_DQ MEM_B_DQ
39
MEM_B_DQS_N MEM_B_DQS_P
45
MEM_B_DQ MEM_B_DQ
51 53
35 37 41 43 47 49
124
55
126 128 130 132 134 136 138 140
MEM_B_DQ MEM_B_DQ MEM_B_DM
BI
15 88
BI
15 88
IN
BI
15 88
BI
15 88
MEM_B_DQ MEM_B_DQ
BI
15 88
BI
15 88
MEM_B_DQS_N MEM_B_DQS_P
BI
15 88
BI
15 88
MEM_B_DQ MEM_B_DQ
BI
15 88
BI
15 88
MEM_B_DQ MEM_B_DQ
BI
15 88
BI
15 88
170 172
MEM_B_DM
IN
174
MEM_B_DQ MEM_B_DQ
BI
15 88
BI
15 88
MEM_B_DQ MEM_B_DQ
BI
15 88
BI
15 88
146 148 150 152 154 156 158 160 162 164 166
88 15
BI
88 15
BI
57 59
MEM_B_DQ MEM_B_DQ
61 IN
MEM_B_DM
63 65
88 15
BI
67
88 15
BI
MEM_B_DQ MEM_B_DQ
88 15
15 88
MEM_B_DQ MEM_B_DQ
142 144
69 71
VREFDQ VSS VSS DQ4 DQ0 DQ5 CRITICAL DQ1 VSS VSS DQS0* DM0 DQS0 F-RT-BGA3 VSS VSS DQ2 DQ6 DQ3 DQ7 VSS VSS DQ8 DQ12 DQ9 DQ13 VSS VSS DQS1* DM1 DQS1 RESET* VSS VSS DQ14 DQ10 DQ15 DQ11 VSS VSS DQ20 DQ16 DQ17 DQ21 VSS VSS DQS2* DM2 DQS2 VSS DQ22 VSS DQ23 DQ18 DQ19 VSS DQ28 VSS DQ24 DQ29 DQ25 VSS DQS3* VSS DM3 DQS3 VSS VSS DQ26 DQ30 DQ27 DQ31 VSS VSS
J3200
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
MEM_B_DQ MEM_B_DQ
BI
15 88
BI
15 88
MEM_B_DQS_N MEM_B_DQS_P
BI
15 88
BI
15 88
MEM_B_DQ MEM_B_DQ
BI
15 88
BI
15 88
MEM_B_DQ MEM_B_DQ
BI
15 88
MEM_B_DM MEM_RESET_L
IN
15 88
IN
28 30
MEM_B_DQ MEM_B_DQ
BI
15 88
BI
15 88
MEM_B_DQ MEM_B_DQ
BI
15 88
BI
15 88
MEM_B_DM
IN
MEM_B_DQ MEM_B_DQ
BI
15 88
BI
15 88
MEM_B_DQ MEM_B_DQ
BI
15 88
BI
15 88
MEM_B_DQS_N MEM_B_DQS_P
BI
15 88
BI
15 88
MEM_B_DQ MEM_B_DQ
BI
15 88
BI
15 88
BI
15 88
C
15 88
KEY
516s0704
B
168
176 178 180 182 184 186 188
15 88
PP0V75_S3_MEM_VREFCA_B
1
C3235
1
2.2UF
MEM_B_DQS_N MEM_B_DQS_P
BI
15 88
BI
15 88
MEM_B_DQ MEM_B_DQ
BI
15 88
BI
15 88
2
20% 6.3V CERM 402-LF
27
C3236 0.1UF
2
20% 10V CERM 402
190 192 194 196 198 200 202
MEM_EVENT_L =I2C_SODIMMB_SDA =I2C_SODIMMB_SCL
OUT
21 28 42
BI IN
204
MTG PIN
206 208
MTG PIN MTG PIN
210 212
MTG PIN
MEM_B_CKE
3 5
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2.2UF
(1 OF 2)
1
DDR3-SODIMM
D
C3210 0.1UF
- =PP0V75_S0_MEM_VTT_B
45
"Expansion" (bottom) slot
45
=PP0V75_S0_MEM_VTT_B
8
DDR3 SO-DIMM Connector B SYNC_MASTER=DDR
SYNC_DATE=07/22/2008
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
516s0704
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
SPD ADDR=0xA2(WR)/0xA3(RD)
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
29
1
96
A
8
7
6
3
4
5
2
1
D
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D
DDR3 RESET Support MCP79 cannot control this signal directly since it must be high in sleep and MCP MEM rails are not powered in sleep.
8
8
=PP1V5_S3_MEMRESET
=PP3V3_S5_MEMRESET
3.3V input must be stable before before 1.5V starts to rise to avoid glitch on MEM_RESET_L.
1
R3310 1K
5% 1/16W MF-LF 2 402
MEMRESET_HW
C
1
R3305 20K
5% 1/16W MF-LF 2 402
MEMRESET_HW
R33001
MEM_RESET
10K 5% 1/16W MF-LF 402 2
MEMRESET_HW 3
5% 1/16W MF-LF 402 2
16
IN
MMDT3904-X-G 1
C OUT
28 29
1
R3309 0
5% 1/16W MF-LF 2 402
Q3305
5
MMDT3904-X-G SOT-363-LF
MEMRESET_HW 20K
Q3305 SOT-363-LF
MEM_RESET_RC_L
R33011
MEMRESET_HW
6 2
MEM_RESET_L MEMRESET_MCP
MEMRESET_HW 1
C3300
4
0.1UF
20% 10V 2 CERM 402
MCP_MEM_RESET_L
B
B
DDR3 Support SYNC_MASTER=T18_MLB
A
SYNC_DATE=06/18/2008
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
30
1
96
A
8
6
7 17
OUT
2
3
4
5
1
PCIE_MINI_PRSNT_L 3
D
Q3401 SSM6N15FEAPE SOT563
4
S
G 5
AP_PWR_EN
21 34
IN
5V S3 WLAN FET
D Q3401
D
SOT563
S
P-TYPE 26 mOhm @4.5V
LOADING
0.8 A (EDP)
G 2
Q3450
20347-325E-12
16V X5R 402
17 89
IN
17 89
PP5V_WLAN
PCIE_MINI_D2R_P PCIE_MINI_D2R_N 95 89 95 89
OUT
17 89
OUT
17 89
95 95
PCIE_CLK100M_MINI_CONN_P PCIE_CLK100M_MINI_CONN_N MINI_CLKREQ_Q_L PCIE_WAKE_L
1
0.1uF
20% 10V CERM 2 402
PP5V_WLAN_F
C3420 10UF
20% 10V CERM 2 402
20% 2 10V X5R 805
C3450 0.1UF 1
PCIE_CLK100M_MINI_P
3
2 10% 16V X5R 402
PLACEMENT_NOTE=Place close to J3401.
DLP11S SYM_VER-1
4
31
C3421 1
0.1uF
AIRPORT
1
MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V
C3422
L3401 90-OHM-100MA
PCIE_MINI_R2D_P PCIE_MINI_R2D_N
2
MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V 1
PLACEMENT_NOTE=Place close to J3401.
31
B
10%
16V X5R 402
C3430
F-RT-SM
C
2 0.1uF
IN
FDC606P_G SOT-6
G
1 10%
1000 mA peak 750 mA nominal max
PCIE_MINI_R2D_C_P PCIE_MINI_R2D_C_N
0.1uF
0402-LF
3
C3431 1 2
J3401 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
FERR-120-OHM-1.5A
PLACEMENT_NOTE=Place close to J3401.
1 2 5 6
L3404
CRITICAL 518S0610
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1
CHANNEL RDS(ON)
SSM6N15FEAPE
D
=PP5V_S3_WLAN
4
6
FDC606P
S
OUT
MOSFET
D
17
MINI_CLKREQ_L
1
R3451
C3451 1
10K
0.033UF
10% 16V 2 X5R 402
P5VWLAN_SS
8
MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V
R3450 1
5% 1/16W MF-LF 2 402
100K 2
PM_WLAN_EN_L
IN
34
5% 1/16W MF-LF 402
C
PLACEMENT_NOTE=Place close to Q3450. IN
17 89
PLACEMENT_NOTE=Place close to Q3450.
1
PCIE_CLK100M_MINI_N
2
IN
17 89
PLACEMENT_NOTE=Place close to J3401. OUT
17 23 32
L3405
NC NC
PP5V_S3_BTCAMERA_F I2C_ALS_SDA BI I2C_ALS_SCL IN 45
275 mA peak 206 mA nominal max 2 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V
ALS CAMERA
45
95 95
95 95
USB_CAMERA_CONN_P USB_CAMERA_CONN_N
L3402 90-OHM
CONN_USB2_BT_P CONN_USB2_BT_N
DLP0NS SYM_VER-1
26 27 28 29 30
1
FERR-120-OHM-1.5A 1 C3452 0.1uF
20% 10V CERM 402
4
3
USB_CAMERA_P
OUT
20 90
1
2
USB_CAMERA_N
OUT
20 90
0402-LF
=PP5V_S3_BTCAMERA MIN_LINE_WIDTH=0.5 mm
8
MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V
2
PLACEMENT_NOTE=Place close to J3401.
32
B
BLUETOOTH
L3403 90-OHM DLP0NS SYM_VER-1
4
3
USB_BT_P
BI
20 90
1
2
USB_BT_N
BI
20 90
PLACEMENT_NOTE=Place close to J3401.
PP5V_WLAN_F =PP3V3_S3_WLAN
8
31
1
R3453 33K
U3402
TC7SZ08AFEAPE 5 SOT665
MINI_RESET_CONN_L
4
A
2
74LVC1G17DRL SOT-553 WLAN_SMIT_BUF 4
2
Y U3401 1
WLAN_SMIT_RC
NC
B
3
1
NC
3
MINI_RESET_L
A
5% 1/16W MF-LF 2 402
5
C3453 1
IN
26
1UF
10% 6.3V 2 CERM 402
Right Clutch Connector
1
R3454 62K
SYNC_MASTER=YITE_M98_MLB
5% 1/16W MF-LF 2 402
SYNC_DATE=07/02/2008
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
31
1
96
A
8
6
7
D
2
3
4
5
1
D
EXPRESSCARD/34 FLEX CONNECTOR L3502 90-OHM
CRITICAL
DLP0NS
J3500
SYM_VER-1
90 20
BI
USB_EXCARD_N
4
90 20
BI
USB_EXCARD_P
1
3
USB2_EXCARD_CONN_N 7
32 95
2
USB2_EXCARD_CONN_P 7
32 95
502250-8727 F-RT-SM
32 8
PLACEMENT_NOTE=Place close to J3500
L3503 90-OHM-100MA
=PP3V3_S3_EXCARD 1
0.1uF
89 17 7
DLP11S SYM_VER-1
C3530 1 C3531
20% 2 10V CERM 402
95 89 32 7
10uF
89 17
20% 2 6.3V X5R 603
IN
4
PCIE_CLK100M_EXCARD_N
3
PCIE_CLK100M_EXCARD_CONN_N
7 32 95
OUT
95 32 7 32 7
89 17
IN
1
PCIE_CLK100M_EXCARD_P
2
PCIE_CLK100M_EXCARD_CONN_P
32 7 7 32 95 32 7
PLACEMENT_NOTE=Place close to J3500
32 7
32 8
PLACEMENT_NOTE=Place close to J3500
=PP1V5_S0_EXCARD 1
C3534 1 C3535 0.1uF
20% 2 10V CERM 402
10uF
20% 2 6.3V X5R 603
89 17
IN
89 17
IN
C3571 1 2
PCIE_EXCARD_R2D_C_N PCIE_EXCARD_R2D_C_P
PCIE_EXCARD_R2D_N PCIE_EXCARD_R2D_P
0.1uF
1
2 0.1uF 10%
10%
45
16V X5R 402
BI
7 32 89 95
32 7
7 32 89 95
95 32 7
2 4 6 8 10 12 14 16 18 20 22 NC 24 26
PCIE_EXCARD_R2D_N PCIE_EXCARD_D2R_P PCIE_CLK100M_EXCARD_CONN_N EXCARD_CLKREQ_CONN_L PP3V3_S0_EXCARD_SWITCH PP3V3_S3_EXCARD_SWITCH PP1V5_S0_EXCARD_SWITCH =SMBUS_EXCARD_SDA EXCARD_CPUSB_L USB2_EXCARD_CONN_N
16V X5R 402
C3570
C
1 3 5 7 9 11 13 15 17 19 21 23 25 27
PCIE_EXCARD_R2D_P
7 32 89 95
PCIE_EXCARD_D2R_N OUT 7 17 89 PCIE_CLK100M_EXCARD_CONN_P 7 32 95 EXCARD_CPPE_L 7 32 PP3V3_S0_EXCARD_SWITCH 7 32 PLT_RESET_SWITCH_L 7 32 PCIE_WAKE_L OUT 17 23 31 PP1V5_S0_EXCARD_SWITCH 7 32 =SMBUS_EXCARD_SCL BI 45 NC
USB2_EXCARD_CONN_P 7
32 95
29
PLACEMENT_NOTE=Place close to J3500
32 7
R3501
EXCARD_CPPE_L
01 MF-LF 402
2
5% 1/16W
C
PCIE_EXCARD_PRSNT_L
17
OUTPUT DECOUPLING PP3V3_S3_EXCARD_SWITCH
7 32
VOLTAGE=3.3V MIN_LINE_WIDTH=.3mm MIN_NECK_WIDTH=0.2mm
TPS2231 17
=PP3V3_S0_EXCARD 8 =PP1V5_S0_EXCARD
2 12
32 8 32
42
B
IN
26
IN
43 20
IN
SMC_EXCARD_PWR_EN TP_EXCARD_STBY_L EXCARD_RESET_L EXCARD_OC_L
R3500
01 MF-LF 402
2
EXCARD_SHDN_L_R
5% 1/16W
20 1 6 19
NC 4 NC 5 NC 13 NC 14 NC 16
QFN AUXOUT VIN3P3 VOUT3P3 VIN1P5 VOUT1P5 AUXIN
SHDN*
PERST*
STBY* SYSRST*
CPPE* CPUSB*
CRITICAL
10uF
20% 2 10V CERM 402
U3500
=PP3V3_S3_EXCARD
C3500 1 C3503 0.1uF
CRITICAL
32 8
1
20% 2 6.3V X5R 603
J3501 503219-0221 M-ST-SM 24
15 3 11
VOLTAGE=3.3V MIN_LINE_WIDTH=.6mm MIN_NECK_WIDTH=0.2mm
8 10 9
PP3V3_S0_EXCARD_SWITCH 1
23 7 32
C3501 C3504 1
0.1uF
9
10uF
10% 2 16V X5R 402
20% 2 6.3V X5R 603
VENICE
OC* NC0
RCLKEN
18 EXCARD_RCLKEN
32
PP1V5_S0_EXCARD_SWITCH MIN_LINE_WIDTH=.6mm MIN_NECK_WIDTH=0.2mm
THRML_PAD
PCIE_FC_R2D_C_P PCIE_FC_R2D_C_N 1 10%
2 0.1uF
10%
IN
95 9
IN
0.1uF
95
16V X5R 402
95
PCIE_CLK100M_FC_P PCIE_CLK100M_FC_N
95 9 95 9
PCIE_FC_R2D_P PCIE_FC_R2D_N OUT OUT
2
3
4
5
16V X5R 402
C3572 VENICE PLACEMENT_NOTE=Place close to J3501.
10uF
20% 2 6.3V X5R 603
95 9
FC_CLKREQ_L
1
PCIE_FC_D2R_P PCIE_FC_D2R_N
B
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NC NC NC NC
=PP3V3_FC_CON
8
=PP1V5_FC_CON
8
FC_PRSNT_L FC_RESET_L
7
GND
IN
C3502 C3505
10% 2 16V X5R 402
21
IN
95 9
1
0.1uF
NC3 NC4
1
95 9 7 32
VOLTAGE=1.5V
NC1 NC2
C3573 1 2
OUT
PLT_RESET_SWITCH_L 7 EXCARD_CPPE_L 7 EXCARD_CPUSB_L 7
OUT
9
OUT
9
25
32
26
32
VENICE
32
Venice Connector 32 8
=PP3V3_S3_EXCARD 32 8
A
32 7
32 7
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28
INPUT DECOUPLING
5
EXCARD_CPUSB_L
1
EXCARD_CPPE_L
2
U3551
ExpressCard Connector
R35611
74HC1G00GWDG SC70-5 4
=PP3V3_S0_EXCARD
100K SMC_EXCARD_CP
OUT
1% 1/16W MF-LF 402 2
42 43
32
EXCARD_RCLKEN
EXCARD_CLKREQ_CONN
5 1
2
74HC1G00GWDG SC70-5 4
U3560
EXCARD_CLKREQ_L
SYNC_MASTER=YITE_M98_MLB OUT
17
3
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
3
C3550 1
A2
0.1uF
20% 10V CERM 2 402
32 7
EXCARD_CLKREQ_CONN_L
U3561 SN74LVC1G04YZPR
B1
C2 BGA C1
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
C3560 1
II NOT TO REPRODUCE OR COPY IT
0.1uF
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
20% 10V CERM 2 402
SIZE
DRAWING NUMBER
D APPLE INC.
7
6
5
4
3
2
REV.
051-7546
SCALE
SHT NONE
8
SYNC_DATE=07/02/2008
NOTICE OF PROPRIETARY PROPERTY
A.0.0 OF
32
1
96
A
6
7
D
C3710 1 C3711 1 0.1UF =PP3V3_ENET_PHY (43mA typ - 1000base-T) (19mA typ - Energy Detect) WF: Marvell numbers, update for Realtek
2
3
4
5
10% 16V 2 X5R 402
8
1
0.1UF
1
=PP1V05_ENET_PHY 8 (221mA typ - 1000base-T) ( 7mA typ - Energy Detect) WF: Marvell numbers, update for Realtek
D
CRITICAL
10% 16V 2 X5R 402
L3715
FERR-120-OHM-1.5A 0402-LF
1
1
C3700 0.1UF
CRITICAL
L3705 FERR-120-OHM-1.5A
10% 2 16V X5R 402
1
C3701 0.1UF
10% 16V 2 X5R 402
1
C3702
2
0.1UF
10% 16V 2 X5R 402
PP1V05_ENET_PHYAVDD
C3714 1
0402-LF
C3715 1 C3716 1
0.1UF
0.1UF
10% 16V X5R 2 402
2
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
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8
0.1UF
10% 16V X5R 2 402
10% 16V 2 X5R 402
PP3V3_ENET_PHYAVDD MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V
1
C3705 0.1UF
10% 2 16V X5R 402
1
C3706 0.1UF
10% 16V 2 X5R 402
=PP3V3_ENET_PHY_VDDREG
9
If internal switcher is used, must place 1x 22uF & 1x 0.1uF caps within 5mm of U3700 pins 44 & 45.
9
IN
=RTL8211_ENSWREG
IN
ENET_CLK125M_TXCLK
1 22 2
ENET_CLK125M_TXCLK_R
PLACE R3796 CLOSE TO U1400, PIN D24
91 18
IN
ENET_TXD ENET_TXD ENET_TXD ENET_TXD
91 18
IN
ENET_TX_CTRL
91 18
IN
91 18
IN
91 18
39
ENSWREG
10 40 AVDD12
3
44 45
15 21 37
U3700
ENET_RESET_L
1
0
IN
91 18
IN
91 18
BI
ENET_MDC ENET_MDIO
ENET_RESET_L is not asserted when WOL is active. Hence, RC (R3725 and C3725) are made NOSTUFF.
B
RTL8211_PHYRST_L
2
5% 1/16W MF-LF 402
NO STUFF
4.7K
=RTL8211_REGOUT 9 If internal switcher is used, must place inductor within 5mm of U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor.
4.7K
5% 1/16W MF-LF
5% 1/16W MF-LF 402 2
2 402
C
If internal switcher is not used, VDDREG and REGOUT can float.
REGOUT
48
RXC
19
RXD[0] RXD[1]/TXDLY RXD[2]/AN0 RXD[3]/AN1
14 16 17 18
RXCTL
13
RTL8211CLGR
22
TXC
23 24 25 26
TXD[0] TXD[1] TXD[2] TXD[3]
27
TXCTL
30 31
MDC MDIO
RGMII/MII
1
29
PHYRSTB*
0.1UF
RTL8211_RSET
20% 2 10V CERM 402
TP_RTL8211_CLK125
46
32
RSET
CLOCK
2.49K
IN
RTL8211_CLK25M_CKXTAL1 TP_RTL8211_CKXTAL2
42 43
91 91
ENET_RXD_R ENET_RXD_R ENET_RXD_R ENET_RXD_R
R3791 R3792 R3793 R3794
22 22 22 22
1 1 1 1
2 2 2 2
ENET_RXCTL_R
R3795
22
1
2
ENET_MDI_P ENET_MDI_N
BI
35 91
BI
35 91
MDI+[1] MDI-[1]
4 5
ENET_MDI_P ENET_MDI_N
BI
35 91
BI
35 91
MDI+[2] MDI-[2]
8 9
ENET_MDI_P ENET_MDI_N
BI
35 91
BI
35 91
MDI+[3] MDI-[3]
11 12
ENET_MDI_P ENET_MDI_N
BI
35 91
BI
35 91
LED0/PHYAD0 LED1/PHYAD1 LED2/RXDLY
34 35 38
RTL8211_PHYAD0 RTL8211_PHYAD1 RTL8211_RXDLY
CKXTAL1 CKXTAL2
LED
1
ENET_CLK125M_RXCLK
2 5%
1/16W MF-LF 402
5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W
5%
1/16W MF-LF 402
MF-LF MF-LF MF-LF MF-LF
402 402 402 402
ENET_RXD ENET_RXD ENET_RXD ENET_RXD ENET_RX_CTRL
OUT
18 91
OUT
18 91
OUT
18 91
OUT
18 91
OUT
18 91
OUT
18 91
B
GND
C3790
7 20 33 47
91 34
91
22
CLK125
R37301 1% 1/16W MF-LF 402 2
REFERENCE
91
R3790
ENET_CLK125M_RXCLK_R
1 2
RESET MEDIA DEPENDENT
C3725
91
MDI+[0] MDI-[0]
MANAGEMENT
R3724 IN
5% 1/16W MF-LF 402 2
R37521
R3751
TQFP
5% 1/16W 402 MF-LF
91 18
1
4.7K
OMIT
2 402
R3796 91 18
28 36
5% 1/16W MF-LF
DVDD12
4.7K
FB12
5% 1/16W MF-LF 402 2
VDDREG
Alias to =PP3V3_ENET_PHY for internal switcher. Alias to GND for external 1.05V supply.
R3725
AVDD33
10K
C
1
DVDD33
NO STUFF
R37201
6 41
NOTE: VDDREG rise time must be >1ms to avoid damage to switcher.
R37501
1
10PF
5% 50V CERM 2 402
R37551 R37561 4.7K
5% 1/16W MF-LF 402 2
4.7K
5% 1/16W MF-LF 402 2
1
R3757 4.7K 5% 1/16W MF-LF
2 402
Reserved for EMI per RealTek request.
Ethernet PHY (RTL8211CL) SYNC_MASTER=SUMA_M98_MLB
A
SYNC_DATE=07/01/2008
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
Configuration Settings: PHYAD AN[1:0] RXDLY TXDLY
= = = =
01 11 0 0
SIZE
(PHY Address 00001) (Full auto-negotiation) (RXCLK transitions with data) (No TXCLK Delay)
8
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
33
1
96
A
8
6
7
2
3
4
5
1
3.3V ENET FET @ 2.5V Vgs: Rds(on) = 90mOhm max I(max) = 1.7A (85C)
CRITICAL
Q3810 NTR4101P SOT-23-HF
=PP3V3_S5_P3V3ENETFET
8
=PP3V3_ENET_FET S
2
D
5% 1/16W MF-LF 402 2
R3810 P3V3ENET_EN_L
1
10% 2 16V X5R 402
1
C3810 0.01UF
100K 2
P3V3ENET_SS
2
5% 1/16W MF-LF 402
D 3
D
G
0.033UF
10K
Q3801
C3811
1
R38001
8
D 3
1
10% 16V CERM 402
SSM6N15FEAPE
5 9
IN
G
www.laptop-schematics.com
SOT563
S 4
=P3V3ENET_EN
MOBILE: Recommend aliasing PM_SLP_RMGT_L and =P3V3ENET_EN. Nets separated on ARB for alternate power options.
WLAN Enable Generation "WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0")) NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal. PM_WLAN_EN_L OUT 31 Pull-up is with power FET.
C Q3805
1.05V ENET FET
D 6
SSM6N15FEAPE SOT563
2 31 21
IN
G
8
=PP1V05_ENET_P1V05ENETFET 1.8V Vgs
S 1
AP_PWR_EN
C3840 1
Q3805
6
D
SSM6N15FEAPE
8
Q3801
1
SOT563
43 42 37 21
IN
S 4
1
S
100K 2
Q3841
IN
P1V05ENET_EN_L
PM_SLP_S3_L
1
10K
SOT23
2
2
G
=PP1V05_ENET_FET
1
S 1
8
C3841 0.01UF
10% 2 16V CERM 402
2
1% 1/16W MF-LF 402
D 3
Q3841
D
6
SOT563
R3841 83 81 68 44 42 37 21 7
SI2312BDS
G
SSM6N15FEAPE
1% 1/16W MF-LF 402 2
SMC_ADAPTER_EN
Q3840 1
S
69.8K
G 2
CRITICAL
D
P1V05ENET_SS
5% 1/16W MF-LF 402
R38421 G
20% 10V CERM 2 402
R3840
=PP3V3_S5_P1V05ENETFET
SSM6N15FEAPE
SOT563
5
3
0.1UF
AC_OR_S0_L D 3
C
P1V05ENET_EN_L_RC
SSM6N15FEAPE SOT563
5
B
9
IN
G
S 4
B
=P1V05ENET_EN
Non-ARB: Recommend aliasing PM_SLP_RMGT_L and =P1V05ENET_EN. Nets separated on ARB for alternate power options.
RTL8211 25MHz Clock
Ethernet & AirPort Support
NOTE: MCP79 can provide 25MHz clock, but clock runs whenever RMGT rails are powered. Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal.
A
SYNC_MASTER=SUMA_M98_MLB
SYNC_DATE=07/01/2008
NOTICE OF PROPRIETARY PROPERTY
R3895 91 18
IN
MCP_CLK25M_BUF0_R
1
22
2
RTL8211_CLK25M_CKXTAL1
OUT
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
33 91
5% 1/16W MF-LF 402 PLACEMENT_NOTE=Place close to U1400
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
34
1
96
A
8
6
7
2
3
4
5
1
Page Notes Power aliases required by this page: (NONE) Signal aliases required by this page: (NONE) BOM options provided by this page: (NONE)
D
D
Place one of 0.1uf cap close to each centertap pin of transformer
1
C3900
1
0.1UF 2
1
C3902 0.1UF
10% 16V X5R 402
2
1
C3904 0.1UF
10% 16V X5R 402
www.laptop-schematics.com
ENETCONN_CTAP C3906 0.1UF
10% 16V
10% 16V
2 X5R
2 X5R
402
402
CRITICAL
91 33
91 33
BI
BI
T3900 SM
ENET_MDI_P
1
12
ENETCONN_P
ENET_MDI_N
2
95 11
ENETCONN_N
3
10
ENET_CTAP0
4
9
ENET_CTAP1
8
95
ENETCONN_N
7
95
ENETCONN_P
95
CRITICAL
J3900
RJ45-M97-2
TX
C
F-RT-TH
TLA-6T213HF 91 33
BI
ENET_MDI_N
5
91 33
BI
ENET_MDI_P
6
C
9 10
1 2 3
RX
4 5
CRITICAL
91 33
BI
ENET_MDI_N
1
91 33
BI
ENET_MDI_P
2
T3901 SM
6 7 95 12
ENETCONN_N
8
11
ENETCONN_P
11
10
ENET_CTAP2
9
ENET_CTAP3
95
12
3 TX
514-0596
TLA-6T213HF 4
91 33
91 33
BI
ENET_MDI_N
5
8
95
ENETCONN_N
BI
ENET_MDI_P
6
7
95
ENETCONN_P
RX
Transformers should be mirrored on opposite sides of the board
B
R39001 R39011 75
5% 1/16W MF-LF 402 2
75
5% 1/16W MF-LF 402 2
1
R3902 75
5% 1/16W MF-LF 2 402
1
R3903 75
B
CRITICAL
5% 1/16W MF-LF 2 402
C3908 1000PF
ENET_BOB_SMITH_CAP MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm
1
2
10% 2KV CERM 1206
Ethernet Connector SYNC_MASTER=SUMA_M98_MLB
A
SYNC_DATE=07/01/2008
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
35
1
96
A
8
6
7
2
3
4
5
=PP3V3_FW_FWPHY 138 mA
7 mA I/O
C4120 1
C4121 1 C4122 1
1UF
1UF
10% 6.3V 2 CERM 402
8 36 38
C4123 1 C4124 1
1UF
10% 6.3V 2 CERM 402
1
1UF
10% 6.3V 2 CERM 402
1UF
10% 6.3V 2 CERM 402
10% 6.3V 2 CERM 402
L4130
120-OHM-0.3A-EMI 114 mA FireWire PHY PP3V3_FW_FWPHY_VDDA 1 2
D
C4130 1 C4131 1 1UF
C4132 1
1UF
10% 6.3V 2 CERM 402
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V
1UF
10% 6.3V 2 CERM 402
10% 6.3V 2 CERM 402
L4110
=PP1V0_FW_FWPHY 135 mA
L4135
120-OHM-0.3A-EMI 1 2 PP1V0_FW_FWPHY_AVDD
25 mA PCIe SerDes
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.0V
0402-LF
1
C4110 1UF
10% 2 6.3V CERM 402
1
C4111 1UF
C4135 1
C4136 1
10% 6.3V 2 CERM 402
10% 6.3V 2 CERM 402
1UF
10% 2 6.3V CERM 402
110 mA Digital Core 1
C4100 1UF
10% 2 6.3V CERM 402
1
C4101 1UF
10% 2 6.3V CERM 402
1
120-OHM-0.3A-EMI 1 2 PP3V3_FW_FWPHY_VP25
17 mA PCIe SerDes
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V
0402-LF
www.laptop-schematics.com
8
D
0402-LF
1UF
0 mA VReg PWR
C4102 1UF
10% 2 6.3V CERM 402
1
C4103 1UF
10% 2 6.3V CERM 402
1
C4104
1
1UF
C4105 1UF
10% 2 6.3V CERM 402
10% 2 6.3V CERM 402
1
C4106
C4141 1
1UF
0.1UF
20% 10V CERM 2 402
10% 2 6.3V CERM 402
1
C4140 1UF
10% 2 6.3V CERM 402
C
C
VDD10
=PPVP_FW_PHY_CPS
R41601
B
390K
5% 1/16W MF-LF 402 2
C4150
R4150
22PF
1
2 1
NC
1
412
2
1% 1/16W MF-LF 402
SM-3.2X2.5MM
R41611 2.94K
1% 1/16W MF-LF 402 2
3
22PF
1
Y4150 24.576MHZ
4
C4151 NC
2
5% 50V CERM 402
FW_CLK24P576M_XO CRITICAL
2
1
R4170 191
1% 1/16W MF-LF 2 402
5% 50V CERM 402
R41621 470K
5% 1/16W MF-LF 402 2
IN
38
IN
38
IN
92 38
BI
92 38
BI
92 38
BI
92 38
BI
38
BI
38
BI
92 38
BI
92 38
BI
92 38
BI
92 38
BI
38
BI
38
BI
38
BI
38
BI
38
BI
=FW_PHY_DS0 =FW_PHY_DS1 =FW_PHY_DS2
B8 A8 B5 A5 B3 A3 B9 A9 B6 A6 B4 A4
FW_P0_TPBIAS FW_P1_TPBIAS FW_P2_TPBIAS
B7 TPBIAS0 C3 TPBIAS1 A2 TPBIAS2
L6 L9
L5 L10
A12 D5 D6 D8
K12
REFCLKN N9 REFCLKP N10
PCI EXPRESS PHY
89 89 89
0.1UF
PCIE_FW_R2D_N PCIE_FW_R2D_P PCIE_FW_D2R_C_N PCIE_FW_D2R_C_P
M4 N2 M1 M3
TP_FW643_TCK TP_FW643_TDI TP_FW643_TDO TP_FW643_TMS
NT-2 (IPU) TRST*
N1
FW643_TRST_L
IN
17 89
PCIE_FW_R2D_C_P
IN
17 89
C4175 1
10% 2 16V PCIE_FW_D2R_N OUT 17 89 X5R 402 10% 2 16V PCIE_FW_D2R_P OUT 17 89 0.1UF X5R 402 PLACEMENT_NOTE=Place C4175 close to U4000 PLACEMENT_NOTE=Place C4176 close to U4000
0.1UF
C4176 1
PCIE_CLK100M_FW_N PCIE_CLK100M_FW_P
NT-4 (IPU) TCK NT-3 (IPU) TDI (IPU) TDO NT-1 (IPU) TMS
WAKE* FIXME!!! - TYPO IN SYMBOL REGCTL REGCLT POWER MANAGEMENT VAUX_DETECT NT-12 (IPD) VAUX_DISABLE NT-13 (OD) CLKREQN
IN
17 89
IN
17 89
=PP3V3_FW_FWPHY
C2 D13 E1 D2 L2
8 36 38
FW643_LDO
R41651
FW_PME_L FW643_REGCTL FW643_VAUX_DETECT TP_FW643_VAUX_ENABLE FW_CLKREQ_L
OUT
19
OUT
17
5% 1/16W MF-LF 402 2
1
R4166 10K
5% 1/16W MF-LF 2 402
B
1
R4164 10K
NAND_TREE REXT XO XI NT-9
TP_FW643_SE TP_FW643_SM TP_FW643_MODE_A TP_FW643_CE TP_FW643_FW620_L TP_FW643_JASI_EN TP_FW643_AVREG TP_FW643_VBUF FW643_PU_RST_L
M13 N13 J2 L13 D12 D1 A10 H13 K13
SE (IPD) SM (IPD) MODE_A (IPD) NT-18 CE (IPD) FW620* (IPU) JASI_EN (IPD) NT-11 AVREG VBUF FW_RESET* (IPU) NT-8
J12 OCR_CTL_V10 J13 OCR_CTL_V12
NT-16 (IPD) SCIFCLK NT-14 (IPD) SCIFDAIN NT-17 SCIFDOUT NT-15 (IPD) SCIFMC
SCIF
NT-OUT NOTE: NT-xx notes show NAND tree order.
SERIAL EEPROM CONTROLLER
NT-7 NT-6
SCL SDA
G2 G1 H1 F2
TP_FW643_SCIFCLK TP_FW643_SCIFDAIN TP_FW643_SCIFDOUT TP_FW643_SCIFMC
N12 M11
FW643_SCL TP_FW643_SDA
N4
FW_RESET_L
5% 1/16W MF-LF 2 402
MISCELLANEOUS CHIP RESET
NT-5
PERST*
IN
26
1
R4163 10K
5% 1/16W MF-LF 2 402
(Reserved) VSS
10% 2 6.3V CERM-X5R 402
89
BGA
NT-10 (IPD)
K1 L8 F13 G13
0.33UF
N8 N7 N5 N6
PCIE_FW_R2D_C_N
10K
TP_FW643_NAND_TREE FW643_REXT FW_CLK24P576M_XO_R FW_CLK24P576M_XI
NC
FW643
1394 PHY
B11 R0 B10 TPCPS
C4162
PCIE_RXD0N PCIE_RXD0P PCIE_TXD0N PCIE_TXD0P
TEST CONTROLLER
FW643_R0 FW643_TPCPS
TP_FW643_OCR10_CTL 1
TPA0N TPA0P TPA1N TPA1P TPA2N TPA2P TPB0N TPB0P TPB1N TPB1P TPB2N TPB2P
0.1UF
C4171 1
VREG_PWR
U4100
(IPD) NT-19 (IPD) NT-20 (IPD) NT-21
FW_P0_TPA_N FW_P0_TPA_P FW_P1_TPA_N FW_P1_TPA_P FW_P2_TPA_N FW_P2_TPA_P FW_P0_TPB_N FW_P0_TPB_P FW_P1_TPB_N FW_P1_TPB_P FW_P2_TPB_N FW_P2_TPB_P
VP25
OMIT CRITICAL
B13 ATBUSB A13 ATBUSH A11 ATBUSN F12 DS0 E12 DS1 E13 DS2
VP
VREG_VSS
B2 D4 D7 D9 D10 E4 E5 E9 F4 F6 F7 F8 F10 G4 G6 G7 G8 G10 H4 H6 H7 H8 H10 J4 J5 J9 J10 K4 K5 K7 K8 K9 L7 K6 K10
38
38
VDDH
VDD33
10% 2 16V X5R 402 10% 2 16V X5R 402
L12
NC NC NC
C1 C12 F1 G12 J1 L3 L11 M2
A1 B1 B12 C13 E2 E10 H2 H12 K2 L1 M12 N3 N11
PLACEMENT_NOTE=Place C4170 close to U1400 PLACEMENT_NOTE=Place C4171 close to U1400
C4170 1
FireWire LLC/PHY (FW643) SYNC_MASTER=SENSOR
A
SYNC_DATE=08/14/2008
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
36
1
96
A
8
6
7
2
3
4
5
1
Page Notes Power aliases required by this page: - =PPBUS_S5_FWPWRSW (system supply for bus power) - =PP3V3_FW_LATEVG_ACTIVE - =PPVP_FW_SUMNODE (power passthru summation node)
FireWire Port Power Switch
Signal aliases required by this page: (NONE)
CRITICAL
BOM options provided by this page: - FW_PORT_FAULT_PU
D
8
1
R4260
C4260 1
470K
PWRDI5 2
=PPBUS_S5_FW_FET
1.5A-24V 8 7 6 5
3 2 1
D4260
F4260
SOI-HF
=PPBUS_S5_FWPWRSW
CRITICAL
OMIT CRITICAL
Q4260 NDS9407 PPBUS_FW_FWPWRSW_F MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V
1
2
1812L15024HF
PPBUS_FW_FWPWRSW_D MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V
D
8
3 1
PDS540XF
0.01uF
5% 1/16W MF-LF 2 402
20% 16V CERM 2 402
4
FWPWR_EN_L_DIV 1
www.laptop-schematics.com
R4261 330K
5% 1/16W MF-LF 2 402
FWPWR_EN_L Enables port power when machine is running or on AC. Q4261 D SSM6N15FEAPE
6
Q4261
D 3
SSM6N15FEAPE
SOT563
SOT563
2 43 42 34 21
83 81 68 44 42 34 21 7
IN
SMC_ADAPTER_EN
IN
PM_SLP_S3_L
G
S 1
5
G
S 4
FW_PORTPWR_EN_FET
C
C
Q4262 SSM3K15FV
D 3
SOD-VESM-HF
1
37
G
S 2
FW_PORTPWR_EN
Late-VG Event Detection 8 38
B
=PP3V3_FW_LATEVG_ACTIVE PP2V4_FW_LATEVG
R42111 10K
5% 1/16W MF-LF 402 2
1
1
R4212 2
4 V+
FWLATEGV_3V_REF
R4219 2.0M
3
5% 1/16W MF-LF 2 402
U4210
D4219
LMC7211 SM-HF 1
V-
LATEVG_EVENT_L
SOD-123 2 1
MBR0540XXH 5
C4211 1 100pF
5% 50V CERM 2 402
FW_PORTPWR_EN 1
37
C4219 0.33UF
1
10% 2 10V CERM-X5R 603
R4213 80.6K
1% 1/16W MF-LF 2 402
B
1
20% 2 10V CERM 402
1% 1/16W MF-LF 2 402
P2V4_FWLATEVG_RC
C4210 0.1UF
10K
R4210 1
200K 2 1% 1/16W MF-LF 402
FWLATEVG_3V_REF Hysteresis: 2.95V when port power is on 2.81V on late Vg event and port power is off
FireWire Port Power SYNC_MASTER=SENSOR
A
SYNC_DATE=08/14/2008
NOTICE OF PROPRIETARY PROPERTY
PART NUMBER 740S0080
QTY 1
DESCRIPTION LITTLEFUSE, 1.5A RESETTABLE 24V
REFERENCE DES
CRITICAL
F4260
CRITICAL
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
BOM OPTION
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
37
1
96
A
8
6
7
2
3
4
5
1
Page Notes Power aliases required by this page: 38 36 8
- =PPVP_FW_PORT1 - =PP3V3_FW_LATEVG
=PP3V3_FW_FWPHY
R43821 R43801 10K
1% 1/16W MF-LF 402 2
FWPHY_DS0
FireWire PHY Config Straps
Signal aliases required by this page: (NONE) NOTE: This page is expected to contain the necessary aliases to map the FireWire TPA/TPB pairs to their appropriate connectors and/or to properly terminate unused signals.
FWPHY_DS2
Configures PHY for:
FWPHY_DS1
- 1-port Portable Power Class (0) 10K
36 36 92 36 92 36
36
92 36
Termination
92 36 36
Place close to FireWire PHY
0.33UF
NC_FW0_TPBIAS MAKE_BASE=TRUE NC_FW2_TPBIAS MAKE_BASE=TRUE NC_FW0_TPAN MAKE_BASE=TRUE NC_FW0_TPAP MAKE_BASE=TRUE NC_FW2_TPAN MAKE_BASE=TRUE NC_FW2_TPAP MAKE_BASE=TRUE
FW_P0_TPB_N FW_P0_TPB_P FW_P2_TPB_N FW_P2_TPB_P
NC_FW0_TPBN NC_FW0_TPBP NC_FW2_TPBN NC_FW2_TPBP
G
D
Cable Power
R43111
PPVP_FW_CPS MAKE_BASE=TRUE MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=12.6V
5% 1/16W MF-LF 402 2
=PPVP_FW_PHY_CPS
CRITICAL
36
L4310
8
38 37
DP4310
1% 1/16W MF-LF 2 402 92 36
5% 1/16W MF-LF 402 2
1% 1/16W MF-LF 402 2
FW_P1_TPA_N
FW_PORT1_TPA_N
92 36
FW_P1_TPB_P
FW_PORT1_TPB_P
6
38
D
MAKE_BASE=TRUE
FW_P1_TPB_N
FW_PORT1_TPB_N MAKE_BASE=TRUE
=PP3V3_FW_FWPHY
38 36 8
2
R4362 56.2
1% 1/16W MF-LF 2 402
SOT-363 2
CRITICAL
6
J4310
1394B-M97
1
F-RT-TH1
BSS8402DW
G S
38
SIGNAL_MODEL=EMPTY 1 SIGNAL_MODEL=EMPTY 1
B
10% 50V 2 X7R 402
Q4300 38
MAKE_BASE=TRUE 92 36
1
0.01uF 38
MAKE_BASE=TRUE 92 36
BILINGUAL
BAV99DW-X-G
C4310 FW_PORT1_TPA_P
PORT 1
3 4
DP4310 CPS_EN_L
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=33V
10% 2 50V X7R 402
SOT-363 5
10% 50V 2 X7R 402
330K
56.2
FW_P1_TPA_P
0.01uF
R43121
R4361
C4314 0.01UF
BAV99DW-X-G
C4311 1 56.2
SM 1
PP2V4_FW_LATEVG
CPS_EN_L_DIV
R4360
FERR-250-OHM Note: Trace PPVP_FW_PORT1 must handle up to 5A 1 2 PPVP_FW_PORT1_F
=PPVP_FW_PORT1
"Snapback" & "Late VG" Protection
5
470K
SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY 1
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
C 3
=PPVP_FW_PHY_CPS_FET
S
8
4
10% 2 6.3V CERM-X5R 402
BSS8402DW
SOT-363
(SYM-VER2)
C4360
FW_P0_TPBIAS FW_P2_TPBIAS FW_P0_TPA_N FW_P0_TPA_P FW_P2_TPA_N FW_P2_TPA_P
Q4300
36
TI PHYs require 1uF even though FW spec calls out 0.33uF
1
D
1% 1/16W MF-LF 402 2
36
1
36
R43811
- Port "1" Bilingual (1394B)
1394b implementation based on Apple FireWire Design Guide (FWDG 0.6, 5/14/03)
C
36
=FW_PHY_DS1
MAKE_BASE=TRUE
NOTE: FireWire TPA/TPB pairs are NOT constrained on this page. It is assumed that FireWire PHY page will provide the appropriate constraints to apply to entire TPA/TPB XNets.
FW_P1_TPBIAS
36
=FW_PHY_DS2
MAKE_BASE=TRUE
BOM options provided by this page: (NONE)
36
=FW_PHY_DS0
MAKE_BASE=TRUE
38
SOT-363
FW_PORT1_TPB_N
1 9
(FW_PORT1_BREF)
(SYM-VER1) 38
1
FW_PORT1_TPB_P
2 8
R4363
NC7
56.2
(GND_FW_PORT1_VG)
1% 1/16W MF-LF 402 2
38
FW_PORT1_TPA_N
38
FW_PORT1_TPA_P
5 4
DP4311 SOT-363 2
220pF
1% 1/16W MF-LF 402 2
0.01uF
10% 50V 2 X7R 402
0.1uF
DP4311 SOT-363 5
3
C4313 1 0.01uF
10% 50V 2 X7R 402
OUTPUT
B INPUT
13 CHASSIS GND
14 15
1
R4319 1M
4
CABLE OUTER SHLD
12
10% 50V 2 X7R 603-1
BAV99DW-X-G
1
TPB(R)
TPBTPB VP TPB+ VP NC NC VG TPA- TPAVG TPA TPA(R) TPA+ TPA+
TPB+
11
C4319 1 6
C4312 1
TPB-
10
BAV99DW-X-G 1 1 C4364 R4364 4.99K
6 3
FW_PORT1_AREF
FW_PORT1_TPB_C
5% 2 25V CERM 402
www.laptop-schematics.com
D
10K
1% 1/16W MF-LF 402 2
- =GND_CHASSIS_FW_PORT1 - =GND_CHASSIS_FW_EMI_R
5% 1/16W MF-LF 2 402
PLACEMENT_NOTE=Place C4319 close to connector pin 5.
AREF needs to be isolated from all local grounds per 1394b spec
514S0605
When a bilingual device is connected to a beta-only device, there is no DC path between them (to avoid ground offset issue) BREF should be hard-connected to logic ground for speed signaling and connection
Late-VG Protection Power A
8
=PP3V3_FW_LATEVG
R4390 1
332
PP2V4_FW_LATEVG MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=2.4V
2
1% 1/16W MF-LF 402
3
PP2V4_FWLATEVG needs to be biased to at least 2.1V for FW signal integrity and should be biased to 2.4V for margin R4390 should be 390 Ohms max for a 3.3V rail
1
FireWire Ports SYNC_MASTER=SENSOR
SYNC_DATE=08/14/2008
37 38
NOTICE OF PROPRIETARY PROPERTY
ESD and late-VG rail CRITICAL for snap-back diodes D4390 (Common to all ports) MMBZ5227BLT1H
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT
SOT23
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
38
1
96
A
8
6
7
2
3
4
5
1
ODD Power Control CRITICAL
Q4590 6
FDC606P_G D
7
PP5V_SW_ODD
MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm VOLTAGE=5V
D
1
S
D
2 5
SOT-6
=PP5V_S0_ODD 4
8
0.068UF
5% 1/16W MF-LF 402
=PP3V3_S0_ODD
R4595 ODD_PWR_EN_LS5V_L
R4597
1
D 6
Q4596
10% 10V 2 CERM 402
100K 2
C4596 0.01UF 1
ODD_PWR_SS
5% 1/16W MF-LF 402
100K 5% 1/16W MF-LF 402
C4595
G
1
100K
2
10% 16V CERM 402
SSM6N15FEAPE SOT563
www.laptop-schematics.com
39 8
R4596
3
NOTE: 3.3V must be S0 if 5V is S3 or S5 to ensure the drive is unpowered in S3/S5.
ODD_PWR_EN G
2
Q4596
S 1
D 3
SSM6N15FEAPE SOT563
5 21
IN
G
S 4
ODD_PWR_EN_L
C
C
SATA ODD Port FL4520 90-OHM-100MA
PLACEMENT_NOTE=PLACE C4520 CLOSE TO MCP79 PLACEMENT_NOTE=PLACE C4521 NEXT TO C4520
DLP11S SYM_VER-1
CRITICAL 3
4
95
1
SATA_ODD_R2D_UF_P
0.01UF 2
J4500
CRITICAL
39 8
=PP3V3_S0_ODD
33K
5% 1/16W MF-LF 402 2
1
SATA_ODD_R2D_UF_N
0.01UF
C4521
SATA_ODD_R2D_C_P
IN
20 89
SATA_ODD_R2D_C_N
IN
20 89
10% 16V CERM 402 2
C4520
10% 16V
CERM 402
PLACEMENT_NOTE=Place FL4520 close to J4500
2
1
4
3
89 7
6
5
89 7
8
7
10
9
89 7
12
11
89 7
14
13
16
15
SATA_ODD_R2D_P SATA_ODD_R2D_N SATA_ODD_D2R_C_N SATA_ODD_D2R_C_P
FL4525
PLACEMENT_NOTE=PLACE C4526 CLOSE TO J4500 PLACEMENT_NOTE=PLACE C4525 NEXT TO C4526
C4526 1 0.01UF
516S0617 OUT
95
M-ST-SM-LF
R45901
42 7
1
55560-0168
2
C4525 1 0.01UF
SMC_ODD_DETECT
2
95
SYM_VER-1
CERM
2
SATA_ODD_D2R_UF_P
10% 16V CERM
CRITICAL 3 SATA_ODD_D2R_N
4
SATA_ODD_D2R_UF_N
10% 16V 95
90-OHM-100MA DLP11S
OUT
20 89
OUT
20 89
402 1
2
SATA_ODD_D2R_P
402
PLACEMENT_NOTE=Place FL4525 close to J4500
Indicates disc presence
B
B CRITICAL
1
C4501
C4502
1
0.1UF
J4501
20% 2 10V CERM 402
20374020E31 F-ST-SM 21
0.1UF
20% 2 10V CERM 402
CRITICAL
L4500
PLACEMENT_NOTE=PLACE C4501 CLOSE TO J4501 PLACEMENT_NOTE=PLACE C4502 CLOSE TO J4501
SATA HDD Port
FERR-70-OHM-4A 1
PP5V_S0_HDD_FLT
2
1
2
6 7 8 9
8
PLACEMENT_NOTE=Place C4510 close to MCP79 PLACEMENT_NOTE=Place C4511 next to C4510
FL4501 90-OHM-100MA
4 5
=PP5V_S0_HDD
0603
PLACEMENT_NOTE=PLACE L4500 CLOSE TO J4501
3
DLP11S SYM_VER-1
CRITICAL
NC NC
3 89
SATA_HDD_R2D_P
89
SATA_HDD_R2D_N
4
C4510 1
SATA_HDD_R2D_UF_P
0.01UF 2
NC
10
95
1
95
C4511 1
SATA_HDD_R2D_UF_N
0.01UF PLACEMENT_NOTE=Place FL4501 close to J4501
13
A
16 17
SATA_HDD_D2R_C_N
89
SATA_HDD_D2R_C_P
NC
14 15
89
SYM_VER-1
C4515 1 0.01UF 0.01UF
18
2
SATA_HDD_R2D_C_N
10% 16V CERM
IN
20 89
IN
20 89
OUT
20 89
402
402
90-OHM-100MA DLP11S
C4516 1
NC NC
SATA_HDD_R2D_C_P
10% 16V CERM
FL4502
11 12
2
2
95
SATA_HDD_D2R_UF_N
CRITICAL
4
3
1
2
SATA_HDD_D2R_N
SATA Connectors
10% 16V CERM 402 2
95
SATA_HDD_D2R_UF_P
SATA_HDD_D2R_P
SYNC_MASTER=CHANG_M98_MLB OUT
NOTICE OF PROPRIETARY PROPERTY
PLACEMENT_NOTE=PLACE FL4502 CLOSE TO J4501
PLACEMENT_NOTE=Place C4515 next to C4516 PLACEMENT_NOTE=Place C4516 close to J4501
19
SYNC_DATE=07/01/2008
20 89
10% 16V CERM 402
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
20
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT
22
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
518S0654
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
39
1
96
A
8
6
7
2
3
4
5
1
D
Port Power Switch
Left USB Port A
CRITICAL
CRITICAL
L4605
Q4690 8
2
PM_SLP_S4_L
68 43 42 21
20
USB_EXTA_OC_L
OUT
IN
OUT1
R4690
20
5% 1/16W MF-LF 2 402
USB_PWR_EN
1 1
10UF
20% 6.3V 2 X5R 603
1
0.47UF
10% 10V 2 X5R 402
1
1
J4600
20% 16V CERM 2 402
F-RT-TH-M97-3 5
L4600 90-OHM-100MA
6
SYM_VER-1
10UF
20% 2 10V CERM 402
USB
CRITICAL DLP11S
CRITICAL
C4695 1
0.1UF
CRITICAL
0.01uF
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V
9
C4691
C
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V
0603
C4605
PP5V_S3_RTUSB_B_ILIM
6
GND TPAD
C4690 C4692
OUT2
EN1 5 OC2* 4 EN2
USB_EXTB_OC_L
OUT
5.1K
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V
OC1*
3
1
PP5V_S3_RTUSB_A_ILIM
7
MSOP
8
FERR-220-OHM-2.5A 1 2 PP5V_S3_RTUSB_A_F
20% 6.3V 2 X5R 603
1
CRITICAL
C4696 C4617 10UF 100UF
20% 2 6.3V POLY-TANT CASE-B2-SM
20% 6.3V X5R 603
1
1
USB2_EXTA_MUXED_N
4
3
1
2
95
USB2_LT1_N
95
USB2_LT1_P
1
C4616 100UF
2
95
20% 2 6.3V POLY-TANT CASE-B2-SM
2 95
USB2_EXTA_MUXED_P
3 4
2 5 3 4 6 VBUS
NC IO NC IO
C
TPS2064DGN
=PP5V_S3_RTUSB
www.laptop-schematics.com
D
7 8
1 GND
514-0606 D4600 RCLAMP0502N SLP1210N6
CRITICAL We can add protection to 5V if we want, but leaving NC for now L4615 FERR-220-OHM-2.5A Place L4600 and L4605 at connector pin 1 2 PP5V_S3_RTUSB_B_F CRITICAL
0603
B
1
C4615
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V
B
0.01uF 20%
2 16V CERM
402
CRITICAL
J4610
USB/SMC Debug Mux
USB F-RT-TH-M97-3 5
SMC_DEBUG_YES 8
=PP3V42_G3H_SMCUSBMUX
CRITICAL
6
L4610
90-OHM-100MA DLP11S
SIGNAL_MODEL=USB_MUX
1
SYM_VER-1
1
R4650
0.1UF 44 43 42
IN
44 43 42
OUT
SMC_RX_L SMC_TX_L
20% 10V CERM 2 402
VCC 5 M+ 4 M-
BI
USB_EXTB_N
4
10K
9
C4650 1
90 20
U4650
Y+ 1 Y- 2
95
3 95
5% 1/16W MF-LF 2 402
90 20
BI
USB_EXTB_P
BI
90 20
BI
USB_EXTA_P USB_EXTA_N
7 D+ 6 D-
8
3
2 7
2 5 3 4 6 VBUS
TQFN
CRITICAL
8
1 GND
SEL 10
OE*
2
4 1
PI3USB102ZLE 90 20
USB_LT2_N USB_LT2_P
NC IO NC IO
SMC_DEBUG_YES
3
GND
USB_DEBUGPRT_EN_L SEL=0 Choose SMC SEL=1 Choose USB
IN
42
D4610 RCLAMP0502N SLP1210N6
External USB Connectors
CRITICAL
A
SYNC_MASTER=AMASON_M98_MLB
SMC_DEBUG_NO
R4651 1
0
5% 1/16W MF-LF 402
Left USB Port B
2
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
SMC_DEBUG_NO
R4652 0
1
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT
2
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
5% 1/16W MF-LF 402
SIZE
DRAWING NUMBER
D APPLE INC.
7
6
5
4
3
2
REV.
051-7546
SCALE
SHT NONE
8
SYNC_DATE=07/02/2008
NOTICE OF PROPRIETARY PROPERTY
A.0.0 OF
40
1
96
A
8
6
7
D
4
5
3
2
1
D
41 8 =PP5V_S3_IR
1
C4801 0.1UF 10% 16V X7R-CERM 402
14
2
VCC
www.laptop-schematics.com
U4800 CY7C63803-LQXC QFN 90 20 90 20
BI BI
USB_IR_P DIFFERENTIAL_PAIR=USB2_IR USB_IR_N DIFFERENTIAL_PAIR=USB2_IR
IR_VREF_FILTER
1
C4803 1UF
2
10% 10V X5R 402-1
12 13 15 16 17 18 19
P1.0/D+ P1.1/DP1.2/VREG P1.3/SSEL P1.4/SCLK P1.5/SMOSI P1.6/SMISO
8 9 10 20 21 NC 22 23 24
7 6 5 4 3 2 1
R4800 100 1
IR_RX_OUT_RC
2
IR_RX_OUT
IN
41
5% 1/16W MF-LF 402
CRITICAL OMIT 1
P/N 338S0633
C4804 0.001UF
2
10% 50V CERM 402
C THRML PAD
VSS 11
25
C
P0.0 P0.1 INT0/P0.2 INT1/P0.3 INT2/P0.4 TIO0/P0.5 TIO1/P0.6
B
B J4800
PLACE PLACE PLACE PLACE
R4805
FF18-6A-R11AD-B-3H
1
F-RT-SM
CRITICAL
10
PP3V42_G3H_LIDSWITCH_R
2
=PP3V42_G3H_LIDSWITCH
8
R4806 1
PP5V_S3_IR_R
10
1/16W
=PP5V_S3_IR
2 402
5% MF-LF
8 41
R4807 1
SMC_LID_R SYS_LED_ANODE_R
5
J4800 J4800 J4800 J4800
402 5% MF-LF
3 4
NEAR NEAR NEAR NEAR
2
1/16W
1
R4805 R4806 R4807 R4808
100
1/16W
R4808
402 5% MF-LF
6
2
1
4.7
1/16W
2
SMC_LID 42 SYS_LED_ANODE 43
43 50
402 5% MF-LF
IR_RX_OUT
41
518S0692 1
2
C4805
1
C4806
1
C4807
0.1UF
0.1UF
0.001UF
10% 16V X7R-CERM 402
10% 16V X7R-CERM 402
10% 50V CERM 402
2
2
1
C4808 0.001UF
2
10% 50V CERM 402
PLACE C4805 NEAR J4800 PLACE C4806 NEAR J4800 PLACE C4807 NEAR J4800 PLACE C4808 NEAR J4800
Front Flex Support SYNC_MASTER=CHANG_M98_MLB
A
SYNC_DATE=07/01/2008
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
41
1
96
A
8
6
7
2
3
4
5
1
NOTE: Unused pins have "SMC_Pxx" names. Unused pins designed as outputs can be left floating, those designated as inputs require pull-ups.
43 7 52 43 8
PP3V3_S5_AVREF_SMC =PP3V3_S5_SMC
D
D C4902 1 22UF
23 21
OUT
PM_RSMRST_L IMVP_VR_ON PM_PWRBTN_L
43
OUT
ESTARLDO_EN
21
OUT
62
OUT
43
43
NC
NC NC NC
SMC_P24
NC
SMC_P26
NC
C
90 83 44 19
BI
90 83 44 19
BI
90 83 44 19
BI
90 83 44 19
BI
90 83 44 19
IN
26
IN
90 26 44 19
IN BI
LPC_AD LPC_AD LPC_AD LPC_AD LPC_FRAME_L SMC_LRESET_L LPC_CLK33M_SMC LPC_SERIRQ SMC_P41 SMB_MGMT_DATA SMS_ONOFF_L
45
BI OUT
76
OUT
51
OUT
44 43 42 40
OUT
44 43 42 40 45
IN BI
NC
(DEBUG_SW_1) (DEBUG_SW_2)
(OC)
SMC_GFX_THROTTLE_L SMC_SYS_KBDLED SMC_TX_L SMC_RX_L SMB_0_S0_CLK
SMC_PA0 SMC_PA1 PM_SYSRST_L USB_DEBUGPRT_EN_L MEM_EVENT_L SMC_PA5 43 SYS_ONEWIRE PM_BATLOW_L
NC NC
(OC)
D4 A5 B4 A1 C2 B2 C1 C3
P40 P41 P42 P43 P44 P45 P46 P47
G2 F3 E4
P50 P51 P52
OUT
40
OUT
29 28 21
BI
60 43
BI
23 21
OUT
23 21
OUT
39 7
IN
IN
43
IN
76
IN
49
OUT
49
OUT
43
OUT
43
OUT
49
IN
49
IN
43
IN
43
IN
52
IN
52
IN
52
IN
43
IN
43
IN
43
IN
43
IN
43
IN
L13 K12 K11 J12 K13 J10 J11 H12
P70 P71 P72 P73 P74 P75 P76 P77
N10 M11 L10 N11 N12 M13 N13 L12
SMC_CPU_ISENSE SMC_CPU_VSENSE SMC_GPU_ISENSE SMC_GPU_VSENSE SMC_DCIN_ISENSE SMC_PBUS_VSENSE SMC_BATT_ISENSE SMC_NB_MISC_ISENSE
P80 P81 P82 P83 P84 P85 P86
A7 B6 C7 D5 A6 B5 C6
SMC_WAKE_SCI_L PM_CLKRUN_L LPC_PWRDWN_L SMC_TX_L SMC_RX_L (OC) SMB_MGMT_CLK
P90 P91 P92 P93 P94 P95 P96 P97
J4 G3 H2 G1 H4 G4 F4 F1
SMC_ONOFF_L SMC_BC_ACOK SMC_BS_ALRT_L PM_SLP_S3_L PM_SLP_S4_L PM_SLP_S5_L PM_CLK32K_SUSCLK (OC) SMB_0_S0_DATA
NC NC NC NC
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
B8 C9 B9 A10 C10 B10 C11 A11
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7
(OC) (OC) (OC) (OC) (OC) (OC)
SMC_RUNTIME_SCI_L SMC_ODD_DETECT SMC_PB3 (See below) 43 SMC_EXCARD_CP SMC_EXCARD_OC_L SMC_GFX_OVERTEMP_L
NC
SMC_FAN_0_CTL SMC_FAN_1_CTL SMC_FAN_2_CTL SMC_FAN_3_CTL SMC_FAN_0_TACH SMC_FAN_1_TACH SMC_FAN_2_TACH SMC_FAN_3_TACH
G11 G13 F12 H13 G10 G12 H11 J13
PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
SMS_X_AXIS SMS_Y_AXIS SMS_Z_AXIS SMC_ANALOG_ID SMC_NB_CORE_ISENSE SMC_NB_DDR_ISENSE ALS_LEFT ALS_RIGHT
M10 N9 K10 L8 M9 N8 K9 L7
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7
HS82117 LGA-HF (2 OF 3)
OMIT
PE0 PE1 PE2 PE3 PE4 PF0
K1 J3 K2 J1 K4 K5
PF1 PF2 PF3 PF4 PF5 PF6 PF7
N5 M6 L5 M5 N4 L4 M4
PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7
M8 N7 K8 K7 K6 N6 M7 L6
PH0 PH1 PH2 PH3 PH4 PH5
E2 F2 J2 A4 B3 C4
C4906 0.1UF
20% 2 10V CERM 402
PLACEMENT_NOTE=Place C4907 close to U4900 pin F1
SMC_PM_G2_EN
P60 P61 P62 P63 P64 P65 P66 P67
OUT
68
SMC_VCL
R4999 1
SMC_ADAPTER_EN
OUT
SMC_PROCHOT_3_3_L SMC_BIL_BUTTON_L
43
IN
43
IN
46
IN
46
IN
47
IN
46
IN
46
IN
46
IN
46
IN
43
OUT
5% 1/16W MF-LF 402
21 34 37 43
IN
4.7
2
PP3V3_S5_SMC_AVCC MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V
C4920 1
C4907 1 0.47UF
0.1UF
20% 10V CERM 2 402
VCC
AVCC
VCL AVREF
U4900
HS82117
PLACEMENT_NOTE=Place R4999 close to U4900 pins N14,N15 PLACEMENT_NOTE=Place C4920 close to U4900 pins N14,N15
10% 6.3V CERM-X5R 2 402
R49091 NC
10K
E5 NC
5% 1/16W MF-LF 402 2
LGA-HF (3 OF 3)
OMIT 44 43
IN 43 43
SMC_RESET_L
D3
RES*
SMC_XTAL SMC_EXTAL
A3 A2
XTAL EXTAL
MD1 MD2
D1 H1
NMI
E3
ETRST
H3
AVSS
L9
1
R4901 10K
5% 1/16W MF-LF 2 402
SMC_MD1
IN
44
SMC_NMI
IN
44
IN
44
SMC_KBC_MDE
21 23
NC
U4900
NC
43 32
OMIT
N3 N1 M3 M2 N2 L1 K3 L2
43
26
LGA-HF (1 OF 3)
P30 P31 P32 P33 P34 P35 P36 P37
43
B
A
P20 P21 P22 P23 P24 P25 P26 P27
A9 D9 C8 B7 A8 D8 D7 D6
43
52
D13 E11 D12 F11 E13 E12 F13 E10
HS82117
0.1UF
20% 2 10V CERM 402
1
www.laptop-schematics.com
IN
P10 P11 P12 P13 P14 P15 P16 P17
C4905
L11
IN
68
B12 A13 A12 B13 D11 C13 C12 D10
0.1UF
20% 2 10V CERM 402
1
E1
68 26
U4900
SMC_EXCARD_PWR_EN SMC_RSTGATE_L ALL_SYS_PWRGD RSMRST_PWRGD
C4904
B1 M1 H10
OUT
0.1UF
20% 2 10V CERM 402
1
M12
OUT
43
C4903
OUT
19 44
IN
19 44
OUT
40 42 43 44
IN
40 42 43 44
BI
SMC_CASE_OPEN SMC_TCK SMC_TDI SMC_TDO SMC_TMS
R4902 10K
5% 1/16W MF-LF 2 402
45
IN
43 50
IN
43 60
IN
43 60
XW4900 SM 2
IN
7 21 34 37 44 68 81 83
IN
21 40 43 68
IN
43
IN
26 90
BI
SMC_TRST_L NO STUFF 1
VSS D2 L3 F10 B11 C5
32
20% 6.3V 2 CERM 805
1
NOTE: P94 and P95 are shorted, P95 could be spare.
1
R4998 10K
5% 1/16W MF-LF 2 402
C
1
R4903 0
5% 1/16W MF-LF 2 402
1
GND_SMC_AVSS
43 46 47
45
IN
43
IN
43 44
IN
43 44
OUT
43 44
IN
43 44
B
NC
SMC_SYS_LED SMC_LID NC NC
OUT IN
SMC_MCP_SAFE_MODE
43 41 43 50
OUT
9
IN
43
NC NC NC
(OC) (OC) (OC) (OC) (OC) (OC)
=SMC_SMS_INT SMB_BSA_DATA SMB_BSA_CLK SMB_A_S3_DATA SMB_A_S3_CLK SMB_B_S0_DATA SMB_B_S0_CLK SMC_PROCHOT SMC_THRMTRIP SMC_PH2 ALS_GAIN
BI
45
BI
45
BI
45
BI
45
BI
45
BI
NOTE: SMS Interrupt can be active high or low, rename net accordingly. If SMS interrupt is not used, pull up to SMC rail.
45
OUT
43
OUT
43
OUT
43
43
NC NC
SMC SYNC_MASTER=T18_MLB
SYNC_DATE=06/18/2008
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
SMC_PB3:
II NOT TO REPRODUCE OR COPY IT
SMC_IG_THROTTLE_L for MG systems. Otherwise, TP/NC okay (was ISENSE_CAL_EN)
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
42
1
96
A
8
6
7
42
SMC_FAN_2_CTL
42
SMC_FAN_2_TACH
42
SMC_FAN_3_CTL
42
SMC_FAN_3_TACH
2
3
4
5 NC_SMC_FAN_2_CTL MAKE_BASE=TRUE
SMC Reset "Button" / Brownout Detect
1
SMC FSB to 3.3V Level Shifting
NC_SMC_FAN_2_TACH MAKE_BASE=TRUE
=PP3V3_S5_SMC
MAKE_BASE=TRUE
=PP3V3_S0_SMC
43 8
NC_SMC_FAN_3_TACH MAKE_BASE=TRUE
C5000
1
1
0.1uF 20% 10V CERM 402
NCP303LSN SOT23-5-HF 5
SMC_MANUAL_RST_L
D
OMIT 1
GND
R5001
C5001
0 SILK_PART=SMC_RST 2
4
NC
CD NC
1
3
2
OUT IN
5% 1/16W MF-LF 402
1
42
SMC_RESET_L OUT
ESTARLDO_EN
2 2
2
42
D 3
=CHGR_ACOK
Q5032
TO CPU
46
SOT563
42
87 62 14 10
SMC_CPU_HI_ISENSE
ALS_RIGHT
46
BI
3.3K 1
42 52 43 42 8
5
=PP3V3_S5_SMC 5
50 43 42
1
SMC_TPAD_RST_L
S 4
47
MAKE_BASE=TRUE
U5001
6
SMC_MCP_DDR_ISENSE
42
SMC_NB_DDR_ISENSE
42
SMC_NB_MISC_ISENSE
42
SMC_ANALOG_ID
D
SMC_CPU_FSB_ISENSE
SOT563
SMC_GPU_1V8_ISENSE
1
47
S
G 2
MAKE_BASE=TRUE
SMC_PROCHOT
3
42
SMC_P24
42
SMC_P26
42
SMC_P41
TP_SMC_P24
87 14 10
MAKE_BASE=TRUE
SMC_BMON_MUX_SEL
OUT
42
PM_THRMTRIP_L
3
D
TP_SMC_P41
Q5059 SSM6N15FEAPE
MAKE_BASE=TRUE
ALS_GAIN
IN
46
MAKE_BASE=TRUE
42
1
Q5059
47
MAKE_BASE=TRUE
02
BC847BV-X-F SOT563-HF
SSM6N15FEAPE
47
MAKE_BASE=TRUE
SN74LVC1G02 SOT553-5 4 SMC_TPAD_RST
2
SMC_ONOFF_L
G
SMC_NB_CORE_ISENSE
4
Q5060
2
CPU_PROCHOT_L_R
5% 1/16W MF-LF 402
MAKE_BASE=TRUE
SMC_MCP_CORE_ISENSE
2
D
BC847BV-X-F SOT563-HF
6
R5062 CPU_PROCHOT_L
42
Q5060
61
MAKE_BASE=TRUE
SSM6N15FEAPE
OUT
3 5
CPU_PROCHOT_BUF
SMC_MCP_VSENSE
ALS_LEFT
TO SMC
SMC_PROCHOT_3_3_L
5% 1/16W MF-LF 402
MAKE_BASE=TRUE
10% 16V CERM 402
50
5% 1/16W MF-LF 402
3.3K
42 44
SMC_BC_ACOK
2
R5061
NC_ESTARLDO_EN MAKE_BASE=TRUE
60 43 42
R5060 470
=PP1V05_S0_SMC_LS 1
CRITICAL
0.01UF
5% 1/10W MF-LF 603
8
1K
U5000
2
1
R5000
www.laptop-schematics.com
52 43 42 8
NC_SMC_FAN_3_CTL
SOT563
NC_ALS_GAIN MAKE_BASE=TRUE
42
SMC_IG_THROTTLE_L
SMC_PB3
4
21
S
MAKE_BASE=TRUE 42
C
SMC_RSTGATE_L
G 5 SMC_THRMTRIP
TP_SMC_RSTGATE_L
IN
42
C
MAKE_BASE=TRUE
R5095 42
SMC_EXCARD_OC_L
OUT
0
1
52 43 42 8
EXCARD_OC_L
2
IN
20 32
5% 1/16W MF-LF 402
42 42
R5091 R5092
SMC_PA0 SMC_PA1
100K 100K
1
2
1
2
SMC AVREF Supply 52
CRITICAL
SMS_INT_L
=SMC_SMS_INT
MAKE_BASE=TRUE 50 43 42 50 42 41
REF3333
=PPVIN_S5_SMCVREF
PP3V3_S5_AVREF_SMC
SOT23-3
1
IN
OUT
7 42
42
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
2
SMC Crystal Circuit
44 42 40 44 42 40
GND 1 3
2
C5020
C5025
0.47UF
10uF
10% 6.3V CERM-X5R 402
20% 6.3V X5R 603
42
353S1381
353S1278
BOM OPTION
REF DES
COMMENTS:
ALL
Intersil ISL60002-33
Debug Power "Button"
2
60 42 60 42
R5010 1
2
TABLE_ALT_HEAD
ALTERNATE FOR PART NUMBER
1
SMC_XTAL
1
0
2
SMC_XTAL_R
5% 50V CERM 402
44 42 44 42 44 42
5% 1/16W MF-LF 402 42 46 47
SMC_ONOFF_L
Y5010
1
1
10K 100K 10K 10K 100K
C5011
5X3.2-SM 42
SILK_PART=PWR_BTN
15pF
2
B
1
2
1
2
1
2
1
2
1
1
SMC_EXTAL
MF-LF
402
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
2
42 43 50
44 42 43 42
R5015
60 43 42
R5075 R5076 R5077 R5078 R5079 R5080 R5081 R5087
SYS_ONEWIRE SMC_BS_ALRT_L SMC_TMS SMC_TDO SMC_TDI SMC_TCK SMC_BIL_BUTTON_L SMC_BC_ACOK
2.0K 100K 10K 10K 10K 10K 10K 470K
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
0
20.00MHZ
TABLE_ALT_ITEM
OUT
OMIT
CRITICAL
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V
1/16W
5%
ONEWIRE_PU
15pF
10% 16V CERM 402
GND_SMC_AVSS PART NUMBER
R5070 R5071 R5072 R5073 R5074
SMC_ONOFF_L SMC_LID SMC_PH2 SMC_TX_L SMC_RX_L
C5010
0.01UF 2
1
C5026
5%
42
VR5020 8
=PP3V3_S5_SMC
2
5% 1/10W MF-LF 2 603
Place R5015,R5001 on bottom side
B
5% 50V CERM 402
System (Sleep) LED Circuit 8 7
PP3V42_G3H 42 37 34 21
8
=PP5V_S3_SYSLED
42
1
1
R5031 523
1% 1/16W MF-LF 402 2
1
R5051
C5050
R5030
5% 1/16W MF-LF 2 402
10% 2 16V X5R 402
20
1% 1/16W MF-LF 2 402
U5050
5
SMC_BIL_BUTTON_DB_L
74LVC1G17DRL
SYS_LED_ILIM 43 42
SOT-553 4
SMC_BIL_BUTTON_L
42 32
10K
0.1UF
1
R5085 R5086
SMC_ADAPTER_EN SMC_CASE_OPEN
42 68 42 40 21
R5088
SMC_EXCARD_CP
R5090
PM_SLP_S5_L PM_SLP_S4_L
10K 10K 10K
1
2
1
2
1
100K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
2
1
2
60 43 8
=PP3V3_S0_SMC
2
2
NC
SOD
SYS_LED_L_VDIV
42
3
OUT
10% 25V 2 X7R 402
41
1/16W MF-LF 402
SMC Support SYNC_MASTER=AMASON_M98_MLB
Q5032
SYNC_DATE=06/18/2008
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
D 6
SSM6N15FEAPE SOT563 IN
2
C5051
SYS_LED_L
42
1
0.01UF
SYS_LED_ANODE
1% 1/16W MF-LF 402 2
10K
5%
NC
3
1.47K
R5089
SMC_PA5
1 1
R50321
A
2SA2154MFV-YAE
Q5030
1
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
SMC_SYS_LED
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
2 G
S 1 SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
43
1
96
A
8
6
7
2
3
4
5
1
LPC+SPI Connector CRITICAL LPCPLUS
J5100
55909-0374 8
90 83 42 19
BI
90 83 42 19
BI
44
IN
44
OUT
90 83 42 19
OUT
43 42
OUT
OUT
42 43 42 40
=PP3V3_S5_LPCPLUS
IN
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
33
34
D LPC_CLK33M_LPCPLUS LPC_AD LPC_AD SPIROM_USE_MLB SPI_ALT_CLK SPI_ALT_CS_L LPC_SERIRQ LPC_PWRDWN_L SMC_TDI SMC_TCK SMC_RESET_L SMC_NMI SMC_RX_L LPCPLUS_GPIO
26 90
IN BI
19 42 83 90
BI
19 42 83 90
44
OUT IN
44
IN
44 19 42
BI IN
19 42
OUT
42 43
OUT
42 43
OUT
42 43
OUT
42
OUT
40 42 43
OUT
18
C5114
MCP79 Internal SPI MUX Support
516S0573
2 10V CERM
9
LPCPLUS
5% 1/16W MF-LF 402 2 90 44 21
C
IN
20%
10K
SPI_CLK_R
OUT
0.1UF
R51901
IN
IN
1
LPCPLUS
=PP3V3_S5_ROM 1
90 44 21
IN
42 19
42
MUX SEL CONTROLLED BY FRANKCARD SWITCH ONCE CS1 IS SUPPORTED IN MCP
44 8
SPI_ALT_MOSI SPI_ALT_MISO LPC_FRAME_L PM_CLKRUN_L SMC_TMS DEBUG_RESET_L SMC_TDO SMC_TRST_L SMC_MD1 SMC_TX_L
IN
Alternate SPI ROM Support 53 44 8
LPC_AD LPC_AD
402
NOT SUPPORTED IN REV A01 OR B01 MCP79 SILICON
VCC 1 Y+ 2 Y-
SPI_MOSI_R
U5110
SPI_ALT_CLK SPI_ALT_MOSI
M+ 5 M- 4
OUT
44
8
OUT
44
44 8
OUT
44 53
OUT
44 53
=PP3V3_S0_LPCPLUS =PP3V3_S5_LPCPLUS
PI3USB102ZLE TQFN
R51911 10K
CRITICAL SPIROM_USE_MLB
10 SEL
MCP SPI Override Options
R5140
5% 1/16W MF-LF 402 2
MCP79 REV A01 REQUIRES EXTERNAL MUX, REV B01 STILL DOES NOT SUPPORT INTERNAL MUX
OE* 8
SPIROM_USE_MLB
3
44
LPCPLUS 1
1
C5124
470 5% 1/16W MF-LF 402 2
SSM3J16FV
1 Y+ 2 Y-
U5120
M+ 5 M- 4
IN
1/16W
D+ 7 D- 6 SPI_MLB_CS_L_MUX
5% MF-LF
OE* 8
OUT
402
1/16W
5% MF-LF
402
IN
R5144
R5147
OUT
0
0
1
53
=PP3V3_S5_ROM
8 44 53
B
SPI Frequency Clamp ENSURES MCP79 SPI_DO OR SPI_CLK INPUT IS LOW WHEN STRAP IS LATCHED.NOT NEEDED FOR B01 OR LATER.
2
5% 1/16W MF-LF 402
PLACEMENT_NOTE=PLACE NEXT TO U1400
NO STUFF Keep very short
R5161
MCP_FORCE_SPI_DO_L 23 8
SPI MUX BYPASS
=PP3V3_S5_MCP_A01 MCP_A01&MCP_A01Q
R51631
MCP_A01&MCP_A01Q
Q5160
53 44
OUT
SPI_CLK_MUX
0 5% 1/16W MF-LF 402
53 44
OUT
SPI_CLK_R
SPI_MOSI_MUX
1
IN
SPI_MISO_MUX
1
0
2
0
2
Q5160 IN
21 44 90
OUT
21 44 90
5% 1/16W MF-LF 402
SPI_MISO
OUT
53 90
OUT
53 90
1
S 1
0
2
5% 1/16W MF-LF 402
D 3
SLP_S3# nVidia recommendation, SSM6N15FEAPE SOT563 not compatible with button-mashing. MCP_A01&MCP_A01Q
R5160
5% 1/16W MF-LF 402
A
G
MCP_A01&MCP_A01Q SPI_MOSI_R
SPI_CLK
R5162 2
MCP_SPI_FORCE
21 44 90
LPCPLUS_NOT R5157
LPCPLUS_NOT R5158 53 44
IN
SPI_MOSI
2
MCP_A01&MCP_A01Q
SOT563
5% 1/16W MF-LF 402 2
2
0
1
5% 1/16W MF-LF 402
D 6
SSM6N15FEAPE
100K LPCPLUS_NOT R5156 1
9 21
PLACEMENT_NOTE=PLACE NEXT TO U5120
5% 1/16W MF-LF 402 2
R5146
BI
To Frank Card
2
20K
MCP_CS1_YES&LPCPLUS_NOT
=SPI_CS1_R_L_USE_MLB
MCP_CS1_YES
5% 1/16W MF-LF 402
44 53
SPI_MLB_CS_L MCP_CS1_NO 1
3
GND
44
1
SPI_MISO_MUX
MCP_CS1_NO 0 2 R5126 1
CRITICAL 10 SEL
19
OUT
MAKE_BASE=TRUE
44
MCP_CS1_NO Pull-up on debug card 0 2 R5127 SPI_ALT_CS_L
1 SPI_ALT_CS_L_MUX
PI3USB102ZLE TQFN
LPC_FRAME_R_L
2
SPI_CS1_R_L_USE_MLB
SPI_ALT_MISO
VCC
SPI_MISO SPI_CS0_R_L
0
5% PLACEMENT_NOTE=Place near J5100 1/16W MF-LF 402
20% 2 10V CERM 402
9
LPCPLUS
B
MCP_CS1_YES 1 R5141
Q5140
R5142
From Frank Card
0.1UF
IN
LPC_FRAME_PU
MCP_CS1_NO 8 44
OUT
3
SOD-VESM-HF
=PP3V3_S5_LPCPLUS
90 21
2
1
SEL HIGH OUTPUTS TO D (ON BOARD ROM) SEL LOW OUTPUTS TO M (FRANKCARD ROM)
90 44 21
C
MCP_CS1_YES
G
GND
1
100K
D
44
SPI_CLK_MUX SPI_MOSI_MUX
D+ 7 D- 6
S
5% 1/16W MF-LF 402 2
www.laptop-schematics.com
D
M-ST-SM 31 32
=PP3V3_S5_LPCPLUS =PP5V_S0_LPCPLUS
44 8
83 81 68 42 37 34 21 7
IN
PM_SLP_S3_L
1
0
2
5
G
S 4
LPC+SPI Debug Connector
MCP_SPI_FORCE_L
5% 1/16W MF-LF 402
SYNC_MASTER=CHANG_M98_MLB
SYNC_DATE=07/01/2008
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
44
1
96
A
8
6
7
MCP79 SMBus "0" Connections
2
3
4
5
SMC "0" SMBus Connections
1
SMC "A" SMBus Connections NOTE: SMC RMT bus remains powered and may be active in S3 state
=PP3V3_S0_SMBUS_MCP_0
R5200
MCP79 U2300 (MASTER)
D
90 21 13 7
8
1
1
R5201
4.7K
4.7K
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
2
2
SMBUS_MCP_0_CLK
SO-DIMM "A"
SMC
J3100 (Write: 0xA0 Read: 0xA1)
U4900 (MASTER)
=PP3V3_GPU_SMBUS_SMC_0_S0
R5250
=I2C_SODIMMA_SCL
28
42
SMB_0_S0_CLK
93
=I2C_SODIMMA_SDA
28
42
SMB_0_S0_DATA
93
MAKE_BASE=TRUE 90 21 13 7
8
1
1
R5251
4.7K
4.7K
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
2
2
SMBUS_SMC_0_S0_SCL
R52701
GPU Temp (Ext)
SMC
EMC1043-1: U5550 (Write: 0x98 Read: 0x99)
U4900 (MASTER)
=SMBUS_GPUTHMSNS_SCL
48
42
SMB_A_S3_CLK
=SMBUS_GPUTHMSNS_SDA
48
42
SMB_A_S3_DATA
R5271 2.2K
5% 1/16W MF-LF 402 2
5% 1/16W MF-LF 2 402
TRACKPAD J5800 (Write: 0x90 Read: 0x91) =I2C_TPAD_SCL
51
=I2C_TPAD_SDA
51
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_A_S3_SDA
MAKE_BASE=TRUE
MAKE_BASE=TRUE
1
2.2K
SMBUS_SMC_A_S3_SCL
MAKE_BASE=TRUE
SMBUS_MCP_0_DATA
=PP3V3_S3_SMBUS_SMC_A_S3
SO-DIMM "B"
GPU Temp (Int)
ALS
J3200 (Write: 0xA2 Read: 0xA3)
G96: U8000 (Write: 0x9E Read: 0x9F)
J3401 (Write: 0x72 Read: 0x73)
=I2C_SODIMMB_SCL
29
=GPU_I2CS_SCL
77
I2C_ALS_SCL
31
=I2C_SODIMMB_SDA
29
=GPU_I2CS_SDA
77
I2C_ALS_SDA
31
SMC "Battery A" SMBus Connections
ExpressCard Slot
MCP Temp
J3500 8
=SMBUS_EXCARD_SCL
32
=SMBUS_EXCARD_SDA
32
EMC1043-1: U5500 (Write: 0x98 Read: 0x99)
=PP3V42_G3H_SMBUS_SMC_BSA
R52801
SMC U4900 (MASTER) 42
SMB_BSA_CLK
93
42
SMB_BSA_DATA
93
1
R5281
1.6K
1.6K
5% 1/16W MF-LF 402 2
5% 1/16W MF-LF 2 402
Battery
=SMBUS_MCPTHMSNS_SCL
48
=SMBUS_MCPTHMSNS_SDA
48
J6955 (See Table)
SMBUS_SMC_BSA_SCL
=SMBUS_BATT_SCL
60
=SMBUS_BATT_SDA
60
MAKE_BASE=TRUE
C
SMBUS_SMC_BSA_SDA
8
Battery Charger
Battery
8
MCP79 U2300 (MASTER?) 90 21
R5260 1
SMC =SMBUS_CHGR_SCL
61
=SMBUS_CHGR_SDA
61
=PP3V3_S0_SMBUS_MCP_1
1
3.3K
U4900 (MASTER) 42
SMB_B_S0_CLK
93
42
SMB_B_S0_DATA
93
R5261
CPU Temp
3.3K
5% 1/16W MF-LF 402 2
EMC1043-1: U5570 (Write: 0x98 Read: 0x99)
5% 1/16W MF-LF 2 402
SMBUS_SMC_B_S0_SCL
=I2C_CPUTHMSNS_SCL
48
=I2C_CPUTHMSNS_SDA
48
MAKE_BASE=TRUE
1
R5230
1
R5231
2.0K
2.0K
5% 1/16W MF-LF 402 2
5% 1/16W MF-LF 2 402
SMBUS_MCP_1_CLK
HDCP ROM
SMBUS_MCP_1_DATA
The bus formerly known as "Battery B"
U2690 or U2695 (Write: 0xA0-0xAE, Read: 0xA1-0xAF) =I2C_HDCPROM_SCL
25
=I2C_HDCPROM_SDA
25
8
Battery Charger Temp
=PP3V3_S3_SMBUS_SMC_MGMT
TMP102: U5540 (Write: 0x92 Read: 0x93)
R5290
SMC
Mikey
1
4.7K
U4900 (MASTER)
MAKE_BASE=TRUE
5% 1/16W MF-LF 402 2
42
SMB_MGMT_CLK
93
42
SMB_MGMT_DATA
93
1
R5291 4.7K
5% 1/16W MF-LF 2 402
SMBUS_SMC_MGMT_SCL
Vref DACs
=SMBUS_TMPSNSR_SCL
48
U2900 (Write: 0x98 Read: 0x99)
=SMBUS_TMPSNSR_SDA
48
=I2C_VREFDACS_SCL
27
=I2C_VREFDACS_SDA
27
MAKE_BASE=TRUE
U6860 (WRITE: 0X72 READ: 0X73)
B
SMBUS_SMC_B_S0_SDA
MAKE_BASE=TRUE
SMC "Management" SMBus Connections
MAKE_BASE=TRUE 90 21
=PP3V3_S0_SMBUS_SMC_B_S0
ISL6258A - U7000 (Write: 0x12 Read: 0x13)
Battery Manager - (Write: 0x16 Read: 0x17) Battery LED Driver - (Write: 0x36 Read: 0x37) Battery Temp - (Write: 0x90 Read: 0x91)
C
SMC "B" SMBus Connections
MAKE_BASE=TRUE
MCP79 SMBus "1" Connections
=I2C_MIKEY_SCL
59
=I2C_MIKEY_SDA
59
D
MAKE_BASE=TRUE
www.laptop-schematics.com
8
SMBUS_SMC_MGMT_SDA
MAKE_BASE=TRUE
B Margin Control U2901 (Write: 0x30 Read: 0x31) =I2C_PCA9557D_SCL
27
=I2C_PCA9557D_SDA
27
SMS U5930 (Write: 0x70 Read: 0x71) =I2C_SMS_SCL
52
=I2C_SMS_SDA
52
M98 SMBus Connections
A
SYNC_MASTER=DDR
SYNC_DATE=07/22/2008
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
45
1
96
A
8
6
7 CPU Voltage Sense / Filter 2
PBUS Voltage Sense & Filter
R5309
SM 1
CPUVSENSE_IN
1
4.53K
Q5315 SMC_CPU_VSENSE
2
OUT
FDG6332CG
42
SC70-6
1% 1/16W MF-LF 402
Place short near U1000 center
1
C5309
8 7
P-CHN
PPBUS_G3H
0.22UF
R5315
GND_SMC_AVSS
5% 1/16W MF-LF 402
Place RC close to SMC
GPU Voltage Sense / Filter
3
PPBUS_G3H_VSENSE MIN_LINE_WIDTH=0.20 mm MIN_NECK_WIDTH=0.20 mm VOLTAGE=18.5V
1
G
100K
42 43 46 47
D
S
4
20% 6.3V X5R 402
2
D
R5385 1 27.4K
5
1% 1/16W MF-LF 402
2
XW5359
=PPVCORE_GPU_REG
2
SMC_PBUS_VSENSE
OUT
42
R5359
SM 1
D
Rthevanin = 4573 ohms
2
PBUSVSENS_EN_DIV 78 8
1
4.53K
GPUVSENSE_IN
1
SMC_GPU_VSENSE
2 1% 1/16W MF-LF 402
Place short near U8000 center
1
OUT
R5316 1
42
5.49K
5% 1/16W MF-LF 402
1% 1/16W MF-LF 402
C5359 0.22UF
2
20% 6.3V X5R 402
R5386 1
100K
2
1
C5385 0.22UF
2 2
PBUSVSENS_EN_L
20% 6.3V X5R 402
GND_SMC_AVSS
42 43 46 47
Place RC close to SMC
GND_SMC_AVSS
42 43 46 47
www.laptop-schematics.com
12 11 8
XW5309
=PPVCORE_S0_CPU
2
3
4
5
6
Place RC close to SMC
D
24 22 8
XW5399 SM
=PPVCORE_S0_MCP
Q5315 FDG6332CG SC70-6
S 1
4.53K2
SMC_MCP_VSENSE
1
1% 1/16W MF-LF 402
G
Enables PBUS VSense divider when high.
R5399
1 2 MCPVSENSE_IN PLACEMENT_NOTE=Place near U1400 center
2
=PBUSVSENS_EN
68
N-CHN
MCP Voltage Sense / Filter
1
OUT
43
C5399 0.22UF
20% 6.3V 2 X5R 402
GND_SMC_AVSS Place RC close to SMC
42 43 46 47
C
C BMON Current Sense - Entire circuit must be near SMC (U4900) 8
=PP3V42_G3H_BMON_ISNS BMON_ENG
BMON_ENG 1 C5318
3
20%
REGULATOR SIDE:
1
BMON_INA_OUT
0.1uF
2 10V CERM
OUT
95 61
IN
5
CHGR_CSO_R_P
2
4
CHGR_CSO_R_N
INA213
IN-
SMC_BMON_MUX_SEL
REF
GND
VCC
61
DCIN Current Sense Filter R5391
3
CHGR_BMON
IN
4 B0
2
0
R5371 100K
5% 1/16W MF-LF 2402
1
5% 1/16W MF-LF 402
Monitors battery discharge current from battery to PBUS
1% 1/16W MF-LF 402
1
R5330
GND
Place RC close to SMC
14.53K2
BMON_AMUX_OUT BMON_ENG
A
VER 1
1
2
B
402
43
5
BMON_PROD LOAD SIDE:
IN
0
SC70 OUT 6
IN+
20%
10V 2 CERM
6
1
U5303 95 61
0.1uF
NC7SB3157P6XG SC70 SEL B1
BMON_ENG
V+
402
1 C5369
U5313
BMON_ENG
SMC_BATT_ISENSEOUT
42
R5380
1 C5390
0.22UF
2
61
IN
4.53K
CHGR_AMON
1
20% 6.3V X5R 402
GND_SMC_AVSS 42
SMC_DCIN_ISENSE
2 1% 1/16W MF-LF 402
1
OUT
42
C5380 0.22UF
43 46 47
2
20% 6.3V X5R 402
GND_SMC_AVSS
B 42 43 46 47
INA213 has gain of 50V/V
CPU VCore High Side Current Sensor 8
=PP3V42_G3H_CPUCOREISNS 1
C5388
CPU VCore Load Side Current Sense / Filter
0.1UF 3
2 8
OUT
=PPVIN_S5_CPU_IMVP_ISNS
20% 10V CERM 402
V+ 62
U5388 R5388
1 3
95
ISNS_CPU_N
0.001 1% 0.5W MF 1206
A
95
ISNS_CPU_P
5 IN-
SC70
4 IN+
OUT
6
CPUVCORE_HISIDE_IOUT
IN
REF 1
SMC_CPU_HI_ISENSE
2 1% 1/16W MF-LF 402
2 4
1
OUT
43
IMVP6_IMON
1
SMC_CPU_ISENSE
2
1
R5332
C5335
OUT
42
C5330
Current & Voltage Sensing
0.22UF 2
20% 6.3V X5R 402
GND_SMC_AVSS
20% 6.3V X5R 402
GND_SMC_AVSS
1
17.4K 1% 1/16W MF-LF 402 2
0.22UF 2
2
=PPVIN_S5_CPU_IMVP_ISNS_R
4.53K 1
IN
6.19K 1% 1/16W MF-LF 402
R5335
INA210
GND 8
Place RC close to SMC
R5331
SYNC_MASTER=SENSOR
SYNC_DATE=08/14/2008
NOTICE OF PROPRIETARY PROPERTY
42 43 46 47
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
42 43 46 47
Place RC close to SMC
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
Consider INA211 (GAIN 500 version) since I=4.93 Amps across R5388
SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
46
1
96
A
8
6
7 MCP VCore Current Sense
8
2
3
4
5
1
GPU VCore Current Sense
=PP3V3_S0_MCPCOREISNS 1
C5420 0.1UF 20% 10V CERM 402
NC
MCP VCore Current Sense Filter
V+
Place RC close to SMC
U5420
D
95 65
95 65
MCPCOREISNS_N MCPCOREISNS_P
78
R5470
INA213
5 IN-
SC70
6
OUT
4 IN+
4.53K
MCPCORE_IOUT
1
SMC_MCP_CORE_ISENSE
2 1% 1/16W MF-LF 402
REF 1
1
OUT
GFXIMVP6_IMON1
IN
2
2
2
GPUISENS_P
95
1% 1/16W MF-LF 402
43
1
20% 6.3V X5R 402
GND_SMC_AVSS
10K
2
V+ 4
3 95
DDRISNS_P
1
C
95 8
OUT
=PPMCPDDR_ISNS
3.65K
2
95
DDRISNS_R_P
C5440 20% 10V CERM 402
1
3.65K
2
V+
2
R5443 DDRISNS_N
MCP MEM VDD Current Sense Filter
MCPDDR_IOUT
VTHRM
95
R5440
1
DDRISNS_R_N
1
4.53K 1% 1/16W MF-LF 402
4
SMC_MCP_DDR_ISENSE
2
1
2
C5442 1 470PF
10% 50V CERM 2 402
R5442
R5441
1M
1M
1
1% 1/16W MF-LF 2 402
1% 1/16W MF-LF 402
43
C5490
C
20% 6.3V X5R 402
GND_SMC_AVSS
SIGNAL_MODEL=EMPTY 1
OUT
0.22UF
9
1% 1/16W MF-LF 402
SIGNAL_MODEL=EMPTY
42 43 46 47
GPU 1.8V Current Sense
SIGNAL_MODEL=EMPTY Gain: 274x
2
C5441 470PF 1
2
GPU VCore Current Sense and GPU 1.8V Current Sense share dual package opamp U5410
Place RC close to SMC
OPA2333DRBG4 DFN
3
8
=PP3V3_S0_GPU1V8ISNS
2 1
10% 50V CERM 402
SIGNAL_MODEL=EMPTY
IN
=PP1V8_S0GPU_ISNS_R
OPA2333s for proto are placeholders for OPA2330
R5413
1 3
95
P1V8GPU_P
1
0.002
=PP1V8_S0GPU_ISNS
95
P1V8GPU_N
1
3.65K
2
5
V+
470PF
10% 50V CERM 2 402
1V05CPU_P
95 66
1
3.65K
8
2
95
1V05CPUISNS_R_P
P1V8GPUISNS_R_N
R5436 95 66
1V05CPU_N
1
3.65K
2
95
1V05CPUISNS_R_N
2
1
R5412 1M
1% 1/16W MF-LF 2 402
1
1M 1% 1/16W MF-LF 402
A
C5472 470PF
7
1
1
10% 50V CERM 2 402
R5437 1M
1% 1/16W MF-LF 2 402
4.53K 1
SMC_CPU_FSB_ISENSE
2 1% 1/16W MF-LF 402
NC
1
C5411 470PF
1M 1% 1/16W MF-LF 402
2
SIGNAL_MODEL=EMPTY
OUT
43
C5435 0.22UF
2
Current Sensing
20% 6.3V X5R 402
GND_SMC_AVSS
SYNC_MASTER=SENSOR
NOTICE OF PROPRIETARY PROPERTY
2
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
SIGNAL_MODEL=EMPTY
C5432
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
470PF 1
SYNC_DATE=08/14/2008
42 43 46 47
Place RC close to SMC
R5432 1
B
2
R5495 CPU1V05_S0_IOUT
SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
II NOT TO REPRODUCE OR COPY IT
2
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
10% 50V CERM 402
SIZE
DRAWING NUMBER
D
Gain: 274x
APPLE INC.
7
6
5
4
3
2
REV.
051-7546
SCALE
SHT NONE
8
42 43 46 47
SIGNAL_MODEL=EMPTY
1.05V CPU Current Sense Filter
4
NC
20% 6.3V X5R 402
GND_SMC_AVSS
R5411
43
0.22UF
9
SIGNAL_MODEL=EMPTY
OUT
C5465
OPA2333DRBG4
9
1% 1/16W MF-LF 402
1
Gain: 274x
VTHRM
SMC_GPU_1V8_ISENSE
2
U5440
V+
6
4.53K 1% 1/16W MF-LF 402
10% 50V CERM 402
DFN
5
1% 1/16W MF-LF 402
1
4
1
CPU FSB 1.05V Current Sense
P1V8_S0GPU_IOUT
1% 1/16W MF-LF 402
C5412 1
NC
7
VTHRM
95
Place RC close to SMC
R5465
DFN
6
SIGNAL_MODEL=EMPTY
MCP MEM VDD Current Sense and CPU FSB 1.05V Current Sense share dual package opamp U5440
P1V8GPUISNS_R_P
R5414 95
OUT
2
GPU 1.8V Current Sense Filter
OPA2333DRBG4
8
1% 1/16W MF-LF 402
1% 1/4W MF 1206 2 4 8
3.65K
20% 10V CERM 402
U5410
R5415
R5431
C5410 0.1UF
2
8
B
42 43 46 47
10% 50V CERM 402
U5440
1% 1/16W MF-LF 402
1% 1/4W MF 1206 2 4
20% 6.3V X5R 402
1% 1/16W MF-LF 402
0.1UF
0.002
0.22UF 2
470PF
2
R5445 1
D
42
C5498
1
8
OUT
C5475
2
1
R5444
1
GND_SMC_AVSS 10K
=PP3V3_S0_MCPDDRISNS
=PPMCPDDR_ISNS_R
SMC_GPU_ISENSE
2
1% 1/16W MF-LF 402
R5498
42 43 46 47
MCP MEM VDD Current Sense
IN
1
NC
NC
New Gain: 2x can sense current up to 16.6 Amps
8
GPUVCORE_IOUT
4.53K
9
1
8
1
V-
GPUISENS_N
1% 1/16W MF-LF 402
R5475
DFN
3
THRM
95
Place RC close to SMC
OPA2333DRBG4
8
2
R5491
C5470 0.22UF
GND
4.53K
GPU VCore Current Sense Filter
U5410
R5493
www.laptop-schematics.com
3
2
A.0.0 OF
47
1
96
A
6
7
2
3
4
5
CPU Proximity/CPU Die/Right Fin Stack
Battery Charger Proximity
R5570 8
=PP3V3_S0_CPUTHMSNS
1
47
8
95 10
BI
MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V
1 1 VDD
C5580
2 DP1
10% 50V CERM 2 402
4 DP2
BI
DFN
3 DN1
CPU_THERMD_N
GND 6
95
Q5501
Detect Right Fin Stack Temperature
5 V+
10K
5% 1/16W MF-LF 402 2
5% 1/16W MF-LF 2 402
CPUTHMSNS_THM_L
ALERT* 8
CPUTHMSNS_ALERT_L
U5540
D
HPA00330AI SOT563
SMDATA 9
=I2C_CPUTHMSNS_SDA
BI
45
SMCLK 10
=I2C_CPUTHMSNS_SCL
BI
45
45 =SMBUS_TMPSNSR_SDA
6
45 =SMBUS_TMPSNSR_SCL
1
SDA
ADD0
SCL
ALERT
4 3
GND 1
2
C5540 0.1uF
THRM_PAD 11
Placement note:
2
Place U5540 near battery charger circuit
Placement note:
CPUTHMSNS_D2_P
20% 10V CERM 402
Place U5570 under CPU and close to left fin stack
SIGNAL_MODEL=EMPTY
3
R5572
THERM* 7
CRITICAL
5 DN2
TEMP SENSOR HAS ADDRESS WRITE:0X92, READ: 0X93
1
10K
2 CERM 402
EMC1403-1 1
0.0022UF
95 10
C5570 0.1uF R55711 20% 10V
U5570
CPU_THERMD_P SIGNAL_MODEL=EMPTY
Detect CPU Die Temperature
=PP3V3_S0_BATTCHARGERTMPSNSR
PP3V3_S0_CPUTHMSNS_R
2
5% 1/16W MF-LF 402
D
1
www.laptop-schematics.com
8
C5590 1 0.0022uF
1
10% 50V CERM 2 402
BC846BMXXH SOT732-3
2 95
CPUTHMSNS_D2_N
Placement note: Place Q5501 on bottom side close to right fin stack
MCP Proximity/MCP Die/Right Heat Pipe C
C
R5500 8
=PP3V3_S3_REMTHMSNS
1
47
PP3V3_S3_REMTHMSNS_R
2
MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V
5% 1/16W MF-LF 402 95 21
C5500 0.1uF 20% R55011 2 10V CERM
MCP_THMDIODE_P
BI
402
1 VDD
SIGNAL_MODEL=EMPTY
C5511
Detect MCP Die Temperature
1
U5500
0.0022uF
10% 50V CERM 2 402
J5502
95 21
78171-0002 M-RT-SM 3
95
Detect Right Heat Pipe Temperature 518S0519
DFN
1
C5521
2
0.0022uF
1
REMTHMSNS_THM_L
ALERT* 8
REMTHMSNS_ALERT_L
SMDATA 9
5 DN2
SIGNAL_MODEL=EMPTY
GND 6
SMCLK 10 THRM_PAD 11
10% 50V CERM 2 402
4 95
R5502
10K
5% 1/16W MF-LF 402 2
THERM* 7
CRITICAL
4 DP2
MCPTHMSNS_D_P
1
10K
5% 1/16W MF-LF
2 402
EMC1403-1 2 DP1 3 DN1
MCP_THMDIODE_N
BI
Note: EMC1403 can perform Beta Compensation for External Diode 1 only
1
=SMBUS_MCPTHMSNS_SDA
BI
45
=SMBUS_MCPTHMSNS_SCL
BI
45
Placement note:
MCPTHMSNS_D_N
Place U5500 near MCP
Placement note: Keep 2 caps as close to IC pins as possible
B
B
GPU Proximity/GPU Die/Left Heat Pipe R5550 8
=PP3V3_S0_GPUTHMSNS
1
47
PP3V3_S0_GPUTHMSNS_R
2
MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V
5% 1/16W MF-LF 402 95 76
1
GPU_TDIODE_P
BI
1 VDD
SIGNAL_MODEL=EMPTY
C5551
Detect GPU Die Temperature
1
U5550
0.0022uF
10% 50V CERM 2 402
95 76
95
3
Detect Left Heat Pipe Temperature
Q5503
A
C5552 0.0022uF
BC846BMXXH SOT732-3
Placement note:
GND 6
10% 50V CERM 2 402
2 95
Place on top side under left heat pipe near CPU
1
5% 1/16W MF-LF 402 2
THERM* 7
GPUTHMSNS_THM_L
ALERT* 8
GPUTHMSNS_ALERT_L
SMDATA 9
5 DN2
SIGNAL_MODEL=EMPTY 1
DFN
CRITICAL
4 DP2
GPUTHMSNS_D_P
1
R5552
10K
10K
5% 1/16W MF-LF
2 402
EMC1403-1 2 DP1 3 DN1
GPU_TDIODE_N
BI
C5550 0.1uF R55511
20% 10V 2 CERM 402
SMCLK 10 THRM_PAD 11
=SMBUS_GPUTHMSNS_SDA
BI
45
=SMBUS_GPUTHMSNS_SCL
BI
45
Thermal Sensors SYNC_MASTER=SENSOR
SYNC_DATE=08/14/2008
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
Placement note:
GPUTHMSNS_D_N
Place U5550 near GPU
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT
Placement note:
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
Keep 2 caps as close to IC pins as possible
SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
48
1
96
A
8
6
7
5
2
3
4
1
D
Left Fan
C 8 7 8
Right Fan
=PP5V_S0_FAN_LT =PP3V3_S0_FAN_LT
8 8
1
R5650 47K
5% 1/16W MF-LF 402 2
42
OUT
SMC_FAN_0_TACH
1
47K
2
7
FAN_LT_TACH
5% 1/16W MF-LF 402
R56511 5% 1/16W MF-LF 402 2 42
IN
SMC_FAN_0_CTL
CRITICAL
J5650
78171-0004 M-RT-SM
1
R5660 47K
5
5
Q5660 2N7002DW-X-G
G
4 S
D
SOT-363 3 7
5% 1/16W MF-LF 402 2
R5665
1 2 3 4
42
OUT
SMC_FAN_1_TACH
1
47K
2
7
FAN_RT_TACH
5% 1/16W MF-LF 402
R56611
6
100K
C
=PP5V_S0_FAN_RT =PP3V3_S0_FAN_RT
CRITICAL
R5655
www.laptop-schematics.com
D
5% 1/16W MF-LF 402 2
518S0369 42
IN
SMC_FAN_1_CTL
78171-0004 M-RT-SM 5 1 2 3 4 6
100K
FAN_LT_PWM
J5660
2
Q5660 2N7002DW-X-G
G
SOT-363 1 S
D 6
7
518S0369
FAN_RT_PWM
B
B
Fan Connectors SYNC_MASTER=M87_MLB
A
SYNC_DATE=10/17/2007
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
49
1
96
A
6
KEYBOARD CONNECTOR
IC
PIN NAME CURRENT
TMP102
V+
PSOC
VDD VOUT VDD
18V BOOSTER
VIN
3V3 LDO
USB INTERFACES TO MLB TRACKPAD PICK BUTTONS SPI HOST TO Z2 KEYBOARD SCANNER
D 51 7 50 51 7 50
PICKB_L BUTTON_DISABLE Z2_HOST_INTN WS_LEFT_SHIFT_KEY WS_LEFT_OPTION_KEY
51 7 51 7
51 7 51 7 51 7 51 7 51 7 51 7 51 7 51 7 51 7 51 7
C
1 2 3 4 5 6 7 8 9 10 11 12 13 14
P2_3 P2_1 P4_7 P4_5 P4_3 P4_1 P3_7 P3_5 P3_3 P3_1 P5_7 P5_5 P5_3 P5_1
P2_5 P2_7 P0_1 P0_3 P0_5 P0_7 VSS VDD P0_6 P0_4 P0_2 P0_0 P2_6 P2_4
WS_CONTROL_KEY Z2_KEY_ACT_L Z2_BOOT_CFG1 TP_P4_5 Z2_DEBUG3 Z2_RESET PSOC_MISO PSOC_F_CS_L PSOC_MOSI PSOC_SCLK Z2_MISO Z2_CS_L Z2_MOSI Z2_SCLK
MAX MAX (TYP) (MAX)
V_SNS
POWER
2.55 KOHM
0.0255 V 0.204 V 0.6 V 0.012 V 0.012 V 0.021 V
0.255E-6 16.32E-6 36E-3 0.72E-3 96E-6 294E-6
10 OHM 0.2 OHM 1.5 OHM
CRITICAL
U5701
CY8C24794 MLF
(SYM-VER2)
APN 337S2983 OMIT
APN 518S0637
4MA (MAX)
4.7 OHM
0.0188 V
75.2E-6 W
50 7 50 7 50 7 50 7
TPAD_DEBUG
P2_2 P2_0 P4_6 P4_4 P4_2 P4_0 P3_6 P3_4 P3_2 P3_0 P5_6 P5_4 P5_2 P5_0 THRML PAD
42 41 40 39 38 37 36 35 34 33 32 31 30 29
50 7 50 7
J5702 FH19C-4S-0.5SH25
WS_KBD17 7 50 WS_KBD16N 50 WS_KBD15_C 50 WS_KBD14 7 50 WS_KBD13 7 50 WS_KBD12 7 50 WS_KBD11 7 50 WS_KBD10 7 50 WS_KBD9 7 50 WS_KBD8 7 50 WS_KBD7 7 50 WS_KBD1 7 50 WS_KBD2 7 50 WS_KBD3 7 50
F-RT-SM1
50
50
50 7
470
50 7
WS_KBD15_C 1
5
NC 50 8
50
R5714
1 2 3 4
=PP3V3_S3_TPAD
ISSP_SCLK_P1_1 ISSP_SDATA_P1_0
ISSP CLOCK ISSP DATA
50 7 50 7
WS_KBD16N
1
6
10K
OUT
25 24 23 22 21 20 19 18 17 16 15
R5710
50
2
5% 1/16W MF-LF 402
C5710
20% 2 10V CERM 402
50 8
50 8
=PP3V42_G3H_TPAD
50 7
WS_LEFT_SHIFT_KBD
50 7
WS_LEFT_OPTION_KBD
50 7
WS_CONTROL_KBD
CRITICAL
50 8
=PP3V3_S3_TPAD
7 51 50 7
9 8 7 6 5 4
1
NC
PLACEMENT_NOTE=NEAR J5713
2
WS_LEFT_SHIFT_KBD
1
5 TC7SZ08AFEAPE SOT665
A
20% 10V CERM 402
4
U5725 Y
SMC_MANUAL_RESET LOGIC 50 8
WS_LEFT_SHIFT_KEY 50
=PP3V42_G3H_TPAD 1
50 8
2
=PP3V42_G3H_TPAD
R5701
USB_TPAD_P
1
24 2
APN 311S0406
50 8
B
TO MLB CONNECTOR
2
PP3V3_S3_PSOC
50
50 7
DIFFERENTIAL_PAIR=USB2_TPAD NET_SPACING_TYPE=USB NET_PHYSICAL_TYPE=USB_90D
WS_LEFT_OPTION_KEY 50
4
U5726 Y
1
WS_LEFT_OPTION_KBD
5
SOT665
A
B
50 7 50 7 50 7
WS_LEFT_SHIFT_KBD WS_LEFT_OPTION_KBD WS_CONTROL_KBD
1 3 6
3
SN74LVC1G10 SC70
A B
U5703
Y
4
43
SMC_TPAD_RST_L
C
2
B
R5702 24 2 1
USB_TPAD_N
90 20
=PP3V3_S3_TPAD
5 TC7SZ08AFEAPE
USB_TPAD_R_P
5%
1/16W MF-LF 402
16V X7R-CERM 402
CRITICAL
CRITICAL
90 20
C5758 0.1UF 10%
B
TP_P7_7
ISSP_SCLK_P1_1 ISSP SCLK/I2C SCL
DIFFERENTIAL_PAIR=USB2_TPAD
31 F-RT-SM
FF14-30A-R11B-B-3H
1
3 50
C
2
0.1UF
50
ISSP_SDATA_P1_0 50 ISSP SDATA/I2C SDA
10
3
C5725
=PP3V42_G3H_TPAD
13 11
50
1K
1
14
WS_KBD17 7 WS_KBD18 7 WS_KBD19 7 WS_KBD20 7 WS_KBD21 7 WS_KBD22 7 WS_KBD23 7 WS_KBD_ONOFF_L
50
2
Z2_CLKIN
26
12
50
0.1UF
ISOLATION CIRCUIT
27
50
50
SMC_ONOFF_L
57
28
50 7
50
2
D
29
WS_KBD15_CAP 7 WS_KBD16_NUM
1% 1/16W MF-LF 402
43 42
50
32 30
WS_KBD1 WS_KBD2 WS_KBD3 WS_KBD4 WS_KBD5 WS_KBD6 WS_KBD7 WS_KBD8 WS_KBD9 WS_KBD10 WS_KBD11 WS_KBD12 WS_KBD13 WS_KBD14
7
R5715 50
NC
2
1% 1/16W MF-LF 402
1
WS_KBD4 7 WS_KBD5 7 WS_KBD6 7
TP_PSOC_P1_3
50 7
APN 518S0430
TEST POINTS ARE FOR ON BOARD PROGRAMMING
NC
=PP3V3_S3_TPAD
IN
50 7
TP_PSOC_SCL
TP_PSOC_SDA
J5713
W W W W W W
50 7
PSOC PROGRAMMING CONNECTOR
15 P1_7 16 P1_5 17 P1_3 18 P1_1 19 VSS 20 D+ 21 D22 VDD 23 P7_7 24 P7_0 25 P1_0 26 P1_2 27 P1_4 28 P1_6
50
10UA 80UA 60MA 60MA 8MA 14MA
R_SNS
50 7
56 55 54 53 52 51 50 49 48 47 46 45 44 43
50
50
WS_KBD23 7 50 WS_KBD22 7 50 WS_KBD21 7 50 WS_KBD20 7 50 WS_KBD19 7 50 WS_KBD18 7 50
PP3V3_S3_PSOC
1
www.laptop-schematics.com
PSOC USB CONTROLLER
2
3
4
5
50
7
8
8
5%
DIFFERENTIAL_PAIR=USB2_TPAD
1/16W MF-LF 402
USB_TPAD_R_N 1
DIFFERENTIAL_PAIR=USB2_TPAD NET_SPACING_TYPE=USB NET_PHYSICAL_TYPE=USB_90D
R5769
=PP3V42_G3H_TPAD
33K
50 8
5%
50 8
=PP3V3_S3_TPAD
2
50 7
WS_CONTROL_KBD
1
1/16W MF-LF 2 402
CRITICAL 5 TC7SZ08AFEAPE SOT665
A
U5727 Y
4
1
R5770 33K 5%
1/16W MF-LF 2 402
1
R5771 33K
5% 1/16W MF-LF 2 402
WS_CONTROL_KEY 50
B
3
U5701 CHIP DECOUPLING PLACE C5701, C5702 & C5703
PLACE C5704, C5705 & C5706
CLOSE TO U5701 VDD PIN 22
CLOSE TO U5701 VDD PIN 49
TPAD BUTTONS DISABLE R5704
50
PP3V3_S3_PSOC 1
C5701
1
4.7UF
2
20% 6.3V X5R 603
1
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM
C5702
1
100PF
2
5% 50V CERM 402
C5703
1
0.1UF
2
10% 16V X7R-CERM 402
C5704
1
100PF
2
5% 50V CERM 402
C5705
1
10% 16V X7R-CERM 402
2
0.1UF
2
1.5 2 =PP3V3_S3_TPAD 8 50
50
5% 1/16W MF-LF 402
BUTTON_DISABLE PLACE THESE COMPONENTS CLOSE TO J5800 THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB
C5706 4.7UF
Q5701
20% 6.3V X5R 603
SSM3K15FV
WELLSPRING 1
D 3
SOD-VESM-HF
SYNC_MASTER=AMASON_M98_MLB SYNC_DATE=06/18/2008
A 1 G SMC_LID 43 42 41
IN
S 2
NOTICE OF PROPRIETARY PROPERTY
THE TPAD BUTTONS WILL BE DISABLE WHEN THE LID IS CLOSED LID OPEN => SMC_LID_LC ~ 3.42V LID CLOSE => SMC_LID_LC < 0.50V
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
50
1
96
A
8
6
7
2
3
4
5
1
BOOSTER +18.5VDC FOR SENSORS BOOSTER DESIGN CONSIDERATION: - POWER CONSUMPTION - DROOP LINE REGULATION - RIPPLE TO MEET ERS - 100-300 KHZ CLEAN SPECTRUM - STARTUP TIME LESS THAN 2MS - R5812,R5813,C5818 MODIFIED
APN 152S0504
PP5V_S3_TPAD_F 51
D5802
1
2 0
5% 1/16W MF-LF 402
R5805
2
INPUT_SW
MIN_LINE_WIDTH=0.50MM
BOOST_SW
VLF3010AT-SM-HF
0.50MM 0.20MM
R5806
SOD-323
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM SWITCH_NODE=TRUE
39PF 2
2
1
3
TPAD_GND_F
CRITICAL
1 C5816 0.1UF
R5801 0 1
PAD
7 51
10% 16V X7R-CERM 402
1
C5817 2.2UF
2
J5800 55560-0227
1% 1/16W MF-LF 2 402
5% 50V CERM 402
TPAD_GND_F 50 7 Z2_CS_L 50 7 Z2_DEBUG3 50 7 Z2_MOSI 50 7 Z2_MISO 50 7 Z2_SCLK 51 7 Z2_BOOST_EN 50 7 Z2_HOST_INTN Z2_BOOT_CFG1 50 7 Z2_CLKIN 50 7
4
BOOST_FB
5
Z2_BOOST_EN
1UF
7 51
1
8
SW
10% 25V X5R 603-1
R5813 71.5K 1% 1/16W MF-LF
1
R5811
2 402
100K
10% 16V X5R 603
2
51 7
PP3V3_S3_LDO
1% 1/16W MF-LF 402 51 7
2
0.50MM 0.20MM
51 7
2
CTRL
THRML
2
C
DO
51
VOLTAGE=0V MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM
PLACEMENT_NOTE=NEAR J5800
FB
QFN
PGND
2
PP5V_S3_TPAD_F
L
GND
4
3
6
1
CRITICAL
1M
TPS61045
VOLTAGE=3V3 MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM
7
2
20% 10V CERM 402
APN 516S0689
1 C5819
U5805
9
1 C5800 0.1UF
7 51
R5812
C5818
VIN
CRITICAL PLACEMENT_NOTE=NEAR J5800
SYM_VER-1
PP18V5_S3
1
NO STUFF
L5800
2
402
MIN_LINE_WIDTH=0.50MM PP5V_S3_BOOSTER MIN_NECK_WIDTH=0.20MM
0.01H-0.3A-80V SM-HF
0 5% 1/16W MF-LF
APN 371S0313
APN 353S1401
=PP5V_S3_TPAD
1
B0520WSXG 1
5% 1/10W MF-LF 603
8
PP18V5_S3_SW
MIN_NECK_WIDTH=0.20MM
1
R5800 0
IPD FLEX CONNECTOR
CRITICAL
L5801 3.3UH-870MA
PLACEMENT_NOTE=under L5800 on top side
D
www.laptop-schematics.com
D
0.50MM 0.20MM
M-ST-SM
2 4 6 8 10 12 14 16 18 20 22
1 3 5 7 9 11 13 15 17 19 21
Z2_KEY_ACT_L 7 50 Z2_RESET 7 50 PSOC_F_CS_L 7 50 PICKB_L 7 50 PSOC_MISO 7 50 PSOC_MOSI 7 50 PSOC_SCLK 7 50 =I2C_TPAD_SDA
45
=I2C_TPAD_SCL 45 PP18V5_S3 7 51 0.50MM 0.20MM
C
TPAD_GND_F
5% 1/10W MF-LF 603 PLACEMENT_NOTE=under L5800 on top side
3V3 LDO FOR IPD R5873 10
51
PP5V_S3_TPAD_F 1
PP5V_S3_VR
2
1% 1/16W MF-LF 402
2
16V
MM3243DRRE
MLF 1 CE
X5R 603
VOUT
1%
1/6W MF 402-HF
VR5802
2.2UF 10%
R5836
VDD
C5853
PP3V3_S3_LDO
C5838
1
0.1UF
2
C5854 4.7UF
10%
PP3V3_S3_LDO_R
3
1
1
2
1
0.2 2
51 7
CRITICAL APN 353S1364
16V X7R-CERM 402
2
20% 6.3V X5R 603
GND
B
4
B
51 7
TPAD_GND_F
Keyboard LED Driver =PP3V3_S0_TPAD
8
=PP5V_S0_KBDLED
CRITICAL
L5850 10UH-0.58A-0.35OHM 1 2 KBDLED_SW MIN_LINE_WIDTH=0.3 MM 1098AS-SM MIN_NECK_WIDTH=0.25 MM
1
R5853
To detect Keyboard backlight, SMC will
470K 5% 1/16W MF-LF 402 2
tristate SMC_SYS_KBDLED: LOW = keyboard backlight present 42
HIGH= keyboard backlight not present IN
J5815
1UF 10% 10V 2 X5R 402-1
F-RT-SM
VIN
51
3 7
R58541 4.7K
5% 1/16W MF-LF 402 2
U5850
R58521
LT3491
1
CAP 4 THRML
KBD BACKLIGHT CONNECTOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
KBDLED_CAP MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
1
7
PAD
C5855
II NOT TO REPRODUCE OR COPY IT
1UF 2
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
10% 35V X5R 603
SIZE
SMC_KDBLED_PRESENT_L 51
DRAWING NUMBER
D APPLE INC.
7
6
5
4
3
2
REV.
051-7546
SCALE
SHT NONE
8
SYNC_DATE=05/12/2008
NOTICE OF PROPRIETARY PROPERTY
1/16W
2 402
2
SYNC_MASTER=PWRSQNC
10 MF-LF
GND
WELLSPRING 2
APN 518S0612
R5855 1%
DFN
10K 5% 1/16W MF-LF 402 2
4
KBDLED_ANODE MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM
CRITICAL
R5853 ALWAYS PRESENT
1 2
LED 5
BOM OPTION: KBDLED_YES
A
SMC_KDBLED_PRESENT_L
SW 3 6 CTRL
NO STUFF
J5815 pin 1 is grounded on keyboard backlight flex
FF18-4A-R11AD-B-3H
SWITCH_NODE=TRUE
C5850 1
SMC_SYS_KBDLED
CRITICAL
1
8
A.0.0 OF
51
1
96
A
8
6
7
2
3
4
5
1
Digital SMS
D
D
Pull-up required if SMS_INT_L not used.
5% 1/16W MF-LF
45
=I2C_SMS_SCL
PROD_DIGSMS
2402
45
=I2C_SMS_SDA
SMS_INT_L
R5931 10K
9
2 VDD
R5932 10K
OUT
ENG_DIGSMS ENG_DIGSMS
1
43
=PP3V3_S3_SMS SCK U5930
7
SDO
8
SDI
4
INT
5
CSB
273141043NC LGA CRITICAL
RESERVED
1
11NC 12NC
2
C5931 0.022UF
10% 16V CERM-X5R 402
2
C5932 0.1UF
Desired orientation when placed on board top-side:
10% 16V X5R 402
+Y +X
1 NC 10NC
Front of system
+Z (up)
GND
ENG_DIGSMS
3
5% 1/16W MF-LF 2402
1
VDDIO
6
1
www.laptop-schematics.com
52 8
=PP3V3_S5_SMC
43 42 8
Circle indicates pin 1 location when placed in correct orientation
ENG_DIGSMS
Stuff R5931 AND NoStuff R5932 to use U5930 NoStuff R5931 AND Stuff R5932 if U5930 is not used
C
C
Analog SMS R5921 PULLS UP SMS_PWRDN TO TURN OFF SMS WHEN PIN IS NOT BEING DRIVEN BY SMC 52 8
=PP3V3_S3_SMS
B
14
1
R59211 5% 1/16W MF-LF 4022 42
IN
SMS_ONOFF_L
SMS_PWRDN MAKE_BASE=TRUE
1
0.1UF 10%
603
AP344ALH 1 5 2 SMS_SELFTEST 15 NC 4 1
R5922 NC 10K
PD ST
+Y 12 SMS_X_AXIS
OUT
42
VOUTY
10 SMS_Y_AXIS
OUT
42
VOUTZ
8
OUT
42
VOUTX
CRITICAL
Front of system
+X
SMS_Z_AXIS
+Z (up)
RES RES NC
NC
NC NC
NC NC
11 NC 13 NC 16 NC
1
GND
C5923
0.01UF 10% 2 16V CERM
7
5% 1/16W MF-LF 2 402
3 NC 6 NC 9
LGA
FS
B
2 4V X5R
402
U5920
Desired orientation when placed on board top-side:
C5926 10UF 20%
2 16V X5R
VDD
10K
C5922
402
1
C5924
0.01UF 10% 2 16V CERM 402
1
C5925
Circle indicates pin 1 location when placed in correct orientation
0.01UF 10% 2 16V CERM 402
Sudden Motion Sensor (SMS) SYNC_MASTER=SENSOR
A
SYNC_DATE=08/14/2008
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
52
1
96
A
8
6
7
2
3
4
5
1
D
44 8
www.laptop-schematics.com
D
=PP3V3_S5_ROM NO STUFF 10K
C
R6150 44
IN
SPI_CLK_MUX
1
PLACEMENT_NOTE=PLACE CLOSE TO U6100 44
IN
SPI_MLB_CS_L
0
5% 1/16W MF-LF 402 2
2
3.3K
5% 1/16W MF-LF 402 2
1
R6101 3.3K
5% 1/16W MF-LF 2 402
C6100 1
8
R61901 R61001
CRITICAL
VCC
0.1UF
20% 10V CERM 2 402
U6100 32MBIT
SPI_CLK
5% 1/16W MF-LF 402
6 SCLK
SI/SIO0 5 MX25L3205DM2I-12G
1 CE*
SPI_WP_L SPI_HOLD_L
SPI_MOSI
90 44
SO/SIO1 2
7 HOLD*
SPI_MISO_R NO STUFF
90
1
R6191 10K
GND
1
R6105
OMIT
3 WP*/ACC
C
R6152
SOP 90 44
1
0
5% 1/16W MF-LF 402
2
0
5% 1/16W MF-LF 402
2
SPI_MOSI_MUX
IN
44
PLACEMENT_NOTE=PLACE CLOSE TO U6100
SPI_MISO_MUX
OUT
44
PLACEMENT_NOTE=PLACE CLOSE TO U6100
4
5% 1/16W MF-LF 2 402
MCP79 SPI Frequency Select Frequency
B
SPI_MOSI
SPI_CLK
31 MHz
0
0
42 MHz
0
1
25 MHz
1
0
1 MHz
1
1
B
25MHz is selected with R5190 and R5191 Any of the 4 frequencies can be selected with R6190, R6191, R5190 and R5191
SPI ROM SYNC_MASTER=CHANG_M98_MLB
A
SYNC_DATE=07/01/2008
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
53
1
96
A
8
6
7
2
3
4
5
1
AUDIO CODEC APPLE P/N 353S1527
XW6203 SM 54
MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V
FERR-220-OHM 2 =PP3V3_S0_AUDIO 1
IN
C6201
0.001UF
20% 4V X5R 2 402
10% 50V 2 CERM 402
1
C6203
0.001UF
OUT
HDA_BITCLK HDA_SYNC HDA_SDOUT HDA_SDIN0
1
22
2
OUT IN
OUT
56
OUT
56
OUT
BCLK
10 5
SYNC
8
AUD_GPIO_0 AUD_GPIO_1
1
33
2
AUD_GPIO_0_R
2 3
AUD_BI_PORT_C_R
48
SPDIFI/EAPD/MIDI-I/DMIC-R
47
0.001UF
0.001UF
20% 50V 2 CERM 402
GND_AUDIO_CODEC
AUD_SPDIF_O
33
1
AUD_SPDIF_OUT
2
5% 1/16W MF-LF 402
AUD_SPDIF_IN AUD_SENSE_A AUD_SENSE_B
U6200
SENSE_A
13
SENSE_B
34
PORT-A-L
39 41
AUD_BI_PORT_A_L AUD_BI_PORT_A_R AUD_BI_PORT_F_L AUD_BI_PORT_F_R AUD_VREF_PORT_F AUD_VREF_PORT_A AUD_BI_PORT_E_L AUD_BI_PORT_E_R
REV B3
GPIO0/DMIC-CLK
PORT-A-R
PORT-C-L
PORT-F-L PORT-F-R
16
NO_TEST 23 24
PORT-F-VREFO
35
PORT-D-L PORT-D-R
30 33
36
NO_TEST 18 NO_TEST 19 NO_TEST 20
BEEP HDA_RST_L
PORT-C-R
PORT-A-VREFO/DCVOL PORT-E-L
CD-R
12
BEEP
11
RESET*
PORT-B-R
22
OUT
58
IN
58
IN
59
IN
59
IN
55
1
0.1UF
43 NO_TEST 44 NO_TEST
NC_AUD_BI_PORT_G_L NC_AUD_BI_PORT_G_R
45 NO_TEST 46 NO_TEST
NC_AUD_BI_PORT_H_L NC_AUD_BI_PORT_H_R
VREF JDREF NC
27 40 37
55
IN
59
IN
59
OUT
59
OUT
55
IN
59
IN
59
OUT
57
OUT
57
OUT
57
C
NC_AUD_VREF_PORT_C NC_AUD_VREF_PORT_B2
PORT-G-L
C6220
10% 2 16V X5R 402
4
5% 1/16W MF-LF 2 402
AUD_VREF_PORT_B AUD_BI_PORT_B_L AUD_BI_PORT_B_R
29 NO_TEST 32 NO_TEST
PORT-H-R
IN
NC_AUD_VREF_PORT_E
PORT-C-VREFO PORT-B-VREFO2
26 AVSS1 42 AVSS2
100K
14
PORT-B-L
PORT-G-R
7 DVSS
R6205
17
15 31 NO_TEST 28 21
PORT-E-VREFO PORT-B-VREFO
CD-L CD-GND
PORT-H-L
1
AUD_CODEC_VREF AUD_CODEC_JDREF NC_VRP
1
R6207 100K
NO_TEST 1
R6206
1
20.0K
1% 1/16W MF-LF 2 402
2
C6222
5% 1/16W MF-LF 2 402
0.001UF
CRITICAL
C6221
1
10% 2 50V CERM 402
3.3UF
XW6201
10% 16V 2 TANT SMA-HF
SM 1 59 57 56 55 54
54 55 56 57 59
ALC885-VB3-GR
PORT-E-R
IN
10% 50V 2 CERM 402
C6207
R6203 SPDIFO
GPIO1/DMIC-L
AUD_BI_PORT_D_L AUD_BI_PORT_D_R NC_BAL_IN_L NC_BAL_IN_COM NC_BAL_IN_R
90 21
20% 6.3V 2 TANT CASE-AL1
1
LQFP
5% 1/16W MF-LF 402
C
1
CRITICAL
SDATA_OUT SDATA_IN
R6250
NC_AUD_BI_PORT_C_L 57
6
CODEC_SDATA_IN
5% 1/16W MF-LF 402 56
54 55 59
D C6206
C6204 1 100UF
10% 50V 2 CERM 402
R6204 90 21
PP4V6_AUDIO_ANALOG
2
AVDD_ADC_DAC
AVDD1 25 AVDD2 38
IN
1
4.7UF
20K
5% 1/16W MF-LF 402 2
90 21
1
DVDD 1 DVDD_IO 9
R6251
90 21
0
CRITICAL
C6200
1
IN
1
MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.20MM
CODEC_DVDD
0402
9
MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM VOLTAGE=4.6V
R6208
2
www.laptop-schematics.com
D
1
5% 1/16W MF-LF 402
L6201
59 58 54 8
4V6_REG_SENSE
GND_AUDIO_CODEC MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=0V
B
B
AUDIO 4.6V REGULATOR APPLE P/N 353S1897
C6211 0.015UF 1 4V6_REG_BP 2 CRITICAL
L6200
FERR-220-OHM 56 9
1
PP5V_S3_AUDIO
2
U6201
MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=5V
MAX8902A
AUD_4V6_REG_IN
3
EN
1
IN
0402
R6220 59 58 54 8
=PP3V3_S0_AUDIO
1
1K
2
7
AUD_REG_SHDN_L
5% 1/16W MF-LF 402 1
C6210 0.1UF
R6221 10K
5% 1/16W MF-LF 2 402
10% 2 16V X5R 402
CRITICAL
C6208 1 10UF
20% 16V TANT-POLY 2 2012-LLP
1
C6209
TDFN
SELA SELB
4 5
OUT OUTS
8 6
PP4V6_AUDIO_ANALOG 54 55 59
4V6_REG_SENSE
54
BP GND
1
10% 16V X7R 402
2
THRML PAD
CRITICAL
9
1
0.001UF
C6205 100UF
10% 2 50V CERM 402
20% 2 6.3V TANT CASE-AL1
1
C6212 0.1UF 10% 16V 402
2 X5R
AUDIO:CODEC SYNC_MASTER=AUDIO
A
XW6200 SM 1
2
SYNC_DATE=07/09/2008
NOTICE OF PROPRIETARY PROPERTY
GND_AUDIO_CODEC 54 55 56 57 59
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
54
1
96
A
8
6
7
2
3
4
5
1
D
D
L6300
FERR-220-OHM 59 54
PP4V6_AUDIO_ANALOG
1
2
www.laptop-schematics.com
Pseudo-Diff Line-In Filter GAIN = -5.4DB AV = 0.52 FC = 1.8 HZ MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.20MM PP4V6_AUDIO_LINE_IN
0402
CRITICAL
C6310 10UF 58
IN
2
AUD_LI_INL
1
R6310
AUD_LI_INL_C
25.5K2
1
R6312 13.3K2
AUD_LI_INL_R
1
1% 1/16W MF-LF 402
20% 16V TANT-POLY 2012-LLP
1% 1/16W MF-LF 402
C6312 2.2UF 1
AUD_PORTA_L 1
R6302
CRITICAL
27.4K
C6301 1
1% 1/16W MF-LF 402 2
C
2.2UF
20% 6.3V 2 CERM 402-LF
CRITICAL
8
C6300 1
UMAX-HF 9
0.001UF
AUD_BI_PORT_A_L
OUT
54
CRITICAL
U6300
10% 50V CERM 2 402
2 10% 16V X5R 603
10CRITICAL MAX4253EUB V+
C
6
7
V-
4
AUD_LIFILT_SHUTDOWN_L
IN
59
IN
54
CRITICAL 58
IN
C6311 10UF
AUD_LI_GND
2
R6301 1
10
2
5% 1/16W MF-LF 402
59 57 56 55 54
1
R6311
AUD_LIFILT_LT_R
25.5K2
1
2
1
AUD_LIFILT_RT_R
1% 1/16W MF-LF 402
R6320
R6322
25.5K2
1
AUD_LIFILT_RT
1% 1/16W MF-LF 402
20% 16V TANT-POLY 2012-LLP
GND_AUDIO_CODEC
13.3K2
1
1% 1/16W MF-LF 402
20% 16V TANT-POLY 2012-LLP
C6320 10UF
R6313 AUD_LIFILT_LT
R6300 1 165 2
AUD_CODEC_INREF
AUD_VREF_PORT_A
1% 1/16W MF-LF 402
13.3K2
1
CRITICAL
1% 1/16W MF-LF 402
CRITICAL
C6303 1
1
0.001UF
CRITICAL
C6302 100UF
10% 50V CERM 2 402
20%
2 6.3V TANT
CASE-AL1
4 3
V-
R63031
2
27.4K
V+
1% 1/16W MF-LF 402 2
B
UMAX-HF
MAX4253EUB CRITICAL AUD_PORTA_R
10
C6321 10UF IN
2
AUD_LI_INR
1
R6321
AUD_LI_INR_C
25.5K2
1
20% 16V TANT-POLY 2012-LLP
AUD_BI_PORT_A_R
OUT
C6322 2.2UF 1
2
B
54
10% 16V X5R 603
R6323 AUD_LI_INR_R
1% 1/16W MF-LF 402
54 55 56 57 59
1
CRITICAL
58
GND_AUDIO_CODEC 5
U6300
CRITICAL
13.3K2
1
1% 1/16W MF-LF 402
AUDIO: LINE IN SYNC_MASTER=AUDIO
A
SYNC_DATE=07/09/2008
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
55
1
96
A
8
6
7
2
3
4
5
1
Headphone Amplifier (MAX9724A) APN:353S1637 D
L6500
D
FERR-120-OHM-1.5A 1 2 PP5V_AUDIO_HPAMP_PVDD_F VOLTAGE=5V MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 mm
0402
CRITICAL
C6500 1 10UF
20% 16V TANT-POLY 2 2012-LLP
1
C6501
0.001UF
10% 50V 2 CERM 402
AUD_HPAMP_OUTL_R
56
IN
56
IN
AUD_HPAMP_INL_M AUD_HPAMP_INR_M
CRITICAL
6 INL 8 INR
U6500 MAX9724A
OUTL 11 OUTR 10
1
TQFN
L6501
AUD_HPAMP_MUTE_L
10K
1
59 57 55 54
1UF
10% 10V X5R 2 402
2
AUD_PORTD_R MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.15 mm
AUD_HPAMP_OUTR_R
OUT
58
OUT
58
56
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.15 mm
R65141
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 mm
2.21K
1% 1/16W MF-LF 402 2
C6503
10% 2 10V X5R 402
CRITICAL
C6502 1
1
R6524 2.21K
1% 1/16W MF-LF 2 402
C
10UF
10% 16V X5R-CERM 2 0805
GND_AUDIO_HPAMP_PGND
2
0
5% 1/16W MF-LF 402
MAX9724_PVSS CRITICAL 1UF
1
1
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.15 mm
MIN_LINE_WIDTH=0.20 mm MIN_NECK_WIDTH=0.10 mm
5% 1/16W MF-LF 402 2
XW6500 SM
R6523
MAX9724_C1N
R65001
C
AUD_PORTD_L
2
C6504 1
4 PVSS
2 0402
9 SVSS
1
2 PGND
AUD_GPIO_0
7 SGND
IN
13 THRM PAD
54
MAX9724_C1P CRITICAL
C1P 1 C1N 3
5 SHDN*
FERR-1000-OHM
0
5% 1/16W MF-LF 402
56
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.15 mm
R6513
VDD
www.laptop-schematics.com
PP5V_S3_AUDIO
12
54 9
GND_AUDIO_CODEC
XW6501 SM 1
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 mm
2
AUD_LO_GND
IN
58
1st Order DAC Filter HP:3.52 HZ LP:34 KHZ VOLTAGE GAIN:1.53
B
B CRITICAL
C6510 3.3UF
54
AUD_BI_PORT_D_L
IN
1
2
R6510
R6511
1
1
13.7K2
AUD_CODEC_OUTL_C
1% 1/16W MF-LF 402
10% 16V TANT SMA-HF
21K
2
AUD_HPAMP_OUTL_R
56
AUD_HPAMP_OUTR_R
56
1% 1/16W MF-LF 402
CRITICAL
C6511 220PF
56
2
AUD_HPAMP_INL_M
1
5% 25V CERM 402
CRITICAL
C6521 220PF
56
2
AUD_HPAMP_INR_M CRITICAL
C6520 3.3UF 54
IN
AUD_BI_PORT_D_R
A
1
2
1
5% 25V CERM 402
AUD_CODEC_OUTR_C
R6520
R6521
1
1
13.7K2 1% 1/16W MF-LF 402
10% 16V TANT SMA-HF
21K
2
AUDIO: HEADPHONE AMP
1% 1/16W MF-LF 402
SYNC_MASTER=AUDIO
SYNC_DATE=07/09/2008
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
56
1
96
A
8
6
7
2
3
4
5
1
2X MONO SPEAKER AMPLIFIERS (LM48310) APN: 353S1901 GAIN = 12DB 79Hz < FC (L&R) < 93Hz 53Hz < FC (SUB) < 62Hz
D
D
PLACE C6611/C6612 CLOSE TO PVDD PIN
PP5V_S3_AUDIO_AMP
CRITICAL
C6612 1 47UF
20% 6.3V TANT-POLY 2 CASE-A4
CRITICAL 1
L6610
54
IN
2
AUD_SPKRAMP_INL_L
0402
10% 16V X7R-CERM 402
L6601
54
IN
2
FERR-1000-OHM 2 AUD_VREF_PORT_B 1
9 PVDD
U6610 LM48310L_PIN LM48310L_NIN
1
100K
59 57 56 55 54
C
57
OUTA 10 OUTB 7
SYNC_OUT 6 5 SYNC_IN
SPKRAMP_L_P_OUT SPKRAMP_L_N_OUT
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM
C6614
8
95 57
SPKRAMP_L_P_OUT
PLACE CLOSE TO U6610 PIN6
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM
R6602 33
95 57
5% 1/16W MF-LF 2 402
11
GND_AUDIO_CODEC
SPKRAMP_L_N_OUT
R6611 0
2
CRITICAL
L6620
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM
1
AUD_BI_PORT_B_R
2
20% 6.3V TANT-POLY 2 CASE-A4
1
AUD_SPKRAMP_INR_L
1
2
10% 16V X7R-CERM 402
SPKRAMP_R_P_OUT
R6620 2
9 PVDD
3 VDD
10% 2 10V X5R 402-1
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM 95 57
SPKRAMP_R_N_OUT
2
U6620 1 IN_P 2 IN_N
LM48310R_PIN LM48310R_NIN
LLP
OUTA 10 OUTB 7
SPKRAMP_R_P_OUT SPKRAMP_R_N_OUT
1
CRITICAL
C6624 0.1UF
8
1
0
33
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM
2
SPKRAMP_SYNC2 57
95 57
SPKRAMP_S_P_OUT
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM
PLACE C6631/C6632 CLOSE TO PVDD PIN
R6630 2
IN
1
AUD_BI_PORT_C_R
2 0402
57
2 10% 10V X5R 402
LM48310S_PIN LM48310S_NIN
9 PVDD
1 IN_P 2 IN_N
AUD_SPKRAMP_SHUTDOWN_L 1
3 VDD
LLP
7 58 95
OUT
7 58 95
B
SPKRAMP_S_N_OUT
R6631 2
0
1
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM
SPKRCONN_S_N_OUT
C6630
10% 2 10V X5R 402-1
OUTA 10 OUTB 7
0.15UF
CRITICAL THRML PAD
GND 8
SPKRAMP_S_P_OUT SPKRAMP_S_N_OUT
57 95 57 95
NOSTUFF SYNC_OUT 6 5 SYNC_IN
C6634
10% 10V 2 X5R 402 59 57 56 55 54
OUT
1UF
0.001UF
4 SD*
CRITICAL
A
SPKRCONN_S_P_OUT
LM48310
0.15UF 1
1
C6631
1
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM
U6630
C6633 AUD_SPKRAMP_INS_L
CRITICAL
CRITICAL
0
5% 1/16W MF-LF 402
PP5V_S3_AUDIO_AMP
CRITICAL
7 58 95
5% 1/16W MF-LF 402
95 57
L6630
SPKRCONN_R_N_OUT
2
PLACE CLOSE TO U6620 PIN6
FERR-1000-OHM
OUT
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM
57 95
5% 1/16W MF-LF 402
20% 6.3V 2 TANT CASE-AL1
1
57 95
R6604
10% 2 50V CERM 402
0
SPKRAMP_SYNC1 57
B
100UF
7 58 95
5% 1/16W MF-LF 402
U6620_SOUT
1
OUT
11
GND_AUDIO_CODEC
C6632 1
SPKRCONN_R_P_OUT
5% 1/16W MF-LF 402
THRML PAD
GND
CRITICAL
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM
R6603
SYNC_OUT 6 5 SYNC_IN
AUD_SPKRAMP_SHUTDOWN_L
10% 2 16V X7R-CERM 402
1
NOSTUFF
4 SD*
1
0
R6621
LM48310
CRITICAL
54
7 58 95
5% 1/16W MF-LF 402
C6620 1UF
0.001UF
0.1UF
0402
1
C6621
10% 2 50V CERM 402
95 57
CRITICAL
CRITICAL
C6623
FERR-1000-OHM
57 9
OUT
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM
SPKRCONN_L_N_OUT
1
C
47UF
59 57 56 55 54
7 58 95
AUD_SPKRAMP_SHUTDOWN_L
C6622 1
57
OUT
5% 1/16W MF-LF 402
PP5V_S3_AUDIO_AMP
IN
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM
SPKRCONN_L_P_OUT
1
SPKRAMP_SYNC1 57
CRITICAL
54
0
2
5% 1/16W MF-LF 402
PLACE C6621/C6622 CLOSE TO PVDD PIN 57 9
R6610
57 95
1
THRML PAD
GND
10% 16V 2 X7R-CERM 402
57 95
U6610_SOUT
CRITICAL
0.1UF
5% 1/16W MF-LF 402 2
LLP
4 SD*
CRITICAL
R6601
3 VDD
LM48310 1 IN_P 2 IN_N
0402 1
SPEAKER CHECKPOINTS
10% 2 10V X5R 402-1
0.1UF 1
C6610 1UF
10% 2 50V CERM 402
C6613
FERR-1000-OHM 1
1
0.001UF
CRITICAL AUD_BI_PORT_B_L
CRITICAL
C6611
www.laptop-schematics.com
57 9
R6605 1
0
2
5% 1/16W MF-LF 402
AUDIO:SPEAKER AMP SYNC_MASTER=AUDIO
11
SPKRAMP_SYNC2 57
GND_AUDIO_CODEC
SYNC_DATE=07/09/2008
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
57
1
96
A
8
6
7
2
3
4
5
1
AUDIO JACK 1 LO/HP JACK, SPDIF TX AUD_SPDIF_OUT
D
AUD_CONNJ1_SLEEVE
0
1
CRITICAL
J6700
AUD_CONNJ1_RING
F-RT-TH3
1
6 5
1
AUD_CONNJ1_SLEEVE_F
2
AUD_CONNJ1_TIPDET
1
AUDIO
R6716
A - VIN B - VCC C - GND
AUD_CONNJ1_TIP
0
1
5% 1/16W MF-LF 402
9
OPERATING VOLTAGE 3.3
POF
AUD_CONNJ1_SLEEVEDET 10
SHIELD PINS
1
13
C6700 0.1UF
10% 16V 2 X5R 402
1
59
M-RT-SM 4
2
59 7
OUT
59 7
OUT
59 7
OUT
BI_MIC_LO BI_MIC_SHIELD BI_MIC_HI
1 2 3
5
FERR-220-OHM-2.5A 1
2
AUD_CONNJ1_RING_F
2
AUD_LO_GND
56
OUT
0603
CRITICAL
L6704
FERR-220-OHM 1
AUD_CONNJ1_TIPDET_F
2
2
AUD_PORTD_R
BI
56
BI
56
0402
CRITICAL
L6706
FERR-220-OHM 1
AUD_CONNJ1_TIP_F
2
2
AUD_PORTD_L
0402
R6710 0
1
C6701
R6700 AUD_CONNJ1_SLEEVEDET_F
2
CRITICAL
CRITICAL
2.2UF
DZ6705
20% 6.3V 2 CERM 402-LF
OUT
78171-0003
L6701
5% 1/16W MF-LF 402
11 12
SHELL
HS_MIC_LO
APN: 518S0520
CRITICAL
5% 1/16W MF-LF 402
4
7 8
0
59
0402
R6715
1 3
OUT
FERR-1000-OHM
5% 1/16W MF-LF 402
2
HS_MIC_HI
L6702
R6714 0
2 0402
5% 1/10W MF-LF 603
AUDIO-JACK-TRANS-M97
C
1
R6711
APN: 514-0607
J6780
FERR-1000-OHM AUD_CONNJ1_SLEEVE2_F
2
5% 1/16W MF-LF 402
=PP3V3_S0_AUDIO
CRITICAL
www.laptop-schematics.com
59 58 54 8
0
1
D
MIC CONNECTOR
54
L6703
R6713 AUD_CONNJ1_SLEEVE2
IN
DZ6702
2
2
CRITICAL
6.8V-100PF
1
2
DZ6706
6.8V-100PF
402
402
1
AUD_J1_TIPDET_R
OUT
59
C
2
SPEAKER CONNECTOR CRITICAL
1
J6781
DZ6703
6.8V-100PF
59
0402
CRITICAL
1
CRITICAL
2
1
OUT
FERR-1000-OHM
402
402
AUD_J1_SLEEVEDET_R
L6705
2
6.8V-100PF
402
2
5% 1/16W MF-LF 402
DZ6704
6.8V-100PF
10K
1
1
APN: 518S0519
C6705 100PF
5% 2 50V CERM 402
1
GND_CHASSIS_AUDIO_JACK
58
95 57 7
IN
95 57 7
IN
78171-0002 M-RT-SM 3
SPKRCONN_L_P_OUT SPKRCONN_L_N_OUT
1 2
4
CRITICAL
RETURN FOR HF NOISE
J6782
APN: 518S0521
78171-0004 M-RT-SM 5
R6701 58 59 58 54 8
B
GND_CHASSIS_AUDIO_JACK
APN: 514-0608
1
10
CRITICAL
J6750
AUD_SPDIF_IN
2
5% 1/16W MF-LF 402
AUD_CONNJ2_SLEEVE
AUDIO-RCVR-M97
OUT
1
0
A - VDD B - GND C - VOUT
1
0
7 8
SHELL SHIELD PINS
11 12
AUD_CONNJ2_SLEEVEDET 1
0
0.1UF
1 2 3 4
C6783 1 100PF 5% 50V NOSTUFF CERM CRITICAL 402
NOSTUFF CRITICAL
2
1
NOSTUFF CRITICAL
NOSTUFF CRITICAL
54
C6781 1
1
100PF
2
AUD_LI_INR
BI
55
AUD_LI_INL
BI
55
1
B
6
C6784 100PF 5%
2
2 50V CERM
402
C6782 100PF
5% 50V CERM 2 402
FERR-1000-OHM
5% 50V 402
2 CERM
0402
L6756
0
1
AUD_CONNJ2_TIP_F
2 0402
2
L6758
5% 1/16W MF-LF 402
FERR-220-OHM 1
CRITICAL
DZ6753
10% 2 16V X5R 402
CRITICAL
2
CRITICAL
1
2
DZ6752 402
1
55
CRITICAL
AUD_J2_TIPDET_R
OUT
59
AUDIO: JACKS SYNC_MASTER=AUDIO
1
C6756
1
402
5% 50V 2 CERM 402
1
2 0402
DZ6754
6.8V-100PF
6.8V-100PF
AUD_LI_GND
2
L6752
1
402
402
A
1
FERR-1000-OHM
2
6.8V-100PF
6.8V-100PF
XW6701 SM
0402
DZ6755
2
AUD_J2_COM
2
AUD_CONNJ2_SLEEVEDET_F
2
5% 1/16W MF-LF 402
C6750
IN
L6754
AUD_CONNJ2_TIPDET_F
R6766 1
1
IN
95 57 7
SPKRCONN_S_P_OUT SPKRCONN_S_N_OUT SPKRCONN_R_P_OUT SPKRCONN_R_N_OUT
FERR-1000-OHM
R6768
10
2
AUD_CONNJ2_RING_F
POF 9
1
5% 1/16W MF-LF 402
2
AUD_CONNJ2_TIP
OPERATING VOLTAGE 3.3
0
1
5% 1/16W MF-LF 402
6
95 57 7
0402
R6764 AUD_CONNJ2_RING
AUDIO
IN
R6762
1 3 4
IN
95 57 7
FERR-220-OHM AUD_CONNJ2_SLEEVE_F
2
5% 1/16W MF-LF 402
AUD_CONNJ2_TIPDET
95 57 7
L6751
R6761
F-RT-TH3 5 2
2
5% 1/16W MF-LF 402
R6749 AUD_J2_OPT_OUT
0
1
=PP3V3_S0_AUDIO
SYNC_DATE=07/09/2008
NOTICE OF PROPRIETARY PROPERTY
100PF THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
GND_CHASSIS_AUDIO_JACK
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 58
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
AUDIO JACK 2 LINE IN JACK, SPDIF RX
SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
58
1
96
A
8
6
7
2
3
4
5
1
PORT E (HEADSET MIC)
NOSTUFF
L6881
FERR-1000-OHM 59 55 54
PP4V6_AUDIO_ANALOG
1
2
VOLTAGE=4.6V MIN_LINE_WIDTH=0.10 mm MIN_NECK_WIDTH=0.10 mm
0402
MIKEY
L6880
CODEC OUTPUT SIGNAL PATHS MIXER(OUTPUT) 0X0C (12) 0X0D (13) 0X0F (15)
PIN COMPLEX MUTE CONTROL 0X14 (20,D) GPIO_0 0X18 (24,B) VREF_B (100%) 0X1A (26,C) VREF_B (100%) 0x1E (SPDIF OUT) N/A
DET ASSIGNMENT 0X14 (20,D) N/A N/A 0X16 (22,G)
CODEC INPUT SIGNAL PATHS FUNCTION LINE IN SPDIF IN BUILT-IN MIC HEADSET MIC
MIXER(INPUT) 0X23 (35) N/A 0X24 (36) 0X24 (36)
59 58 54 8
PIN COMPLEX 0X15 (21,A) 0x1F (SPDIF IN) 0X19 (25,F) 0X1B (27,E)
VREF VREF_A (50%) N/A VREF_F (100%) MIKEY
1
45
IN
0 MIKEY 2
=I2C_MIKEY_SCL
CRITICAL MIKEY 1
1
5% 1/16W 402 MF-LF
R6891
BI
0 MIKEY 2
=I2C_MIKEY_SDA
1
21
OUT
0 MIKEY 2
AUD_I2C_INT_L
59 54
OUT
AUD_SENSE_A
59
R6893 IN
2
0
1
SCL
MICBIAS
B1
HS_MIC_BIAS
HS_SDA
A3
SDA
DETECT
A1
HS_SW_DET
HS_INT_L
C3
INT*
HS_RST_L
B2
ENABLE GND
MIKEY
R68801
PORT G DETECT(SPDIF DELEGATE)
PP3V3_S0_AUDIO_F
1
HS_RX_BP
4.7UF 20% TANT 603-HF
MIKEY 1
GND_AUDIO_CODEC
C6881
5% 1/16W MF-LF 402 2
0.01UF 16V
MIKEY
10% 402 CERM 2
1
R6881
R6882
5% 1/16W MF-LF 2 402
Q6800
47K
D 3
Q6801
SOT563
1
C6883 0.1UF
AUD_PORTG_DET_L NC
54
D 3
SSM6N15FEAPE
SSM6N15FEAPE
54
SSM6N15FEAPE
SOT563
OUT
1
AUD_BI_PORT_E_L
OUT
5 G
5% 1/16W MF-LF 402
1
AUD_BI_PORT_E_R
1
R6883 100K
SOT563
5 G
2 G
S 4
5% 1/16W MF-LF 2 402
XW6880 SM
S 4
C6801
HS_MIC_HI
S 1
59 57 56 55 54
GND_AUDIO_CODEC
1
IN
58
IN
58
OMIT
10% 25V X5R 402
AUD_J1_DET_RC
2
2
MAKE_BASE=TRUE
D 6
Q6801
5% 1/16W MF-LF 2 402
MIKEY CRITICAL
1% 1/16W MF-LF 2 402
AUD_PORTD_DET_L NC
R6802 AUD_J1_TIPDET_R
10K
1% 1/16W MF-LF 2 402
2.2K
1% 1/16W MF-LF 402 2
GND_AUDIO_CODEC
54 55 56 57 59
MIKEY
1
R6805
5.11K
AUD_OUTJACK_INSERT_L
C6882
2 6.3V
1
R6806
220K
IN
C1
MIKEY CRITICAL 1
10K
R6801
58
BYPASS
100K
HS_INT_L PULLUP ON MCP PAGE
59 57 56 55 54
1
C
U6880 CD3272A2 WCSP9
1
5% 1/16W 402 MF-LF
AUD_IPHS_SWITCH_EN
D
MIKEY
B3
MIKEY AUD_SENSE_B
AVDD
HS_SCL
5% 1/16W 402 MF-LF
OUT
6.3V 20% 2 603 X5R
10UF
R6892
19 9
54
C6880
5% 1/16W 402 MF-LF
DET ASSIGNMENT 0X15 (21,A) N/A N/A MIKEY
PORT D DETECT (Line-out)
PP3V3_S0_HS_RX
2
0402
R6890
45
CONVERTER 0X08 (8) 0X0A (10) 0X07 (7) 0X07 (7)
=PP3V3_S0_AUDIO
OMIT
C6884
1
1
15PF
OMIT
C6885
0.001UF
50V 5% 402 CERM 2
C
50V 2 10% CERM 402
HS_MIC_LO
2
0.1UF
10V 2 20% CERM 402 59 57 56 55 54
GND_AUDIO_CODEC
R6803 59
PP3V3_S0_AUDIO_F
1 1
R6861 220K
59 58
AUD_J1_SLEEVEDET_R
IN
100K 2 5% 1/16W MF-LF 402
5% 1/16W MF-LF 2 402
TABLE_5_HEAD
PART#
DESCRIPTION
REFERENCE DESIGNATOR(S)
BOM OPTION
AUD_J1_SLEEVEDET_INV
TABLE_5_ITEM
116S0114
1
100K 5% 0402 RESISTOR
R6883
MIKEY
131S1513
1
15PF 5% 0402 CAPACITOR
C6884
MIKEY
132S0045
1
100PF 10% 0402 CAPACITOR
C6885
MIKEY
116S0004
1
0 OHMS 5% 0402 RESISTOR
R6883
NOMIKEY
116S0004
1
0 OHMS 5% 0402 RESISTOR
C6884
NOMIKEY
116S0004
1
0 OHMS 5% 0402 RESISTOR
C6885
NOMIKEY
TABLE_5_ITEM
Q6800
D 6
59 58
AUD_J1_SLEEVEDET_R
TABLE_5_ITEM
SSM6N15FEAPE SOT563
TABLE_5_ITEM
TABLE_5_ITEM
1
C6802
2 G
0.01UF
59 57 56 55 54
QTY
S 1
TABLE_5_ITEM
10% 2 16V CERM 402
GND_AUDIO_CODEC
LINE_IN AMP SHUTDOWN CONTROL 59 55 54
PORT F (BUILT-IN MIC)
PP4V6_AUDIO_ANALOG
PORT A DETECT (Line-in)
1
R6815
1 59 54
B
5% 1/16W MF-LF 2 402
R6813
PP3V3_S0_AUDIO_F
Q6803 AUD_INJACK_INSERT_L
270K
5% 1/16W MF-LF 2 402
SSM3K15FV
D 3
1
47K
NC
2
D 6
59 57 56 55 54
AUD_LIN_SHUTDOWN
1 G
C6811
5 G
S 2
5% 1/16W MF-LF 402
B
20% TANT-POLY 2012-LLP
GND_AUDIO_CODEC
L6850
FERR-1000-OHM
0.1UF OUT
OUT
1
AUD_BI_PORT_F_L
2
BI_MIC_HI_F
AUD_BI_PORT_F_R
1
R6852 100K
XW6850 SM GND_AUDIO_CODEC
59 57 56 55 54
2 20% CERM 402
1
2
5% 1/16W MF-LF 2 402
C6852 15PF 50V
1
5% 402 CERM 2
1
GND_CHASSIS_AUDIO_MIC
1
IN
7 58
IN
7 58
IN
7 58
C6851 0.001UF
10% 50V 2 CERM 402
BI_MIC_LO_F
L6851
FERR-1000-OHM 1
2
BI_MIC_LO
0402
XW6851 SM
GND_AUDIO_CODEC
BI_MIC_HI
2
0402
10% 25V X5R 402
S 4
0.1UF 10V
1
MAKE_BASE=TRUE
S 1 54
1
10UF
2.2K 2
C6850
D 3
SOT563
C6853
1
1
CRITICAL 54
2 G
R6850 BI_MIC_BIAS CRITICAL
2 16V
SOT563
Q6803
2.2K 2
AUD_J2_DET_RC
5% 1/16W MF-LF 402
59 57 56 55 54
1
SSM6N15FEAPE
SSM6N15FEAPE
R6812 AUD_J2_TIPDET_R
AUD_VREF_PORT_F
55
Q6802 SOD-VESM-HF
IN
IN
5% 1/16W MF-LF 402 OUT
1% 1/16W MF-LF 402 2
R6811
54
AUD_LIFILT_SHUTDOWN_L
39.2K
1
58
5% 1/16W MF-LF 2 402
100K
1
59
100K
R6814
AUD_SENSE_A
OUT
R6855
www.laptop-schematics.com
CONVERTER 0X02 (2) 0X03 (3) 0X05 (05) 0X06 (6)
A2
D
VOLUME 0X0C (12) 0X0D (13) 0X0F (15) N/A
C2
FUNCTION HP/LINE OUT SATELLITES SUB SPDIF OUT
FERR-1000-OHM
BI_MIC_SHIELD
2
1
R6851 0
5% 1/16W MF-LF 2 402
PLACE L6800/C6800 CLOSE TO Q6800/01/02
AUDIO: JACK TRANSLATORS
L6800
FERR-1000-OHM
A
59 58 54 8
=PP3V3_S0_AUDIO
1
SYNC_MASTER=AUDIO
2
PP3V3_S0_AUDIO_F 59 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
C6800 0.1UF
10V 2 20% CERM 402 59 57 56 55 54
SYNC_DATE=07/09/2008
NOTICE OF PROPRIETARY PROPERTY
0402
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT
GND_AUDIO_CODEC
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
59
1
96
A
8
6
7
2
3
4
5
1
MagSafe DC Power Jack CRITICAL
F6905 C6905 0.01UF
4
SOT-563
Vgs(max) = 20V PP18V5_DCIN_ONEWIRE
5
6
MIN_LINE_WIDTH=0.25mm MIN_NECK_WIDTH=0.20mm VOLTAGE=18.5V 10% 25V X5R 2 402
R69151
5% 1/16W MF-LF 402 2
5% 1/16W MF-LF 402 2
R69141 ONEWIRE_ESD
5
1
U6915 LM397
3
V-
100K
5% 1/16W MF-LF 402 2
D
270K
5% 1/16W MF-LF 402 2
Vth = Vdcin * (Rb / (Ra + Rb)) Vth = Vdcin / 2
5% 1/16W MF-LF 402 2
ONEWIRE_PWR_EN_L 5
G
S
270K
1
4
C6917 0.001UF
5% 1/16W MF-LF 402 2
10% 2 50V CERM 402
6
R6920 24.3K
Q6915 SSM6N15FEAPE
SMC_BC_ACOK_RC 1
S
G
C6910
SSM6N15FEAPE
1
0.001UF
2
SMC_BC_ACOK
42 43
IN
5% 1/16W MF-LF 402
C
10% 50V CERM 2 402
CRITICAL
Q6920
SYS_ONEWIRE_BILAT
4
3
D
SOT563
1K
1
2
Q6920
1% 1/16W MF-LF 2 402
R6910
SOT563
Voltage divider from DCIN ensures Q6901 Vgs is met when SYS_ONEWIRE is high or low. Q6920 used as bilateral switch to ensure SYS_ONEWIRE doesn’t drive unpowered U6990 CRITICAL
1
D
SSM6N15FEAPE
2
The chassis ground will otherwise float and can send transients onto ADAPTER_SENSE when AC is connected.
5% 1/16W MF-LF 402 2
ONEWIRE_PWR_EN_L_DIV Vgs = 11.750V @ 20V DCIN Vgs = 7.63V @ 13V DCIN R69121 330K
R69181
3
SOT563
R69161
2
CRITICAL Q6915
SSM6N15FEAPE
SOT23-5-HF 4 ONEWIRE_OVERVOLT
V+
470K 2
SOT563
1
ADAPTER_SENSE
ONEWIRE_EN
270K CRITICAL ONEWIRE_DCIN_DIV
R69111
G
5% 1/16W MF-LF 402 2
If ADAPTER_SENSE > Vth then turn off FET
100K
D6900 CRITICAL
1
270K
G 5
2
1
RCLAMP2402B
S
R6917
0.1UF
R69131
D
1
C6915 1 SC-75
C
BSS84V
1-Wire OverVoltage Protection
20% PLACEMENT_NOTE=Place near L6900 2 50V CERM 603
3
D
8 60
SYS_ONEWIRE
BI
42 43
3.425V "G3Hot" Supply Supply needs to guarantee 3.31V delivered to SMC VRef generator
R6905 60 8
=PP18V5_DCIN_CONN
1
47
D6905
HN2D01JEAPE
2
5% 1/8W MF-LF 805
SOT665
PPDCIN_S5_P3V42G3H MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm VOLTAGE=18.5V 8
1
5
3
4
PPVIN_G3H_P3V42G3H
=PPVBAT_G3H_P3V42G3H MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V
NC
2
C6990
NC
P3V42G3H_BOOST 3 VIN
1
10UF 10% 25V X5R 805
NC
J6950
2
Battery Connector
TSOT23-8 SHDN* CRITICAL
20% 6.3V X5R 402
SW BIAS
5
FB
8
7
NC
CRITICAL 33UH
P3V42G3H_SW
1
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE
PPVBAT_G3H_CONN_F MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=12.6V
3
1
2
1
R6995
61
2
1% 1/16W MF-LF 2 402
=SMBUS_BATT_SCL =SMBUS_BATT_SDA SMC_BS_ALRT_L
5 6
9
42 43
2
C6950
D6950
J6955
SC-75
10% 2 50V CERM 402
1% 1/16W MF-LF 402
CRITICAL
RCLAMP2402B
0.001UF
20% 6.3V X5R-CERM 603
Vout = 1.25V * (1 + Ra / Rb)
78171-0005 M-RT-SM
6
3
11
2
CRITICAL 1
2
200K
45 60
1
8
C6999 22UF
R6996
45 60
7
1
P3V42G3H_FB 1
4
(Switcher limit)
348K
22pF 5% 50V CERM 402
PPVBAT_G3H_CONN
B
200mA max output C6995
SM-LF
8
Vout = 3.425
1
L6950
2
=PP3V42_G3H_REG 2
CDPH4D19FHF-SM
FERR-50-OHM 1
L6995
2
GND 4
BAT-M98 F-RT-SM 10
1
0.22UF
LT3470ETS8 1
CRITICAL
C6994
U6990
2
B
6 BOOST
www.laptop-schematics.com
1
2
=PP18V5_DCIN_CONN
CRITICAL Q6910
1206-1
D
1
3
PWR PWR GND GND SIG
PP18V5_DCIN_FUSE MIN_LINE_WIDTH=1mm MIN_NECK_WIDTH=0.20mm VOLTAGE=18.5V
2
6
M-RT-SM
Q6910 restricts system load to 10K-70K window until adapter detects system and enables 16.5V output.
6AMP-24V 1
S
D
78048-0573
G
J6900
S
CRITICAL
516S0698
=PP3V42_G3H_BATT =SMBUS_BATT_SDA =SMBUS_BATT_SCL SMC_BIL_BUTTON_DB_L
1 2
GND_BATT_CHGND
3 4 5
A
8
BI
45 60
BI
45 60
OUT
7
C6954
518S0588
1
C6953
1
C6952
0.001UF
47PF
47PF
10% 50V CERM 402
5% 50V CERM 402
5% 50V CERM 402
2
2
1
1
DC-In & Battery Connectors
43
SYNC_MASTER=T18_MLB
C6955 0.001UF
2
2
SYNC_DATE=12/06/2007
NOTICE OF PROPRIETARY PROPERTY
10% 50V CERM 402
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
60
1
96
A
8
6
7 FROM ADAPTER 8
Inrush Limiter
=PPDCIN_S5_CHGR
2
3
4
5
1
Reverse-Current Protection PPDCIN_S5_CHGR_R
R70651
C7060 1
100K
1 2
Q7060
R7061
D
5% 1/16W MF-LF 2 402
5
6
7 8
8
330K
=PP3V42_G3H_CHGR
CHGR_SGATE_DIV
Q7065
6 7
D
CRITICAL CRITICAL SOI SOI HAT1128R01HAT1128R01
S G
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm 1
1
R70701
C7070
62K
5% 1/16W MF-LF 402 2
U7070
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=18.5V
5% 1/16W MF-LF 2 402
CHGR_AMON 46 61 R7075 clamps CHGR_AMON when charger is not powered to counter TL331 bias current.
1
SOT23-5 4
CHGR_SGATE
VCC
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.25 mm
GND
D
1M
5
TL331
PPDCIN_S5_INRUSH
R7074
1% 1/16W MF-LF 402 2
10% 16V 2 X5R 402
8 61
1
57.6K
0.1uF
R7066
5
4
5% 1/16W MF-LF 402 2
D
CHGR_AGATE_DIV MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm 1
3
S
10% 25V X5R 2 402
G
0.1UF
5% SOD-723-HF 1/16W 1 MF-LF 2 402
4
470K
3 D
SGATE_P0V1_VREF
3
Q7074 SSM6N15FEAPE
2
SOT563
1
R7071
6 D
Q7074 SSM6N15FEAPE
1.82K
1% 1/16W MF-LF 402 2
SOT563
G 5
4 S
AMON_CLAMP G 2
1 S
PP5V1_CHGR_VDD 61
D7040
(CHGR_DCIN)
1
R7021 10
1
R7001
95
C7015 1
10% 2 16V X5R 402
0.001UF
93
BOOT 25 UGATE 24 PHASE 23
CHGR_BOOT CHGR_UGATE CHGR_PHASE CHGR_LGATE TP_CHGR_TRKL CHGR_AMON CHGR_BMON =CHGR_ACOK
CRITICAL 4 1
LFPAK-HF
0.1UF 3
1 2 3
OUT
46
OUT
43
1UF
10% 2 25V X5R 603-1
1
C7034 1000PF
10% 2 25V X7R 402
L7030 4.7UH-10.2A PPVBAT_G3H_CHGR_REG
2
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE 46 61
C7033
CRITICAL
10% 2 25V X5R 402
OUT
1
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=12.6V CRITICAL
FDA1254F-SM
5
C7040 1
1
22UF
CRITICAL
Q7035
4
20% 25V 2 POLY-TANT CASE-D2-SM
CRITICAL
RJK0305DPB
R7050
LFPAK-HF
0.5% 1W MF 0612
152S0542
1
2 4
1 3
PPVBAT_G3H_CHGR_R
CHGR_VNEG_R
1
470PF
(CHGR_CSO_P) (CHGR_CSO_N)
10% 2 50V CERM 402
10% 25V X5R 2 603-1
10% 10V X5R 2 402
1
C7011
C7005 1
0.01UF
0.1UF
10% 16V 2 CERM 402
2
95 46
CHGR_CSO_R_P
CRITICAL
HAT1127H LFPAK-SM
10% 16V CERM 2 402
1
1
Q7056
Q7055
60
2
5
PPVBAT_G3H_FET
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=12.6V
4
1
B PPVBAT_G3H_CONN
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=12.6V
1
16V 2 X5R 402
0.1UF
10% 2 16V X5R 402
10
2
5% MF-LF 402 1/16W
BATT_POS_GATE
R7052 1
R7056 1M
C7058 0.1UF 10%
C7056
R7057 330K
95 46
CHGR_CSO_R_N
5% 1/16W MF-LF 402
(PPVBAT_G3H_CHGR_R)
1UF
10
5% 1/16W MF-LF 402
C7016
C7000 1
CRITICAL HAT1127H 3
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=12.6V
1UF
R7051
10% 2 16V X5R 402
1000PF
LFPAK-SM
C7055 1
Max Current = 8.5A (L7030 limit) f = 400 kHz
2
1% 1/16W MF-LF 402 2
0.033UF
C7041
10% 2 25V X7R 402
0.01uF
XW7000 SM
3.01K
1
0.01
C7057 1
R7016
C7042
10% 2 25V X5R 603-1
1UF
1 2 3
1
1
1
RJK0305DPB
C7035
10% 50V CERM 2 402
1
C7032
Q7030
2
0.1uF
CHGR_VCOMP_R
B
C7050
93
1
1
THRM_PAD
SIGNAL_MODEL=EMPTY
20% 25V 2 POLY-TANT CASE-D2-SM
2
93
1% 1/16W MF-LF 2 402
22UF
1
93
56.2K
C7031
5
CHGR_BGATE CHGR_DCIN
21 13 9 15 14
20% 25V 2 POLY-TANT CASE-D2-SM
0.1UF
CRITICAL 1
C7030 22UF
10% 2 25V X5R 402
CHGR_AGATE CHGR_CSI_P CHGR_CSI_N
BGATE 16 DCIN 2
LGATE (OD) TRKL* 20V/V AMON 32V/V BMON (OD) ACOK
CRITICAL 1
C7021
S
R7015
OMIT
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=18.5V
1 2 3
1
5 ICOMP 7 VCOMP 8 VNEG 18 CSOP 17 CSON
29
1% 1/16W MF-LF 402 2
CHGR_ICOMP CHGR_VCOMP CHGR_VNEG CHGR_CSO_P CHGR_CSO_N
PPDCIN_S5_FET_CHGR
G
9.31K
C
2
D
R70111
NC
10% 25V 2 X5R 402
1206
2
4
VREF = 3.2V, < 300uA CHGR_ACIN
4 VREF 3 ACIN
0.1UF
1
8AMP-24V
0.5% 1W MF 0612
5
U7000
=SMBUS_CHGR_SCL =SMBUS_CHGR_SDA
ISL6258A
BI
22 PGND
IN
45
20
19
45
C7022 1
10% 10V 2 X5R 402
VDD VDDP 12 VHST CRITICAL AGATE 1 11 SCL CSIP 28 QFN 10 SDA CSIN 27
26 6 AGND
1% 1/16W MF-LF 402 2
C7001 1 1UF
Input impedance of ~40K meets sparkitecture requirements
4 2
5% 1/16W MF-LF 402
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5.1V
10% 10V 2 X5R 402
1
30.1K
PP5V1_CHGR_VDDP
2
5% 1/16W MF-LF 402
30mA max load
1UF
Divider sets ACIN threshold at 13.07V
R7010
1
CHGR_CSI_R_N
CRITICAL
F7040
0.02
D
C7002 1
ACIN pin threshold is 3.2V, +/- 50mV
PP5V1_CHGR_VDD
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5.1V
1
1
R7020
S
61
4.7
10
3 1
CHGR_CSI_R_P
G
=PP3V42_G3H_CHGR
61 8
10% 2 16V CERM 402
1SS418
R7022
0.047UF
8
2
CRITICAL 95
C7020
=PPBUS_G3H
SOD-723-HF
2
5% 1/16W MF-LF 402
SIGNAL_MODEL=EMPTY
1
C
TO SYSTEM
NOSTUFF
(CHGR_AGATE)
www.laptop-schematics.com
R7060
3
1SS418
2
D7005
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=18.5V
1
1
2
60 9
5% MF-LF 402 1/16W
GND_BATT_CHGND
C7026 0.001UF
10% 50V 2 CERM 402
10% 25V 2 X5R 402
GND_CHGR_AGND MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V
PBus Supply & Battery Charger SYNC_MASTER=M99_MLB
A M99 1. 2. 3. 4. 5.
PART NUMBER
DESCRIPTION
REFERENCE DES
CRITICAL
353S1811
QTY 1
IC,ISL6258,BAT CHARGER,28P,4X4,QFN,L
U7000
CRITICAL
ISL6258
2S Battery Default
353S1832
1
IC,ISL6258A,BAT CHARGER,4X4MM,QFN28
U7000
CRITICAL
ISL6258A
3S Battery Default
SYNC_DATE=12/10/2007
NOTICE OF PROPRIETARY PROPERTY
differences from last sync on 12/02/07 to T18 MLB: L7030 changed from T18 MLB inductor to 152S0542. Added Q7056, C7058,R7055,R7056.. U7000 Thermal Pad is now connected to GND, not through XW. Q7060 and Q7065 changed to 376S0667. Q7055 and Q7056 changed to 376S0666.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
BOM OPTION
SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
61
1
96
A
8
6
7
10
1
1000PF
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=12.6V
C7196
10% 25V 2 X7R 402
1
0.1UF
10% 16V 2 X5R 402
=PP5V_S0_CPU_IMVP 10
D
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V
1% 1/16W MF-LF 402
C7126
10% 10V 2 X5R 402
PP3V3_S0_IMVP6_3V3
2
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V
1% 1/16W MF-LF 402
=PP1V05_S0_CPU
R7199
87 21
87 43 14 10
PM_DPRSLPVR
IN
499
1
CPU_PROCHOT_L
OUT
0
1
1
CRITICAL
C7110 1
470K
C
87 9
IN
87 9
IN
87 9
IN
87 9
IN
87 9
IN
87 9
IN
87 9
IN
87 14 10 9
IN
10
IN
10% 16V CERM 2 402
2
IMVP6_VID IMVP6_VID IMVP6_VID IMVP6_VID IMVP6_VID IMVP6_VID IMVP6_VID
87
0.01uF
402
5% 1/16W MF-LF 2 402
46
OUT
42 41 40 39 38 37
CPU_DPRSTP_L IMVP_DPRSLPVR CPU_PSI_L IMVP6_IMON
46 45 2 3
48 9
4.02K
C7105
1% 1/16W MF-LF 402 2
1
R7108
1
OUT
62
IN
26
OUT
147K
0.015UF
1% 1/16W MF-LF 2 402
10% 16V X7R 2 402
62
22
1
0.001UF
R7113
62
1K
62
10% 50V 2 CERM 402
1% 1/16W MF-LF 402 2
IMVP6_VDIFF_RC
VR_PWRGD_CLKEN_L IMVP_VR_ON_R VR_PWRGOOD_DELAY IMVP6_VR_TT_L IMVP6_NTC (GND_IMVP6_SGND) IMVP6_SOFT
47
IMVP6_RBIAS (GND_IMVP6_SGND) IMVP6_VDIFF
4
44 1 5 6
7
VDD
36
62
BOOT2 26
62
BOOT1
VID6 VID5
U7100
VID4
13
62 62
IMVP6_FB2 IMVP6_FB IMVP6_COMP IMVP6_VW
12 11 10 9
C7127
IMVP6_BOOT1 IMVP6_BOOT2
VID3 VID2 VID1 VID0
DPRSTP*
35
62
IMVP6_UGATE1
PHASE1 34
62
IMVP6_PHASE1
LGATE1 32
62
IMVP6_LGATE1
UGATE1
PGND1
33
C7114
IMON
62
IMVP6_ISEN1
27
62
IMVP6_UGATE2
PHASE2 28
62
IMVP6_PHASE2
LGATE2 30
62
IMVP6_LGATE2
UGATE2
(PGD_IN) (ISL9504A)
CLK_EN* VR_ON
XW7103 SM 1
Q7101
C7156 1 1000PF
10% 25V X7R 2 402
1
IMVP6_VO1
62
1
C7115
R7100
20%
1
1
2
10% 10V CERM 402
(IMVP6_ISEN1)
C
PGND2 29
VR_TT* ISEN2
23
(GND) 62
5
IMVP6_ISEN2
CRITICAL
NTC VSUM SOFT
19 8
62
VO 18
RBIAS
16
IMVP6_VSUM IMVP6_OCSET IMVP6_VO IMVP6_DROOP
62
IMVP6_DFB
RTN
OUT
62
NO STUFF
1
1
(IMVP6_PHASE2)
2
XW7101 SM
5
R7118
1
1K
1
R7116
C7129
13.3K
180pF
1% 1/16W MF-LF 2 402
TPAD
0.36UH-30A-1.05MOHM PCMC104T-SM
1
10% 16V CERM 2 402
NC
L7101
1 2 3
10% 50V CERM 2 402
1% 1/16W MF-LF 402
C7131
CRITICAL
C7116 1 0.001uF
3.92K2
15
VW
49
62
1
VSEN 14
COMP
OUT
R7117
FB2 FB
RJK0305DPB LFPAK-HF
VDIFF 17
Q7102
4
1% 1/16W MF-LF 2 402
5% 2 50V CERM 402
1
CRITICAL
Q7103
4
XW7102 SM
2
2
IMVP6_VSUM2
62
1
1
LFPAK-HF
C7134
R7107
0.068UF
1
R7130
11K
1 2 3
2.61K
1% 1/16W MF-LF 2 402
R7105
1% 1/16W MF-LF 402 2
1
1
10% 6.3V CERM-X5R 2 402
1% 1/16W MF-LF 2 402
B
0.22UF 1
2
10% 10V CERM 402
1% 1/10W MF-LF 2 603
10KOHM-5%
0.22UF
6.81K
C7104
3.65K
R7131
C7128 1
R7110
2
5% 1/16W MF-LF 2 402
R7106
CRITICAL 1
10K
1% 1/16W MF-LF 402
1
(IMVP6_VW)
10% 25V 2 X7R 402
1
1
R7115
1000PF
IMVP6_VO2
62
(IMVP6_VO)
SIGNAL_MODEL=EMPTY
C7157 1
1
RJK0328DPB
IMVP6_VO_R
10% 50V CERM 2 402
0.22UF
2
1% 1/10W MF-LF 2 603
10% 50V X7R-CERM 2 402
0.001UF
5% 1/16W MF-LF 2 402
3.65K
402
1
10K
1% 1/16W MF-LF 402
603
2 10V CERM
C7107
C7103
R7101
MIN_LINE_WIDTH=0.50 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=0V
1% 1/16W MF-LF 402 2
2
IMVP6_VSUM1
62
2 25V X5R
GND_IMVP6_SGND
97.6K
XW7104 SM
2
RJK0328DPB
PGOOD
21
R71141
2
3V3
GND
IMVP6_COMP_RC
1
8
44A MAX CURRENT
0.36UH-30A-1.05MOHM (IMVP6_PHASE1)
1
220PF
10% 2 50V CERM 402
1 2 3
0.22UF
20% 25V 2 X5R 603
C7113 1
470PF
L7100
PSI*
1K 1% 1/16W MF-LF 2 402
1
10%
1
D =PPVCORE_S0_CPU_REG
CRITICAL
(GND)
ISEN1 24
DPRSLPVR
1
0.22UF
0.01UF
(IMVP6_FB)
B
1UF
LFPAK-HF
4
QFN
R7109
255
1% 1/16W MF-LF 402 2
10% 2 25V X5R 603-1
RJK0305DPB
CRITICAL
1
R7111
1
20% 25V 2 POLY-TANT CASE-D2-SM
22UF
Q7100
5
PVCC
DROOP
25
1
PSI* Operation Mode 1 2-Phase CCM 0 1-Phase CCM 1 1-Phase DCM 0 1-Phase DCM
1 2 3
DFB
C7106
5
C7154
C7153 1
31
OCSET 62
62
1
10% 25V 2 X7R 402
R7104
43
IMVP6_NTC_R
R71271
20% 25V 2 POLY-TANT CASE-D2-SM
1000PF
LFPAK-HF
VIN
2
C7152 1
1
R7198
(IMVP6_NTC)
R7126
10K
20
5% 1/16W MF-LF 402
LAYOUT NOTE: Place R7126 in hot spot of reg circuit.
R7197
2
1% 1/16W MF-LF 402
CRITICAL
C7155 1 22UF
4
20% 6.3V 2 X5R-CERM 402
1
10% 16V 2 X5R 402
5% 1/16W MF-LF 2 402
R7119
10% 2 25V X5R 603-1
4.7UF
1
0.1uF
68
20% 25V 2 POLY-TANT CASE-D2-SM
1UF
PCMC104T-SM
C7130
1
1
22UF
C7135
1
ISL9504BCRZ
13 12 11 10 8 6
10
1
1
1UF
R7121 =PP3V3_S0_IMVP
DPRSLPVR DPRSTP* 0 1 1 0 1 0 1 0
PP5V_S0_IMVP6_VDD
2
CRITICAL
C7109
C7117 1
CRITICAL
R7112 1
These caps are for Q7102
CRITICAL
C7108 1
PPVIN_S5_IMVP6_VIN
2
1% 1/16W MF-LF 402
8
1
These caps are for Q7100
=PPVIN_S5_CPU_IMVP
R7120
8
2
3
4
5
www.laptop-schematics.com
8
0603-LF
(IMVP6_ISEN2)
2
(IMVP6_VSUM)
(IMVP6_COMP)
Place R7131 Between L7100,L7101 and CPU
(IMVP6_VO)
R7122 87 62
87 62
C7121 0.22UF
R7160 42
A
62
IMVP_VR_ON
IMVP6_OCSET
1
0
2
IMVP_VR_ON_R
XW7100 SM
62
1
5% 1/16W MF-LF 402
MIN_LINE_WIDTH=0.25 MM
1
20% 6.3V 2 X5R 402
C7133 0.01uF
1
10% 16V CERM 2 402
1
IMVP6_VSEN_P
IMVP6_VSEN_N NO STUFF
C7132 0.01uF
1
0
5% 1/16W MF-LF 402
2
CPU_VCCSENSE_P
IN
11 87
CPU_VCCSENSE_N
IN
11 87
R7123 0
1
2
5% 1/16W MF-LF 402
10% 2 16V CERM 402
IMVP6 CPU VCore Regulator
2
SYNC_MASTER=M87_MLB
MIN_NECK_WIDTH=0.20 MM
SYNC_DATE=10/17/2007
NOTICE OF PROPRIETARY PROPERTY 62 62 62 62 62 62 62 62 62 62
IMVP6_VO IMVP6_DROOP IMVP6_DFB IMVP6_SOFT IMVP6_RBIAS IMVP6_VDIFF IMVP6_FB2 IMVP6_FB IMVP6_COMP IMVP6_VW
MIN_LINE_WIDTH=0.25 MIN_LINE_WIDTH=0.25 MIN_LINE_WIDTH=0.25 MIN_LINE_WIDTH=0.25 MIN_LINE_WIDTH=0.25 MIN_LINE_WIDTH=0.25 MIN_LINE_WIDTH=0.25 MIN_LINE_WIDTH=0.25 MIN_LINE_WIDTH=0.25 MIN_LINE_WIDTH=0.25
MM MM MM MM MM MM MM MM MM MM
MIN_NECK_WIDTH=0.20 MIN_NECK_WIDTH=0.20 MIN_NECK_WIDTH=0.20 MIN_NECK_WIDTH=0.20 MIN_NECK_WIDTH=0.20 MIN_NECK_WIDTH=0.20 MIN_NECK_WIDTH=0.20 MIN_NECK_WIDTH=0.20 MIN_NECK_WIDTH=0.20 MIN_NECK_WIDTH=0.20
MM MM MM MM MM MM MM MM MM MM
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING 62 62 62 62 62 62 62 87 62
8
7
IMVP6_PHASE1 IMVP6_BOOT1 IMVP6_UGATE1 IMVP6_LGATE1 IMVP6_ISEN1 IMVP6_VSUM1 IMVP6_VO1 IMVP6_VSEN_P
6
MIN_LINE_WIDTH=1.5 MM MIN_LINE_WIDTH=0.25 MM MIN_LINE_WIDTH=0.5 MM MIN_LINE_WIDTH=0.5 MM MIN_LINE_WIDTH=0.25 MM MIN_LINE_WIDTH=0.25 MM MIN_LINE_WIDTH=0.25 MM MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM
5
62 62 62 62 62 62 62
I849
87 62
IMVP6_PHASE2 IMVP6_BOOT2 IMVP6_UGATE2 IMVP6_LGATE2 IMVP6_ISEN2 IMVP6_VSUM2 IMVP6_VO2 IMVP6_VSEN_N
4
MIN_LINE_WIDTH=1.5 MM MIN_LINE_WIDTH=0.25 MM MIN_LINE_WIDTH=0.5 MM MIN_LINE_WIDTH=0.5 MM MIN_LINE_WIDTH=0.25 MM MIN_LINE_WIDTH=0.25 MM MIN_LINE_WIDTH=0.25 MM MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM
3
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
I848
2
REV.
051-7546
A.0.0 OF
62
1
96
A
8
6
7
2
3
4
5
1
8
=PPVIN_S5_P5VP3V3 CRITICAL
R7264 2
CRITICAL 1
1
C7240
P5VP3V3_VREG5
C7241
P5VP3V3_VREG3
2 P5VS5_VBST_R
5 1
CRITICAL
C
0.1UF
Q7220
f=365KHz
2
4
RJK0305DPB 8
C7224
0
1
C7200
5% 1/16W MF-LF 402
1
C7203
2
20% 6.3V X5R 603
10% 25V X5R 603-1
10% 50V X7R 603-1
VIN 14 SKIPSEL
L7220
3 2 1
1
1
330UF 20% 6.3V 2 POLY-TANT CASE-D3L-SM1
2
IHLP2525CZ-SM1
CRITICAL
C7252
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
2.2UH-14A
(Q7220 limit) C7250
1
20% 10V X5R 805
5
NO STUFF1
R7222
10UF
10 5% 1/16W MF-LF 402 2
2
GATE_NODE=TRUE
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
Q7225
2
1UF
P5VS5_DRVL
C7264
20% 6.3V X5R 603
10% 50V X7R 603-1
P5VS5_ENTRIP
1 ENTRIP1
1
3 2 1
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
P3V3S5_DRVL
2
5.5A max output
L7260
(L7260 limit)
Q1 10
SW 8
1
2 IHLP2525CZ
NO STUFF1
CRITICAL
R7262
1
10
C7290
1
10UF
5% 1/16W MF-LF 402 2
2
C7292 150UF
20% 6.3V X5R 603
20% 2 6.3V POLY-TANT CASE-B2-SM
P3V3S5_RC
7
6
5
C7262 100PF 5% 50V CERM 402
NO STUFF
GND THRM_PAD
1
C7208
1
220PF
PLACEMENT_NOTE=Place XW7220 next to L7220.
2
PP5V_S5_REG_XW
8
Vout = 3.3V
NO STUFF1
25
1
1% 1/16W MF-LF 402
=PP3V3_S5_REG
P3V3S5_ENTRIP
EN0 13 15
SM
f=460KHz
2
Q2
PGOOD 23 75K
3
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
P3V3S5_VFB
ENTRIP2 6
R7200
4
4.7UH-5.5A
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
VCLK 18
2
9
CRITICAL
(P3V3S5_V02)
VFB2 5
100PF
Q7260 FDMS9600S
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
2 VFB1
CRITICAL 2
MLP
P3V3S5_LL
VO2 7
P5VS5_VFB
1
0.1UF
P3V3S5_DRVH
DRVL2 12
24 VO1
10% 25V X5R 603-1
10UF
SWITCH_NODE=TRUE
19 DRVL1
C7281
P3V3S5_VBST
LL2 11
C7222
XW7220
1
2
1
DRVH2 10
NO STUFF1 5% 50V CERM 402
2
2
GATE_NODE=TRUE
LFPAK-HF P5VS5_RC
2
20% 25V POLY-TANT CASE-D2-SM
C7205
GATE_NODE=TRUE
(P5VS5_VO1)
4
RJK0301DPB
1
1
VBST2 9
20 LL1
P5VS5_LL
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
10% 10V CERM 402
VREG5 17
21 DRVH1 TPS51125
P5VS5_DRVH
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
CRITICAL
1
22UF
2
0.22UF
VREG3 8
U7201 QFN
22 VBST1
P5VS5_VBST
CRITICAL
C7201
VREF
4 TONSEL
Vout = 5.0V 6A max output
1
10UF
1UF
LFPAK-HF
=PP5V_S3_REG
C7280 P3V3S5_VBST_R
P5VP3V3_VREF
R7224
3
2
2
10% 25V X5R 603-1
16
20% 25V POLY-TANT CASE-D2-SM
1
5% 1/16W MF-LF 402
1UF
22UF
0
2
XW7260 SM
75K
5% 25V CERM 402 2
PLACEMENT_NOTE=Place XW7200 next to U7200 pin 15.
2
R7206
1
PLACEMENT_NOTE=Place XW7260 next to L7260.
1% 1/16W MF-LF 402
PP3V3_S5_REG_XW PATH=I621
PATH=I623
1
1
R7260
XW7200
R7220
6.49K
SM
15K
GND_P5VP3V3_SGND
5% 1/16W MF-LF 2 402
1
1% 1/16W MF-LF
2
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V
2 402
B
R7261
R7221
One master PGOOD for both 5V and 3V3
10K 1% 1/16W MF-LF
68
10K 1% 1/16W MF-LF
P5V3V3_PGOOD
OUT
2 402
2 402
Q7210
D 6
SSM6N15FEAPE SOT563
68 8
=PP3V42_G3H_PWRCTL 2 1
G
S 1
Q7211
R7210
2
ALTERNATE FOR PART NUMBER
376S0651
376S0668
BOM OPTION
REF DES
COMMENTS:
ALL
FET FDM8678S alternate to Si7108
SOT563
5% 1/16W MF-LF 402
5
P5VS3_EN_L
TABLE_ALT_HEAD
PART NUMBER
Q7210
TABLE_ALT_ITEM
D 3
SSM6N15FEAPE
10K
G
S 4
D 3
SSM6N15FEAPE SOT563
TABLE_ALT_ITEM
376S0652
376S0669
ALL
FET FDM8676 alternate to Si7110
152S0778
152S0693
ALL
4.7uH inductor Cyntec a;ternate to MagLayers
68
P3V3S5_EN_L
M99 1. 2. 3. 4.
TABLE_ALT_ITEM
5
68
G
S 4
=P5VS3_EN
differences from last sync on 11/01/07 to M88 MLB: L7260 changed from M88 MLB inductors to 152S0693. Q7220 changed to 372S0512. Q7225 changed to 376S0511. U7200 changed to 353S2087. Added R7200, R7220,R7221, R7260,R7261, C7201.
5V / 3.3V Power Supply
A
SYNC_MASTER=M99_MLB
SYNC_DATE=01/09/2008
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
.
SIZE
DRAWING NUMBER
D APPLE INC.
7
6
5
4
3
2
REV.
051-7546
SCALE
SHT NONE
8
C
B
1 1
www.laptop-schematics.com
D
D
A.0.0 OF
63
1
96
A
8
6
7
2
3
4
5
1
D
D
=PPVIN_S0_DDRREG_LDO
1
C7355
8
www.laptop-schematics.com
8
=PPVIN_S3_DDRREG
10UF
20% 2 6.3V X5R 603 8
CRITICAL
4.7
1
PP5V_S3_DDRREG_V5FILT
2
C7332
C7331 1
1
20% 25V 2 POLY-TANT CASE-D2-SM
20% 25V 2 POLY-TANT CASE-D2-SM
10% 2 25V X5R 603-1
22UF
R7305
=PP5V_S3_DDRREG
CRITICAL
C7330 1
22UF
1
1UF
C7333 1000PF
10% 2 25V X7R 402
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V
5% 1/16W MF-LF 402
5
CRITICAL
10% 10V 2 X5R 402
V5IN
V5FILT
8
TPS51116
=PPVTT_S3_DDR_BUF
10mA max load
=PPVTT_S0_DDR_LDO
Vout XW7360 SM 1
CRITICAL
2
22UF
20% 6.3V X5R-CERM 2 603
SYM (2 OF 2)
1
LL 20
24 VTT
= VTTREF
DRVL 19
DDRREG_VTTSNS
CRITICAL
1
DRVH 21
QFN
5 VTTREF
Vout = VDDQSNS/2
MIN_LINE_WIDTH=2 mm MIN_NECK_WIDTH=0.2 mm
C7360
VBST 22
U7300
2 VTTSNS
NC NC
C7361 22UF
CS 16
7 NC0 12 NC1
20% 2 6.3V X5R-CERM 603
VDDQSET 9
VTTGND
THRM_PAD GND
DDRREG_VBST
(DDRREG_VBST)
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
DDRREG_DRVH GATE_NODE=TRUE
DDRREG_LL SWITCH_NODE=TRUE
DDRREG_DRVL GATE_NODE=TRUE
C
CRITICAL
C7325
1 2 3
1
L7330
1.0UH-13A-5.6MOHM
2
1
2 PCMB065T-SM
10% 50V X7R 603-1
CRITICAL 1
5
330UF
CRITICAL
(DDRREG_LL)
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
Q7335
4
(DDRREG_DRVL)
RJK0301DPB
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
C7340
LFPAK-HF
20% 2 2.5V POLY-TANT CASE-C2-SM
CRITICAL
C7341 1 330UF
DDRREG_CS
20% 2.5V POLY-TANT 2 CASE-C2-SM
DDRREG_FB
=PPDDR_S3_REG 8 Vout = 1.50V or 1.80V 15A max output (Q7335 limit) f = 400 kHz
1
C7345 10UF
PLACEMENT_NOTE=Place next to Q7335
(DDRREG_CSGND)
1
NO STUFF
2
C7320 1 100PF
5% 50V CERM 2 402
(DDRREG_VDDQSNS)
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm 2
(DDRREG_FB)
XW7300 SM
10% 16V 2 X5R 402
2
XW7345 SM PLACEMENT_NOTE=Place next to C7345 1
XW7335 SM
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm
C7350 1
C7346
10% 25V 2 X7R 402
1 2 3
DDRREG_CSGND
0.033UF
1
1000PF
20% 2 6.3V X5R 603
PGND CS_GND 18
27 8
LFPAK-HF
0.1UF
3
IN OUT
1% 1/16W MF-LF 402 2
MODE 4
10 S3 VTT Enable 11 S5 VDDQ/VTTREF Enable 13 PGOOD VDDQ PGOOD
25
68 68
=DDRVTT_EN =DDRREG_EN DDRREG_PGOOD
1
IN
RJK0305DPB
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
10K
VDDQSNS 8
CRITICAL 69 9
R73101
Q7330
4
(DDRREG_DRVH)
VLDOIN
6 COMP
C
DDRREG_VDDQSNS
23
1UF
17
C7305
20% 6.3V 2 CERM 603
14
4.7UF
1
15
C7300
1
Vout = 0.75V * (1 + Ra / Rb)
1
1
R7320 15.0K
1% 1/16W MF-LF 2 402
1
R7321 15.0K
1% 1/16W MF-LF 2 402
B
B
GND_DDRREG_SGND MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V
1.5V DDR3 Supply SYNC_MASTER=M99_MLB
A
SYNC_DATE=12/13/2007
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
64
1
96
A
8
6
7
8
2
3
4
5
1
=PPVIN_S0_P5VRTS0_MCPCORE CRITICAL
C7510 1
D
1
C7511
D
5
1UF
22UF
10% 2 25V X5RCRITICAL 603-1
20% 25V POLY-TANT 2 CASE-D2-SM
D
Q7510
SI7110DN
G
PWRPK-1212-8-HF
4
S 2
1
(P5VRTS0_UGATE)
CRITICAL
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM GATE_NODE=TRUE
R75001
C7501 1
5% 1/16W MF-LF 402 2
10% 10V X5R 2 402-1
4.7
5
CRITICAL
PVIN_P5VRTS0_MCPCORE
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM GATE_NODE=TRUE MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM 1
CRITICAL
C
10% 2 16V X7R 603
L7510 2.2UH-14A
Vout = 5.03V 5A max output (Q7510 limit?) f = 400 kHz
1
2
P5VRTS0_BOOT P5VRTS0_UGATE P5VRTS0_PHASE P5VRTS0_LGATE
(P5VRTS0_PHASE) MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM SWITCH_NODE=TRUE
IHLP2525CZ-SM1
(=PP5V_RTS0_REG)
(=P5V_RTS0_EN) 1
2
C7516 10UF
2
20% 10V X5R 805
XW7516 SM
CRITICAL
C7515
0.22UF
P5V_RTS0_FB P5V_RTS0_ILIM
1PLACEMENT_NOTE=Place next to C7516
1
P5VRTS0_VSNS
330UF 20% 6.3V 2 POLY-TANT CASE-D3L-SM1
NO STUFF 1
R7520
NO STUFF
61.9K
C7520 1
1% 1/16W MF-LF 2 402
5% 50V CERM 2 402
6 17 15 16 18 10 14 9 11 12 29 4 20 2
LDO LDOREFIN VIN BOOT1 CRITICAL BOOT2 UGATE1 UGATE2 PHASE1 ISL6236 PHASE2 LGATE2 LGATE1 QFN OUT1 OUT2 EN1 EN2 BYP FB1 REFIN2 ILIM1 ILIM2 SKIP* EN_LDO REF SECFB POK1 TON POK2
U7500
THRM_PAD GND
100PF
10% 10V 2 X5R 402-1
PVCC VCC VREF3
33
8
C7514
C7503 1
1UF
5
10% 25V 2 X5R 805
(P5VRTS0_BOOT)
1
21
2
7 8 24 26 25 23 30 27
1UF
10% 10V 2 X5R 402-1
Max load 100mA PP5V_S0_MCPREG_LDO VOLTAGE=5V (SGND) MCPCORES0_BOOT MCPCORES0_UGATE MCPCORES0_PHASE MCPCORES0_LGATE (=PPMCPCORE_S0_REG)
1
4.7UF
R7514
0
100K
5% 1/16W MF-LF 2 402
0.22UF
1
1% 1/16W MF-LF 2 402
B
68
OUT
68
IN
IN
21
IN
21
IN
0.001
L7560
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM SWITCH_NODE=TRUE
1
2
PPMCPCORE_ISENSE
MPL104-SM
5
1 3
=PPMCPCORE_S0_REG
2 4
MCPCOREISNS_P MCPCOREISNS_N 95 47
95 47
Vout = See below
1% 1W MF 1206
0.6UH-30A-1.5MOHM
(MCPCORES0_PHASE)
C7566
1
10UF
20% 4V X5R 2 603
Q7565
4 (MCPCORES0_LGATE)
CRITICAL 1
LFPAK-HF 1
PP2V_S0_MCPREG_REF VOLTAGE=2V
C7567 10UF
Max load 50uA
MCP_PROD
20% 2 4V X5R 603
1 2 3
R75701
1
C7530
R75641 100K
0.1UF
1% 1/16W MF-LF 402 2
20% 2 10V CERM 402
GND_MCPREG_SGND
R75711 54.9K
0.1% 1/16W MF 402 2
=P5V_RTS0_EN MCPCORES0_PGOOD P5V_RTS0_PGOOD =MCPCORES0_EN
Vout = 2.0V * Req / (Ra + Req) Req = Rb || Rc || Rd || Re
1
330UF
C7568 330UF
20% 2 2.5V POLY-TANT CASE-C2-SM
1
20% 2 2.5V POLY-TANT CASE-C2-SM
C7569 1000PF 10%
2 25V X7R
402
MCP_PROD 1
MCP_PROD
1 C7590 R7580 475K
0.01UF
10% 16V 2 CERM 402
Q7580 SSM6N15FEAPE
1
R7581
R7582
237K
110K
0.1% 1/16W MF 2 402
D 3
0.1% 1/16W MF 2 402
MCP_VID1_L
Q7580
D 6
SSM6N15FEAPE
SOT563
2 G
MCP_VID2_L
Q7582
D 3
SSM6N15FEAPE
SOT563
S 4
MCP_PROD
1
0.1% 1/16W MF 2 402
MCP_VID0_L
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0V
CRITICAL
C7565
0.1% 1/16W MF 402 2
2
8
Max Current: 25A? (Q7560 Limit) f = 300 kHz
RJK0328DPB
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE
5 G
21
R5425
CRITICAL
5% 10V CERM-X7R 2 603
48.7K
Vout = 0.7V * (1 + Ra / Rb) IN
1 2 3
C7564 1
MCPCORES0_REFIN MCPCORES0_ILIM
PGND
XW7500 SM
1
R7521
OUT
LFPAK-HF
1
68
RJK0305DPB
20% 2 6.3V X5R-CERM 402
MCP_PROD
68
Q7560
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE
C7502
CRITICAL
32 31 1 13 28
1UF
CRITICAL
C7504 1
10UF
C7561
10% 25V 2 X5R 603-1
20% 25V 2 POLY-TANT CASE-D2-SM
(MCPCORES0_UGATE) 4
22
S
C7500 1
1
22UF
5
PP3V3_S0_MCP_VREF
3
(P5VRTS0_LGATE)
19
G
PWRPK-1212-8-HF
4
C7560 1
10% 25V 2 X7R 402
(Internal 10-ohm path from PVCC to VCC) PP5V_S0_MCPREG_VCC MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V
SI7108DN
3
C7563 1000PF
D
Q7511
=PP5V_RT_REG
1
1UF
SOT563
S 1
5 G
MCP79 Rev A01 requires higher core & analog voltage
A
QTY
DESCRIPTION
REFERENCE DES
114S0382
1
RES,MTL FILM,1/16W,48.7K,1,0402,SMD,LF
R7570
MCP_A01
114S0400
1
RES,MTL FILM,1/16W,76.8K,1,0402,SMD,LF
R7571
MCP_A01
114S0482
1
RES,MTL FILM,1/16W,523K,1,0402,SMD,LF
R7580
MCP_A01
114S0453
1
RES,MTL FILM,1/16W,267K,1,0402,SMD,LF
R7581
MCP_A01
114S0422
1
RES,MTL FILM,1/16W,130K,1,0402,SMD,LF
R7582
MCP_A01
114S0373
1
RES,MTL FILM,1/16W,40.2K,1,0402,SMD,LF
R7570
MCP_A01Q
114S0404
1
RES,MTL FILM,1/16W,84.5K,1,0402,SMD,LF
R7571
MCP_A01Q
114S0458 114S0447 114S0411
1 1 1
RES,MTL FILM,1/16W,301K,1,0402,SMD,LF RES,MTL FILM,1/16W,237K,1,0402,SMD,LF RES,MTL FILM,1/16W,100K,1,0402,SMD,LF
CRITICAL
BOM OPTION
R7580
MCP_A01Q
R7581
MCP_A01Q
R7582
MCP_A01Q
VID 000 001 010 011 100 101 110 111
Rev A01 Voltage
Production Voltage MCP Target
+1.224V +1.159V +1.101V +1.049V +0.995V +0.952V +0.913V +0.876V
+1.060V +0.994V +0.937V +0.885V +0.830V +0.789V +0.752V +0.719V
+1.05V +1.00V +0.95V +0.90V +0.85V +0.80V +0.75V +0.70V
1.05V / MCP Core Regulator SYNC_MASTER=M99_MLB
SYNC_DATE=01/08/2008
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
7
6
5
4
3
2
REV.
051-7546
SCALE
SHT NONE
8
C
B
S 4
MCP_VID MCP_VID MCP_VID
PART NUMBER
www.laptop-schematics.com
3
A.0.0 OF
65
1
96
A
8
6
7
2
3
4
5
1
D
8
www.laptop-schematics.com
D
=PPVIN_S0_CPUVTTS0 CRITICAL 1
C7690 1
C7695 1UF
22UF
10% 2 25V X5R 603-1
20% 25V POLY-TANT 2 CASE-D2-SM
CRITICAL
Q7660 FDMS9600S
8
9 4 3 2
MLP
=PP5V_S0_CPUVTTS0
1
C7601 1 2.2UF
C
10% 16V 2 X5R 603
68
68
=CPUVTTS0_EN
IN
CPUVTTS0_PGOOD
OUT
(=PPCPUVTT_S0_REG) CPUVTTS0_VFB CPUVTTS0_TRIP
R7679
V5FILT
1
10% 2 10V X5R 402
U7600 TPS51117RGY_QFN14 SYM (2 OF 2) QFN
1 EN_PSV 6 PGOOD
VBST 14
CPUVTTS0_VBST
3 VOUT
DRVH 13
CPUVTTS0_DRVH
5 VFB
GATE_NODE=TRUE
CPUVTTS0_LL
LL 12
SWITCH_NODE=TRUE
CPUVTTS0_DRVL
DRVL 9 THRM_PAD
7
GND
C7680
CPUVTTS0_TON
TON 2
11 TRIP
1% 1/16W MF-LF 402 2
1UF
V5DRV
CRITICAL
GATE_NODE=TRUE
PGND
Q1
165K
C7600
10 SW
8
1
PPCPUFSB_ISNS
1 3
=PPCPUVTT_S0_REG 2 4
1
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM
C7665 10UF
Q2
95 47
1
8
Vout = 1.052V 6A max output (Q7660 limit?) f = 360 kHz
20% 6.3V 2 X5R 603
1V05CPU_P
C
CRITICAL
10% 50V X7R 2 603-1
95 47
7 6 5
C7660 1
1V05CPU_N
330UF
2
20% 2.0V 2 POLY-TANT B2-SM
XW7665 SM 1
CPUVTTS0_VSNS 1
R7670 8.06K
R7685
1% 1/16W MF-LF 2 402
6.34K
XW7600 SM 1
2
IHLP2525CZ-SM1
0.1UF
1
1% 1/16W MF-LF 2 402
1% 1/4W MF 1206
2.2UH-14A
1
10
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V
0.002
L7660
PP5V_S0_CPUVTTS0_V5FILT
8
1% 1/16W MF-LF 402
2
15
200
4
1
R5435
CRITICAL
R7601
NO STUFF
PLACEMENT_NOTE=Place XW7665 next to C7665
C7670 1 100PF
5% 50V CERM 2 402
(GND)
2
1
R7671 20.0K
1% 1/16W MF-LF 2 402
GND_CPUVTTS0_SGND MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V
B
Vout = 0.75V * (1 + Ra / Rb)
(CPUVTTS0_VFB)
B
(=PPCPUVTT_S0_REG)
CPU VTT Power Supply SYNC_MASTER=M99_MLB
A
SYNC_DATE=12/14/2007
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
M99 differences from last sync on 12/03/07 to T18 MLB: 1. Tied THERMAL_PAD to PGND. GND and THERMAL_PAD disconnected.
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
66
1
96
A
8
6
7
2
3
4
5
1
1.8V S0 Switcher / 1.0VFW SWITCHER S5 power required for output discharge feature
D
D =PP3V3_S3_P1V8S0
C7700
CRITICAL
1
L7780
2.2UF
2.2UH
20% 6.3V CERM 2 402-LF
1
P1V0FW_SW MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE
=PP1V0_FW_REG 2
CPL2512-SM
C7782 1 10PF
3
5% 50V CERM 2 402
VIN
LTC3547
GND 5
4.7UF
20% 2 4V X5R 402
1
280K
RUN1 2 RUN2 7
THRML PAD
1% 1/16W MF-LF 2 402
R7783
SW1 4 SW2 6
9
1 VFB1 8 VFB2
187K
P1V0FW_VFB
U7700 DFN-HF
CRITICAL
1% 1/16W MF-LF 2 402
CRITICAL
L7700 2.2UH
P1V8S0_LX
=PP1V8_S0_REG
1
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE
2 CPL2512-SM
C7701 1
1
R7700
10PF
C
5% 50V CERM 2 402
562K
1% 1/16W MF-LF 2 402
P1V8S0_VFB
1
R7701
=P1V8S0_EN 8
1.8V S0 Switcher
C
INPUT RAIL IS 3.3V S0
=PP3V3_GPU_P1V8S0
8
20% 4V 2 X5R 402
1 IN
8
Vout = 1.816V 0.3A max output (Switcher limit) f = 1.6 MHz C7705 4.7UF
68
8
Vout = 1.001V 300mA max output (Switcher limit) f = 2.25 MHz 1 C7785
1 R7782
www.laptop-schematics.com
8
280K
C7760
=PP3V3_FW_P1V0FW
1
1
10uF
1% 1/16W MF-LF 2 402
20% 6.3V X5R 603
CRITICAL
L7760
U7760
10UH-0.55A-330MOHM PCAA031B-SM MAX CURRENT = 300MA
TPS62202 4
=P1V8FB_EN
83 82 68
Vout = 0.6V * (1 + Ra/Rb)
CRITICAL
VI 2
3
FB EN
SOT23-5
SW 5
P1V8GPU_SW
1
2
GND
=PP1V8_GPUIFPX_REG C7762
2
8
1
10uF 67 8
20% 6.3V X5R 603
=PPVIN_S0_P1V05S5
MCP 1.05V AUXC Supply
5
1
C7775 1UF
10% 2 25V X5R 603-1
D
4
CRITICAL
Q7770 SI7110DN
G
PWRPK-1212-8-HF
CRITICAL
S
P5V_P1V05S5_V5FILT
R7751
B
1 67 8
=PPVIN_S0_P1V05S5 1
4.7
2
5% 1/16W MF-LF 402
C7752
C7751
1UF
12 PVCC
1
P1V05_S5_FSET 68
38.3K
10% 16V CERM 2 402
2 VCC
1
C7750
ISL6269 QFN UG 14
P1V05S5_DRVH GATE_NODE=TRUE
68
IN
OUT
=P1V05S5_EN P1V05_S5_PGOOD
4 3 16 5
BOOT 13 PHASE 15 ISEN 9
EN FCCM PGOOD COMP
LG 11
P1V05S5_VFB
R7753 C7755 33PF
1
49.9K
1
6 FB
P1V05S5_VBST P1V05S5_LL SWITCH_NODE=TRUE
0.1UF MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM
CRITICAL
2
Q7771
XW7775 SM
SI7108DN
G
PWRPK-1212-8-HF
1
5% 50V CERM 2 402
4.7UF
20% 2 4V X5R 402
CRITICAL 20% 2.0V 2 POLY-TANT B2-SM
P1V05S5_VSNS
R7780 3.74K
1% 1/16W MF-LF 2 402
(GND)
R7781
1
2
4.42K
XW7750 SM
10% 50V CERM 2 402
Vout = 1.052V 5A max output (L7770 limit) f = 400 kHz
C7776
1 THRML PAD 17
470PF
1
1
330UF
2 3
10% 25V X5R 2 402
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM
8 VO
C7754 1
B
8
C7771 1
S
P1V05S5_DRVL GATE_NODE=TRUE
PGND 10
P1V05S5_COMP_R
A
D
4
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM
=PP1V05_S5_MCP
5
1% 1/16W MF-LF 402 2
2.2UF
7 FSET
P1V05_S5_COMP
1% 1/16W MF-LF 2 402
2.43K
10% 2 16V X5R 603
PLACEMENT_NOTE=Place XW7775 next to C7775
2 PCMB053T
C7770 1
R7752
0.01UF
R77791
U7750
10% 16V 2 X5R 603 1 VIN
C7753 1
1.5UH-6.0A 1
2.2UF
1
L7770
2 3
P5V_P1V05S5
10% 2 25V X5R 603-1
1% 1/16W MF-LF 2 402
1
P1V05S5_ISEN MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V
2
Misc Power Supplies
1% 1/16W MF-LF 2 402
1
SYNC_MASTER=M99_MLB
GND_P1V05S5_SGND
SYNC_DATE=12/14/2007
NOTICE OF PROPRIETARY PROPERTY
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
Vout = 0.6V * (1 + Ra / Rb)
(P1V05S5_VFB)
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
(=PP1V05_S5_REG)
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
67
1
96
A
6
7
State
SMC_PM_G2_ENABLE
PM_SLP_S4_L
Run (S0)
1
1
1
Sleep (S3)
1
1
0
Soft-Off (S5)
1
0
0
R7810
Battery Off (G3Hot)
0
0
0
100K
3.3V 1,05V S5 ENABLE R7802 =PP3V42_G3H_PWRCTL
2
P3V3S5_EN_L
1
5% 1/16W MF-LF 402
NO STUFF
Q7800
D
D 3
10% 10V CERM 402
2
(PM_S4_STATE_L)
PM_SLP_S4_L 1
2
2
R7811 5% 1/16W MF-LF 402
1
1 G
5% 1/16W MF-LF 402
1
PLACEMENT_NOTE=near U7300
PLACEMENT_NOTE=near U7201
P5VS3_EN
=PP3V42_G3H_PWRCTL
DDRREG_EN
C7840 2
PLACEMENT_NOTE=near U4900
5.1K
1
0.1uF
R7801 2
PM_G2_P1V05S5_EN
1
=P1V05S5_EN
20% 10V CERM 402
67
OUT
MAKE_BASE=TRUE
1 2
6
5% 1/16W MF-LF 402
1
PLACEMENT_NOTE=near U7750
C7801
2
VDD
0.47UF 2
10% 6.3V CERM-X5R 402
5
SENSE
4
CT
=P5VS3_EN
OUT
63
=DDRREG_EN
OUT
64
MAKE_BASE=TRUE
68 8
S 2
1
C7810
1
0.47UF
5% 1/16W MF-LF 402
2
RESET*
1
RSMRST_PWRGD
D
C7812 0.47UF
10% 6.3V CERM-X5R 402
2
PLACEMENT_NOTE=near U7300
U7840
MAKE_BASE=TRUE
NO STUFF
R7840 100K
69
OUT
R7812
5.1K
5% 1/16W MF-LF 402 2
=PP3V3_S5_PWRCTL
100K
=P3V3S3_EN
MAKE_BASE=TRUE
PLACEMENT_NOTE=near U1400
68 63 8
5% 1/16W MF-LF 402
IN
S5 rail PWRGD
PLACEMENT_NOTE=near U7201
SMC_PM_G2_EN
R78581
3.3V,5V S3 ENABLE 43 42 40 21
0.068UF
SSM3K15FV IN
63
C7802
1
SOD-VESM-HF 42
OUT
PM_SLP_S3_L
1
10% 6.3V CERM-X5R 402 PLACEMENT_NOTE=near U7201
42
TPS3808G33DBVRG4
CT
PLACEMENT_NOTE=near U7750
SOT23-6
MR*
3
P1V05_S5_PGOOD
67
TPS3808 MR* HAS INTERNAL PULLUP
GND
2
C7841 1
www.laptop-schematics.com
68 63 8
100K
2
3
4
5
0
8
0.001UF 20% 50V CERM 402
2
Other S0 RAILS
68 8
MAKE_BASE=TRUE
PM_SLP_S3_L
1
IN
2
2
5% 1/16W MF-LF 402
C
R78802
1
R7879
R78812
22K
33K
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
1
R7882
R7883
2
0 5% 1/16W MF-LF 402
1
1
2
R7884
2
10K
10K
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
1
2
R7885
0
R7878 83 81 44 42 37 34 21 7
=PP3V3_S0_PWRCTL
PM_SLP_S3_L_R
(PM_SLP_S3_L)
100
1
R7886 5.1K 5% 1/16W MF-LF 402
1
PLACEMENT_NOTE=nearU9900 PLACEMENT_NOTE=nearU7951 PLACEMENT_NOTE=nearQ7971 PLACEMENT_NOTE=nearU7500 PLACEMENT_NOTE=nearU9900 PLACEMENT_NOTE=nearU7700 PLACEMENT_NOTE=nearU7600
P2V5S0_EN
1
=P5V_RTS0_EN
OUT
65
=P3V3S0_EN
OUT
69
10K
=PBUSVSENS_EN
OUT
46
5% 1/16W MF-LF 402 2
=P2V5S0_EN
OUT
86
P1V2_S0_EN
5% 1/16W MF-LF 402 2
R7892 1
=P1V2S0_EN
OUT
65
IN
MCPCORES0_PGOOD
66
IN
CPUVTTS0_PGOOD
OUT
69
OUT
67
P1V8S0_EN
=P1V8S0_EN
MAKE_BASE=TRUE
MCPDDR_EN
P1V8S0_PGOOD
65
IN
P5V_RTS0_PGOOD
63
IN
P5V3V3_PGOOD
OUT
69
=CPUVTTS0_EN
OUT
66
=MCPCORES0_EN
OUT
65
MAKE_BASE=TRUE
MCPCORES0_EN
5% 1/16W MF-LF 402
0.1UF
MAKE_BASE=TRUE
2
S0_PWR_PGOOD MAKE_BASE=TRUE
5 TC7SZ08AFEAPE 2
NO STUFF
R7891 NO STUFF 1
Unused PGOOD signal
C7880 C7881 1
0.47UF 2
DDRREG_PGOOD
64
MAKE_BASE=TRUE
1
0.47UF
10% 6.3V CERM-X5R 402
2
10% 6.3V CERM-X5R 402
C7882 0.47UF
2
C7883
1 C7884
0.47UF
10% 6.3V CERM-X5R 402
68 9
NO STUFF 1
0.47UF
10% 6.3V CERM-X5R 402
2
1
2
C7885 0.47UF
10% 6.3V CERM-X5R 402
2
2
10% 6.3V CERM-X5R 402
100K
P1V1_GPU_EN_RC
4
ALL_SYS_PWRGD
OUT
1
5% 1/16W
EG_PWRSEQ_HW R7868
R7852 0
402
2
68 8
5% 1/16W MF-LF 402
EG_PWRSEQ_HW
Q7850
D 3
1
P1V1_GPU_EN
SOT563
=P1V1GPU_EN OUT
MAKE_BASE=TRUE
G
78
82 83
5% MF-LF 1/16W 402
3
C7850
2
20% 16V CERM 402
D 6
0
1
2
5% 1/16W MF-LF 402
GPUVCORE_EN_RC_L
=P1V8FB_EN
MAKE_BASE=TRUE
OUT
B
67 82 83
C7870 1 0.1uF
NO STUFF
D 3
Q7861
C7869 0.022UF
SOT563
20% 16V CERM 402
5
GPU_S0_EN_L
2
SSM6N15FEAPE
SOT563
100K
P1V8_S0GPU_EN
EG_PWRSEQ_HW
PLACEMENT_NOTE=near U9500
R78531
8
R7869
P1V8_S0GPU_EN_RC
=PP3V3_S0_VMON
G
PLACEMENT_NOTE=near U9500
S 4
1
2
G96 GPU requires rails to come up in the following order: 1) 1.1V 2) GPU_3.3V 3) GPUVcore 4) GDDR3 1.8V BOMOPTION: EG
2
G
VCC
8
=PP1V5_S0_VMON
68
S 1
NC =PP1V05_S0_VMON
LTC2909
1
SEL
8 7
ADJ1 ADJ2
6
REF
DFN
GND
5
8
GPUVCORE ENABLE EG_PWRSEQ_HW R7863 =PP3V3_GPU_PWRCTL
100K
1
2
A
0
1
5% 1/16W 402 MF-LF
GPUVCORE_EN
=GPUVCORE_EN
MAKE_BASE=TRUE
2
OUT
68 8
C7861
SSM6N15FEAPE
GPUVCORE_EN_RC_L
2
G
10% 16V CERM 402 PLACEMENT_NOTE=near U8900
TIE TMR TO GND TRST = 200MS S0PGOOD_PWROK
THRM_PAD
Power Control SYNC_MASTER=PWRSQNC
R7890 1
100K
5% 1/16W MF-LF 402 2
PLACEMENT_NOTE=near U7972
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT
EG_PWRSEQ_HW R7888 0
1
P1V1GPU_PGOOD
5% MF-LF 1/16W 402
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
P3V3GPU_EN
OUT
69 83
82
P1V8FB_PGOOD
PM_ALL_GPU_PGOOD MAKE_BASE=TRUE
OUT
9 68
SIZE
DRAWING NUMBER
D APPLE INC.
5
4
3
2
REV.
051-7546
SCALE
SHT NONE
6
SYNC_DATE=05/12/2008
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
100K
5% 1/16W MF-LF 402 2
2
82
7
68
NOTICE OF PROPRIETARY PROPERTY
R7889
1
0.01UF
S 1
4
=PP3V3_S0_PWRCTL
EG_PWRSEQ_HW 1
D 6
SOT563
RST*
=PP3V3_S0_PWRCTL 68 8
2
Q7861
2
EXT GPU PWRGD Pullup
78 83
PLACEMENT_NOTE=near U8900
EG_PWRSEQ_HW
TMR
LTC2909 THRESHOLD IS 3.136V 1.5V 1.05V COMPARED TO 0.5V
EG_PWRSEQ_HW R7864
GPUVCORE_EN_RC
5% 1/16W MF-LF 402
2
U7870
MAKE_BASE=TRUE
5% 1/16W MF-LF 402 2
20% 10V CERM 402
PLACEMENT_NOTE=near U9500
0.022UF
SSM6N15FEAPE
place XW0402 if needed to save trace space for pin 7,8
EG_PWRSEQ_HW
GPUVCORE_PGOOD
NO STUFF
1
S 4
100K
=PP3V3_GPU_PWRCTL
PLACEMENT_NOTE=near U9500
SSM6N15FEAPE
Q7850
EXTGPU_PWR_EN
8
26 42
B
3.3V 1.05V AND 1.5V S0 RAILS MONITOR CIRCUIT
EG_PWRSEQ_HW
EG_PWRSEQ_HW
68
SOT665
3
1
2
5
68 8
1
ALL_GFX_PGOOD_R
PLACEMENT_NOTE=near U7880
Graphic MEM ENABLE
MF-LF
5% 1/16W MF-LF 402
IN
2
9
=PP3V3_S5_PWRCTL
10K
1
R7850
83
C7886
1.1V GPU ENABLE
2
=PP3V3_S0_PWRCTL
EG_PWRSEQ_HW 68 8
0
U7880Y
5% 1/16W MF-LF 402
0.47UF
10% 6.3V CERM-X5R 402
R7851 68 8
PM_ALL_GPU_PGOOD 1
A
PLACEMENT_NOTE=nearU7500 PLACEMENT_NOTE=nearQ7971 PLACEMENT_NOTE=nearU7951 PLACEMENT_NOTE=nearU9900 PLACEMENT_NOTE=nearQ7600 PLACEMENT_NOTE=nearU7700 PLACEMENT_NOTE=nearU9900
EG_PWRSEQ_HW
B
1
20% 10V CERM 402
2
PLACEMENT_NOTE=near U7880
=MCPDDR_EN
MAKE_BASE=TRUE
CPUVTTS0_EN
R7894 1 0
IN
PLACEMENT_NOTE=near U1400
C
8 68
C7889
1
86
MAKE_BASE=TRUE
P1V05S0_EN
=PP3V3_S5_PWRCTL
S0PGOOD_PWROK
68
MAKE_BASE=TRUE
100K
TP_DDRREG_PGOOD
PM_ALL_GFX_PGOOD high PM_ALL_GPU_PGOOD
IG EG
S0 ENABLE
A.0.0 OF
68
1
96
A
8
6
7
2
3
4
5
3.3V S0 FET
3.3V S3 FET
CRITICAL
CRITICAL
Q7910
Q7930
FDC638P_G
FDC606P_G
=PP3V3_S0_FET
SOT-6
=PP3V3_S3_FET
=PP3V3_S3_P3V3S3FET
8
8
=PP3V3_S0_P3V3S0FET
P3V3S3_EN_L
S 1
47K
=P3V3S3_EN
IN
3
Q7912
5% 1/16W MF-LF 402
RDS(ON)
0.01UF 1
P3V3S3_SS
2
SOT563
48 mOhm @4.5V
LOADING
5% 1/16W MF-LF 402
0.087 A (EDP)
2
68
IN
5
=P3V3S0_EN
G
2
47K 1
S 4
2
LOADING
FDC606P_G
5 6
8
=PP1V05_S5_P1V05S0FET
=PP3V3_GPU_P3V3GPUFET 4
1
P1V05S0_SS
2
5% 1/16W MF-LF 402
5
APN 376S0651
MOSFET
SI7108DN
CHANNEL
10% 10V X5R 402 2
8
4
=PP3V3_S5_P1V05FET
G
5 mOhm @4.5V
LOADING
Q7951
R79531
SSM3K15FV
2.1 A (EDP)
2 G
R7951 P1V05_EN_L
Q7951
1
100K 2
83 68
=PP1V05_S0_FET
C
G
P-TYPE
1
2
10% 16V CERM 402
26 mOhm @4.5V
LOADING
1.1 A (EDP)
BOM_OPTION
EG
IN
P3V3GPU_EN 1
G
S 2
8
C7953 0.068UF
10% 10V 2 CERM 402
5% 1/16W MF-LF 402
D 3
1
S 1
0.01UF
P3V3GPU_SS
5% 1/16W MF-LF 402
D 3
FDC606P
2 3
D 6
SOT563
5% 1/16W MF-LF 402 2
2
MOSFET CHANNEL RDS(ON)
C7970
SOD-VESM-HF
SSM6N15FEAPE
10K
1
Q7972
S
1
1K
P3V3GPU_EN_L
RDS(ON)
2
R7970
N-TYPE
D
8
3.3V GPU FET
1
1UF
51K
PWRPK-1212-8-HF
5% 1/16W MF-LF 402
C7971
R7972 1
1.05V S0 FET
Q7953 SI7108DN
=PP3V3_S0GPU_FET
3
=PP5V_S3_P1V05S0FET
2.9 A (EDP)
Q7970
CRITICAL
8
26 mOhm @4.5V
2
SOT-6
R7952 220K
1 2
D 1
CRITICAL
1.05V S0 FET C
D
10% 16V CERM 402
3.3V GPU FET 8
P-TYPE
RDS(ON)
0.01UF
P3V3S0_SS
5% 1/16W MF-LF 402
10% 16V CERM 402
FDC606P
CHANNEL C7930
R7930 P3V3S0_EN_L
2
3.3V S0 FET MOSFET
G
P-TYPE
C7910
R7910 1
FDC638P
10% 16V X5R 402
www.laptop-schematics.com
68
G
2
MOSFET CHANNEL
SSM6N15FEAPE
2
1
0.033UF
1 2
2
10% 16V X5R 402
C7931
1
100K
D 3
D
10K 5% 1/16W MF-LF 402
SOT563
R7932
1
0.033UF
S
Q7912 SSM6N15FEAPE
4
3.3V S3 FET
2
R7912
D 6
1
3
5
C7911
1
S
5
6 4
D
8
6
SM 8
1
P1V05_EN_L_RC
SSM6N15FEAPE SOT563
5 G 68
S 4
P1V05S0_EN
IN
MCP79 DDR FETs
B
B
MCP79 DDR pad leakage is high enough that nVidia recommends unpowering during sleep. In order to support unpowering rail, hardware must guarantee MEM_CKE signals are low before rail is turned off, and remains low until after rail turns back on or DIMMs will exit self-refresh prematurely. MEM_VTT_EN output from MCP79 used to enable clamp on VTT rail, which pulls all CKE signals low through VTT termination resistors.
1.5V S0 FET
C7902
8
=PP5V_S3_MCPDDRFET
1
1
R7903
10K
2
Q7901 SI7108DN
G
MOSFET
SI7108DN
CHANNEL
N-TYPE
RDS(ON)
5 mOhm @4.5V
LOADING
5.4 A (EDP)
10 5% 1/16W MF-LF 402 2
=PP5V_S3_VTTCLAMP
PWRPK-1212-8-HF
Q7975 R79761
Q7971
D 6 1 2
3
SSM6N15FEAPE SOT563
MCPDDR_EN_L
1
47K 5% 1/16W MF-LF 402
D 3
SSM6N15FEAPE
2
G
S 1
2
1
=PP1V8R1V5_S0_FET
100K 5% 1/16W MF-LF 402 2
8
Power FETs 2
0.068UF 10% 10V 2 CERM 402
Q7975
D
3
IN
S 1
SYNC_MASTER=PWRSQNC
S 4
IN
G
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
1
0.001UF 20% 50V CERM 2 402
MCPDDR_EN_L_RC
SYNC_DATE=05/12/2008
NOTICE OF PROPRIETARY PROPERTY
NO STUFF
C7976
SSM6N15FEAPE SOT563
5
68
G
VTTCLAMP_EN
C7903
64 9
G
D 6
SSM6N15FEAPE SOT563
SOT563
5
90mA max load @ 0.9V 81mW max power
VTTCLAMP_L 8
S
R7971
Q7971
CRITICAL
D
4
100K 5% 1/16W MF-LF 402 2
A
APN 376S0651
5
1
MCPDDR_SS
5% 1/16W MF-LF 402
=PPVTT_S0_VTTCLAMP
R79751
0.1UF 20% 10V CERM 2 402
R7901
8
1.5V S0 FET
=PP1V8R1V5_S0_MCP_FET
8
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
S 4 SIZE
=DDRVTT_EN
DRAWING NUMBER
D
=MCPDDR_EN
APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
69
1
96
A
8
6
7
2
3
4
5
1
OMIT
Page Notes
U8000 89 9
89 9
Signal aliases required by this page: (NONE)
89 9
BOM options provided by this page: (NONE)
89 9
D 8 8 8
=PP1V1_GPU_PEX_PLLXVDD =PP1V1_GPU_PEX_IOVDDQ =PP1V1_GPU_PEX_IOVDD
1UF
4.7UF
10% 2 6.3V CERM 402
NC_GPU_DFM
C8001
1
C8000
U8000
C
1
NB9P-GS H32 M7 P6 P7 R7 U7 V6 AB7 AD6 AF6 AG6 AJ5 D35 AK15 AL7 E7 E35 F7 A2
BGA SYMBOL 2 OF 9 PEX_IOVDD1 PEX_IOVDD2 PEX_IOVDD3 PEX_IOVDD4 PEX_IOVDD5
1UF
AK16 AK17 AK21 AK24 AK27
B
PEX_PLLVDD
1
C8004 0.1UF
20% 2 10V CERM 402
10% 2 6.3V CERM 402
1
AG11 AG12 AG13 AG15 AG16 AG17 AG18 AG22 AG23 AG24 AG25 AG26 AJ14 AJ15 AJ19 AJ21 AJ22 AJ24 AJ25 AJ27 AK18 AK20 AK23 AK26 AL16
1UF
10% 2 6.3V CERM 402
1
1
PEG_R2D_C_P
C8026
0.1uF
IN
1
IN
IN
IN
IN
IN
IN
PEG_R2D_C_N PEG_R2D_C_P PEG_R2D_C_N PEG_R2D_C_P PEG_R2D_C_N PEG_R2D_C_P
4.7UF
20% 2 6.3V CERM 603
C8009 1UF
1
1
C8010
22UF
1
20% 2 10V CERM 402
1
GPU_VDD_SENSE
78
78
0.1uF
1
0.1uF
1
PEG_R2D_C_P
C8034
0.1uF
1
IN
PEG_R2D_C_N
C8035
0.1uF
IN
PEG_R2D_C_P
C8036
0.1uF
89 9
IN
PEG_R2D_C_N
C8037
0.1uF
89 9
1
IN
PEG_R2D_C_P
1
C8016 C8015 1 4.7UF
20% 2 6.3V CERM 603
C8038
1 1
0.1uF
1
IN
PEG_R2D_C_N
C8039
0.1uF
89 9
1
IN
PEG_R2D_C_P
C8040
0.1uF
89 9
1
IN
PEG_R2D_C_N
C8041
0.1uF
89 9
1
IN
PEG_R2D_C_P
C8042
0.1uF
89 9
1
89 9
2
IN
IN
IN
PEG_R2D_C_N PEG_R2D_C_P PEG_R2D_C_N
IN
89 9
IN
PEG_R2D_C_P PEG_R2D_C_N
C8043 C8044 C8045 C8046 C8047
0.1uF
1
0.1uF
1
0.1uF
1
0.1uF
1
0.1uF
1
4.7UF
20% 6.3V 2 CERM 603
AG14
GPU_GND_SENSE
1
IN
0603
C8017 0.1UF
AD19
0.1uF
89 9
10NH-600MA
PP1V1_GPU_PEX_PLLVDD_F
AD20
1
1
89 9
20% 2 10V CERM 402
180mA
GND_SENSE
C8032
0.1uF
0.1uF
89 9
VDD_SENSE
C8031
1
C8033
L8015
1
C8030
0.1uF
PEG_R2D_C_N
89 9
MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.2V
C8029
1
IN
C8011 0.1UF
20% 2 10V CERM 402
C8028
0.1uF
89 9
C8006
20% 2 6.3V CERM-X5R 805
0.1UF
10% 2 6.3V CERM 402
C8027
1
0.1UF
20% 2 10V CERM 402
C8007
0.1uF
89 9
89 9
C8008
1
1
89 9
C8005
0.1uF
0.1uF
1500mA 1
PEX_IOVDDQ1 PEX_IOVDDQ2 PEX_IOVDDQ3 PEX_IOVDDQ4 PEX_IOVDDQ5 PEX_IOVDDQ6 PEX_IOVDDQ7 PEX_IOVDDQ8 PEX_IOVDDQ9 PEX_IOVDDQ10 PEX_IOVDDQ11 PEX_IOVDDQ12 PEX_IOVDDQ13 PEX_IOVDDQ14 PEX_IOVDDQ15 PEX_IOVDDQ16 PEX_IOVDDQ17 PEX_IOVDDQ18 PEX_IOVDDQ19 PEX_IOVDDQ20 PEX_IOVDDQ21 PEX_IOVDDQ22 PEX_IOVDDQ23 PEX_IOVDDQ24 PEX_IOVDDQ25
NC
C8003
1
C8025
NO_TEST=TRUE
OMIT
0.1uF
PEG_R2D_C_N
89 9
20% 2 6.3V CERM-X5R 805
1
IN
22UF
20% 2 6.3V CERM 603
C8023
0.1uF
89 9
89 9
1
PEG_R2D_C_N
C8022
1
C8024
89 9
C8002
IN
PEG_R2D_C_P
C8021
0.1uF
PEG_R2D_C_P
89 9
1
IN
PEG_R2D_C_N
C8020
IN
89 9
250mA
IN
PEG_R2D_C_P
89 9
89 9
PEX 1.1V Current = 2A
IN
89 9
IN
PEG_R2D_C_P
C8048
0.1uF
1
0.1uF
1
0.1uF
1
89 9
IN
PEG_R2D_C_N
C8049
89 9
IN
PEG_R2D_C_P
C8050
89 9
IN
89 17
IN
89 17
IN
9
IN
PEG_R2D_C_N
C8051
0.1uF
1
R8020
1
0 5% 1/16W MF-LF 402
2
BGA SYMBOL 1 OF 9 PEX_RX0 PEX_TX0 PEX_RX0* PEX_TX0*
AL17 AM17
PEG_R2D_P PEG_R2D_N
2 89 10% 16V X5R 40289 2 10% 16V X5R 402
PEG_R2D_P PEG_R2D_N
2 89 10% 16V X5R 40289 2 10% 16V X5R 402
PEG_R2D_P PEG_R2D_N
AR19 AR20
PEX_RX2 PEX_RX2*
PEX_TX2 PEX_TX2*
AL19 AK19
2 89 10% 16V X5R 40289 2 10% 16V X5R 402
PEG_R2D_P PEG_R2D_N
AP20 AN20
PEX_RX3 PEX_RX3*
PEX_TX3 PEX_TX3*
AL20 AM20
2 89 10% 16V X5R 40289 2 10% 16V X5R 402
PEG_R2D_P PEG_R2D_N
2 89 10% 16V X5R 40289 2 10% 16V X5R 402
PEG_R2D_P PEG_R2D_N
2 89 10% 16V X5R 40289 2 10% 16V X5R 402
PEG_R2D_P PEG_R2D_N
AP23 AN23
PEX_RX6 PEX_RX6*
PEX_TX6 PEX_TX6*
AL23 AM23
2 89 10% 16V X5R 40289 2 10% 16V X5R 402
PEG_R2D_P PEG_R2D_N
AN25 AP25
PEX_RX7 PEX_RX7*
PEX_TX7 PEX_TX7*
AM24 AM25
2 89 10% 16V X5R 40289 2 10% 16V X5R 402
PEG_R2D_P PEG_R2D_N
2 89 10% 16V X5R 40289 2 10% 16V X5R 402
PEG_R2D_P PEG_R2D_N
AP26 AN26
PEX_RX9 PEX_RX9*
2 89 10% 16V X5R 40289 2 10% 16V X5R 402
PEG_R2D_P PEG_R2D_N
AN28 AP28
2 89 10% 16V X5R 40289 2 10% 16V X5R 402
PEG_R2D_P PEG_R2D_N
AR28 AR29
2 89 10% 16V X5R 40289 2 10% 16V X5R 402
PEG_R2D_P PEG_R2D_N
2 89 10% 16V X5R 40289 2 10% 16V X5R 402
PEG_R2D_P PEG_R2D_N
AN19 AP19
AN22 AP22
AR22 AR23
AR25 AR26
AP29 AN29
AN31 AP31
PEX_RX1 PEX_RX1*
PEX_RX4 PEX_RX4*
PEX_RX5 PEX_RX5*
PEX_RX8 PEX_RX8*
PEX_TX1 PEX_TX1*
PEX_TX4 PEX_TX4*
PEX_TX5 PEX_TX5*
PEX_TX8 PEX_TX8*
AM18 AM19
AM21 AM22
AL22 AK22
AL25 AK25
PEX_TX9 PEX_TX9*
AL26 AM26
PEX_RX10 PEX_RX10*
PEX_TX10 PEX_TX10*
AM27 AM28
PEX_RX11 PEX_RX11*
PEX_TX11 PEX_TX11*
AL28 AK28
PEX_RX12 PEX_RX12*
PEX_RX13 PEX_RX13*
PEX_TX12 PEX_TX12*
PEX_TX13 PEX_TX13*
AK29 AL29
AM29 AM30
89 89
89 89
89 89
89 89
89 89
89 89
89 89
89 89
89 89
89 89
89 89
89 89
89 89
89 89
2 89 10% 16V X5R 40289 2 10% 16V X5R 402
PEG_R2D_P PEG_R2D_N
AR31 AR32
PEX_RX14 PEX_RX14*
PEX_TX14 PEX_TX14*
AM31
89
AM32
89
2 89 10% 16V X5R 40289 2 10% 16V X5R 402
PEG_R2D_P PEG_R2D_N
AR34 AP34
PEX_RX15 PEX_RX15*
PEX_TX15 PEX_TX15*
AN32 AP32
AR16 AR17
PEX_REFCLK PEX_REFCLK*
PEX_TSTCLK_OUT PEX_TSTCLK_OUT*
AJ17
PEX_TERMP
AG21
89 89
PEG_D2R_C_P PEG_D2R_C_N
PEG_D2R_C_P PEG_D2R_C_N
PEG_D2R_C_P PEG_D2R_C_N
PEG_D2R_C_P PEG_D2R_C_N
PEG_D2R_C_P PEG_D2R_C_N
PEG_D2R_C_P PEG_D2R_C_N
PEG_D2R_C_P PEG_D2R_C_N
PEG_D2R_C_P PEG_D2R_C_N
PEG_D2R_C_P PEG_D2R_C_N
PEG_D2R_C_P PEG_D2R_C_N
PEG_D2R_C_P PEG_D2R_C_N
PEG_D2R_C_P PEG_D2R_C_N
PEG_D2R_C_P PEG_D2R_C_N
PEG_D2R_C_P PEG_D2R_C_N
PEG_D2R_C_P PEG_D2R_C_N
PEG_D2R_C_P PEG_D2R_C_N
C8055
0.1uF
1
C8056
0.1uF
1
C8057
0.1uF
1
C8058
0.1uF
1
C8059
0.1uF
1
C8060
0.1uF
C8061
0.1uF
1
C8062
0.1uF
1
C8063
0.1uF
1
C8064
0.1uF
1
C8065
0.1uF
1
C8066
0.1uF
1
C8067
0.1uF
1
C8068
0.1uF
1
C8069
0.1uF
1
C8070
0.1uF
1
C8071
0.1uF
C8072
0.1uF
C8073
0.1uF
1
C8074
0.1uF
1
C8075
0.1uF
1
C8076
0.1uF
1
C8077
0.1uF
1
C8078
0.1uF
1
C8079
0.1uF
1
C8080
0.1uF
1
C8081
0.1uF
1
C8082
0.1uF
1
C8083
0.1uF
C8084
0.1uF
C8085
0.1uF
1
C8086
0.1uF
1
1
1 1
1 1
2 10% 16V X5R 402 2 10% 16V X5R 402
PEG_D2R_P
OUT
9 89
PEG_D2R_N
OUT
9 89
2 10% 16V X5R 402 2 10% 16V X5R 402
PEG_D2R_P
OUT
9 89
PEG_D2R_N
OUT
9 89
2 10% 16V X5R 402 2 10% 16V X5R 402
PEG_D2R_P
OUT
9 89
PEG_D2R_N
OUT
9 89
2 10% 16V X5R 402 2 10% 16V X5R 402
PEG_D2R_P
OUT
9 89
PEG_D2R_N
OUT
9 89
2 10% 16V X5R 402 2 10% 16V X5R 402
PEG_D2R_P
OUT
9 89
PEG_D2R_N
OUT
9 89
2 10% 16V X5R 402 2 10% 16V X5R 402
PEG_D2R_P
OUT
9 89
PEG_D2R_N
OUT
9 89
2 10% 16V X5R 402 2 10% 16V X5R 402
PEG_D2R_P
OUT
9 89
PEG_D2R_N
OUT
9 89
2 10% 16V X5R 402 2 10% 16V X5R 402
PEG_D2R_P
OUT
9 89
PEG_D2R_N
OUT
9 89
2 10% 16V X5R 402 2 10% 16V X5R 402
PEG_D2R_P
OUT
9 89
PEG_D2R_N
OUT
9 89
2 10% 16V X5R 402 2 10% 16V X5R 402
PEG_D2R_P
OUT
9 89
PEG_D2R_N
OUT
9 89
2 10% 16V X5R 402 2 10% 16V X5R 402
PEG_D2R_P
OUT
9 89
PEG_D2R_N
OUT
9 89
2 10% 16V X5R 402 2 10% 16V X5R 402
PEG_D2R_P
OUT
9 89
PEG_D2R_N
OUT
9 89
2 10% 16V X5R 402 2 10% 16V X5R 402
PEG_D2R_P
OUT
9 89
PEG_D2R_N
OUT
9 89
2 10% 16V X5R 402 2 10% 16V X5R 402
PEG_D2R_P
OUT
9 89
PEG_D2R_N
OUT
9 89
2 10% 16V X5R 402 2 10% 16V X5R 402
PEG_D2R_P
OUT
9 89
PEG_D2R_N
OUT
9 89
2 10% 16V X5R 402 2 10% 16V X5R 402
PEG_D2R_P
OUT
9 89
PEG_D2R_N
OUT
9 89
D
C
B
R8060
PEG_CLK100M_P PEG_CLK100M_N GPU_RESET_L
AP17 AN17
2 89 10% 16V X5R 40289 2 10% 16V X5R 402
www.laptop-schematics.com
NB9P-GS
Power aliases required by this page: - =PP1V2_GPU_PEX_PLLXVDD - =PP1V2_GPU_PEX_IOVDDQ - =PP1V2_GPU_PEX_IOVDD
GPU_RESET_R_L TP_PEX_CLKREQ_L
AM16
PEX_RST*
AR13
PEX_CLKREQ*
PEX_RFU1 PEX_RFU2
AJ18
AG19 NC AG20
PEX_TSTCLK_P PEX_TSTCLK_N PEX_TERMP_PD
200
1
2
1% 1/16W MF-LF 402
R8050 2.49K2
1
1% 1/16W MF-LF 402
NC
NV G96 PCI-E
A
SYNC_MASTER=MUXGFX
SYNC_DATE=07/10/2008
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
70
1
96
A
8 Page Notes
6
7
3
4
5
2
1
OMIT
U8000
U8000
NB9P-GS BGA
NB9P-GS
Signal aliases required by this page: (NONE)
8
=PPVCORE_GPU ???A @ ???/???MHz Core/Mem Clk for VDD
BOM options provided by this page: (NONE)
1
D
2
1
2
1
2
1
2
C
1
2
8
C8100
1
C8101
4.7UF
4.7UF
20% 6.3V X5R-CERM 402
20% 6.3V X5R-CERM 402
2
C8103
1
1
C8102 4.7UF
C8104
2
20% 6.3V X5R-CERM 402
1
C8105
1
C8106
0.47UF
0.47UF
0.47UF
0.47UF
10% 6.3V CERM-X5R 402
10% 6.3V CERM-X5R 402
2
10% 6.3V CERM-X5R 402
2
10% 6.3V CERM-X5R 402
1
C8110
1
2
C8108
1
C8109
C8111
0.47UF
0.47UF
0.47UF
10% 6.3V CERM-X5R 402
10% 6.3V CERM-X5R 402
2
10% 6.3V CERM-X5R 402
2
10% 6.3V CERM-X5R 402
1
C8115
1
C8113
1
C8114 0.1UF
0.1UF
0.1UF
20% 10V CERM 402
20% 10V CERM 402
20% 10V CERM 402
20% 10V CERM 402
2
C8118
1
2
C8119
1
2
C8120
1
1
10% 6.3V CERM-X5R 402
C8112 0.47UF
2
C8116
0.1UF
C8107 0.47UF
2
0.47UF 2
1
1
10% 6.3V CERM-X5R 402
C8117 0.1UF
2
C8121
1
20% 10V CERM 402
C8122
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
20% 10V CERM 402
20% 10V CERM 402
20% 10V CERM 402
20% 10V CERM 402
20% 10V CERM 402
2
2
2
2
=PP1V8_GPU_FBVDDQ
Nvidia PRD for GB-128 uses 4x4.7uF, 8x0.47uF, 16x0.1uF ???A @ ???MHz 1.8V GDDR3
C8150
B
1
C8151
4.7UF
4.7UF
20% 6.3V CERM 603
20% 6.3V CERM 603
2
L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 M12 M14 M16 M18 M20 M22 M24 P11 P13 P15 P17 P19 P21 P23 P25 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 T12 T14 T16 T18 T20 T22 T24 V11 V13 V15 V17
BGA SYMBOL 9 OF 9
VDD
VDD
B3 B6 B9 B12 B15 B21 B24 B27 B30 B33 C2 C34 E6 E9 E12 E15 E18 E24 E27 E30 F2 F5 F31 F34 J2 J5 J31 J34 L9 M2 M5 M11 M13 M15 M17 M19 M21 M23 M25 M31 M34 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 P12 P14 P16 P18 P20 P22 P24 R2 R5 R31 R34 T11 T13 T15 T17 T19 T21 T23 T25 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 V2 V5 V9 V12 V14 V16
V19 V21 V23 V25 W11 W12 W13 W14 W15 W16 W17 W18 W19 AD24 W21 W22 W23 W24 W25 Y12 Y14 Y16 Y18 Y20 Y22 Y24 AB11 AB13 AB15 AB17 AB19 AB21 AB23 AB25 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AD12 AD14 AD16 AD18 AD22 W20
1
2
OMIT
C8156
1
0.1UF 20% 10V CERM 402
C8162
C8157
1
0.1UF 2
1
20% 10V CERM 402
C8163
C8158
1
0.1UF 2
1
20% 10V CERM 402
C8164
C8159
1
0.1UF 2
1
20% 10V CERM 402
C8165
C8160
1
0.47UF 2
1
10% 6.3V CERM-X5R 402
C8166
C8161 0.47UF
2
1
10% 6.3V CERM-X5R 402
C8167
0.1UF
0.1UF
0.1UF
0.1UF
0.47UF
0.47UF
20% 10V CERM 402
20% 10V CERM 402
20% 10V CERM 402
20% 10V CERM 402
10% 6.3V CERM-X5R 402
10% 6.3V CERM-X5R 402
C8168
2
1
C8169
2
1
C8170
2
1
C8171
0.47UF
0.47UF
0.47UF
0.47UF
10% 6.3V CERM-X5R 402
10% 6.3V CERM-X5R 402
10% 6.3V CERM-X5R 402
10% 6.3V CERM-X5R 402
2
2
2
2
U8000
1
2
NB9P-GS BGA
2
B18 J17 U27 AB27 AB29 AC27 AD27 AE27 AJ28 E21 G8 G9 G17 G18 G22 H29 J14 J15 J16
1
2
1
2
A
SYMBOL 7 OF 9
J20 J21 J22 J23 J24 J29 N27 P27 R27 T27
FBVDDQ
FBVDDQ
U29 V27 V29 V34 W27 Y27 AA27 AA29 AA31
SYMBOL 8 OF 9
GND
GND
V18 V20 V22 V24 V31 Y11 Y13 Y15 Y17 Y19 Y21 Y23 Y25 AA2 AA5 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA34
D
www.laptop-schematics.com
Power aliases required by this page: - =PPVCORE_GPU - =PP1V8_GPU_FBVDDQ
AB12 AB14 AB16 AB18 AB20 AB22 AB24 AC9 AD2 AD5 AD11 AD13 AD15 AD17 AD21 AD23 AD25 AD31 AD34 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AG2 AG5 AG31 AG34 AK2 AK5 AP33 AK31 AK34 AL6 AL9 AL12 AL15 AL18 AL21 AL24 AL27 AL30 AN2 AN34 AP3 AP6 AP9 AP12 AP15 AP18 AP21 AP24 AP27 AP30
C
B
NV G96 Core/FB Power SYNC_MASTER=MUXGFX
SYNC_DATE=07/10/2008
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
71
1
96
A
8 Page Notes
6
7
2
3
4
5
1
Power aliases required by this page: - =PP1V2_GPU_FBPLLAVDD - =PP1V8_GPU_FBIO OMIT
D
C
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73 94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
B
BI
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73
BI
94 73 94 73
BI BI
FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ
OMIT
U8000
BOM options provided by this page: (NONE)
U8000
NB9P-GS
NB9P-GS
BGA R30 R32 P31 N30 L31 M32 M30 L30 P33 P34 N35 P35 N34 L33 L32 N33 K31 K30 G30 K32 G32 H30 F30 G31 H33 K35 K33 G34 K34 E33 E34 G33 AG30 AH31 AG32 AF31 AF30 AD30 AC32 AE30 AE32 AF33 AF34 AE35 AE33 AE34 AC35 AB32 AN33 AK32 AL33 AM33 AL31 AK30 AJ30 AH30 AM35 AH33 AH35 AH32 AH34 AM34 AL35 AJ33 P29
NC R29 NC L29 NCM29 NC AD29 NC AE29 NC AG29 NC AH29 NC
SYMBOL 3 OF 9 FBA_D0 FBA_CMD0 FBA_D1 FBA_CMD1 FBA_D2 FBA_CMD2 FBA_D3 FBA_CMD3 FBA_D4 FBA_CMD4 FBA_D5 FBA_CMD5 FBA_D6 FBA_CMD6 FBA_D7 FBA_CMD7 FBA_D8 FBA_CMD8 FBA_D9 FBA_CMD9 FBA_D10 FBA_CMD10 FBA_D11 FBA_CMD11 FBA_D12 FBA_CMD12 FBA_D13 FBA_CMD13 FBA_D14 FBA_CMD14 FBA_D15 FBA_CMD15 FBA_D16 FBA_CMD16 FBA_D17 FBA_CMD17 FBA_D18 FBA_CMD18 FBA_D19 FBA_CMD19 FBA_D20 FBA_CMD20 FBA_D21 FBA_CMD21 FBA_D22 FBA_CMD22 FBA_CMD23 FBA_D23 FBA_D24 FBA_CMD24 FBA_D25 FBA_CMD25 FBA_D26 FBA_CMD26 FBA_D27 FBA_CMD27 FBA_D28 FBA_CMD28 FBA_CMD29 FBA_D29 FBA_CMD30 FBA_D30 FBA_D31 FBA_CLK0 FBA_D32 FBA_CLK0* FBA_D33 FBA_CLK1 FBA_D34 FBA_CLK1* FBA_D35 FBA_D36 FBA_DQM0 FBA_D37 FBA_DQM1 FBA_D38 FBA_DQM2 FBA_D39 FBA_DQM3 FBA_D40 FBA_DQM4 FBA_D41 FBA_DQM5 FBA_D42 FBA_DQM6 FBA_D43 FBA_DQM7 FBA_D44 FBA_D45 FBA_DQS_RN0 FBA_D46 FBA_DQS_RN1 FBA_D47 FBA_DQS_RN2 FBA_D48 FBA_DQS_RN3 FBA_D49 FBA_DQS_RN4 FBA_D50 FBA_DQS_RN5 FBA_D51 FBA_DQS_RN6 FBA_D52 FBA_DQS_RN7 FBA_D53 FBA_D54 FBA_DQS_WP0 FBA_D55 FBA_DQS_WP1 FBA_D56 FBA_DQS_WP2 FBA_D57 FBA_DQS_WP3 FBA_D58 FBA_DQS_WP4 FBA_D59 FBA_DQS_WP5 FBA_D60 FBA_DQS_WP6 FBA_D61 FBA_DQS_WP7 FBA_D62 FBA_D63 FB_DLLAVDD0 FB_PLLAVDD0 FBA_RFU0 FBA_RFU1* FBA_DEBUG FBA_RFU2 FB_CAL_PD_VDDQ FBA_RFU3* FB_CAL_PU_GND FBA_RFU4 FB_CAL_TERM_GND FBA_RFU5* FBA_RFU6 FBA_RFU7*
BGA V32 W31 U31 Y32 AB35 AB34 W35 W33 W30 T34 T35 AB31 Y30 Y34 W32 AA30 AA32 Y33 U32 Y31 U34 Y35 W34 V30 U35 U30 U33 AB30 AB33 T33 W29
FB_A_LMA FB_A_RAS_L FB_A_LMA FB_A_BA FB_A_UMA FB_A_UMA FB_A_UMA FB_A_CS1_L FB_A_CS0_L FB_A_MA FB_A_CAS_L FB_A_WE_L FB_A_BA FB_A_UMA FB_A_MA FB_A_DRAM_RST FB_A_MA FB_A_MA FB_A_CKE FB_A_MA FB_A_MA FB_A_MA FB_A_LMA FB_A_MA FB_A_LMA FB_A_MA FB_A_MA FB_A_BA TP_FBA_CMD28 TP_FBA_CMD29 TP_FBA_CMD30
T32 T31 AC31 AC30
FB_A_CLK_P FB_A_CLK_N FB_A_CLK_P FB_A_CLK_N
P30 P32 J30 H34 AF32 AF35 AL32 AL34
N32 L35 H31 G35 AD32 AC34 AJ31 AJ35
FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L FB_A_RDQS FB_A_RDQS FB_A_RDQS FB_A_RDQS FB_A_RDQS FB_A_RDQS FB_A_RDQS FB_A_RDQS
OUT
73 94
94 74
BI
OUT
73 94
94 74
BI
OUT
73 94
94 74
BI
OUT
73 94
94 74
BI
OUT
73 94
94 74
BI
OUT
73 94
94 74
BI
OUT
73 94
94 74
BI
OUT
76
94 74
BI
OUT
73 94
94 74
BI
OUT
73 94
94 74
BI
OUT
73 94
94 74
BI
OUT
73 94
94 74
BI
OUT
73 94
94 74
BI
94 74
BI
94 74
BI
94 74
BI
94 74
BI
OUT
73 94
OUT
73 94
OUT OUT
73 94
73 94
OUT
73 94
OUT
73 94
1
OUT
OUT
73 94
OUT
73 94
OUT
73 94
OUT
73 94
1
73 94
R8201
R8200
94 74
BI
10K
94 74
BI
94 74
BI
2
5% 1/16W MF-LF 402
10K
2
5% 1/16W MF-LF 402
L34 J32 H35 AE31 AC33 AJ32 AJ34
FB_A_WDQS FB_A_WDQS FB_A_WDQS FB_A_WDQS FB_A_WDQS FB_A_WDQS FB_A_WDQS FB_A_WDQS
FBA_DEBUG FBCAL_PD_VDDQ FBCAL_PU_GND FBCAL_TERM_GND
BI
94 74
BI
73 94
94 74
BI
73 94
94 74
BI
94 74
BI
OUT
73 94
94 74
BI
76
94 74
BI
76
94 74
BI
94 74
BI
94 74
BI
94 74
BI
94 74
BI
94 74
BI
94 74
BI
94 74
BI
76
OUT
73 94
OUT
73 94
OUT OUT
73 94 73 94
BI
73 94
BI
73 94
BI
73 94
BI
73 94
BI BI
73 94
BI
73 94
BI
73 94
IN
73 94
IN
73 94
IN
73 94
IN
73 94
IN
73 94
IN
73 94
72 8
IN
73 94
IN
73 94
OUT
73 94
OUT
73 94
OUT
73 94
OUT
73 94
OUT
94 74
BI
94 74
BI
94 74
BI
94 74
BI
94 74
BI
94 74
BI
94 74
BI
73 94
=PP1V1_GPU_FBPLLAVDD
1
0.1UF
73 94
OUT
73 94
OUT
73 94
OUT
73 94
C8202
1
20% 10V CERM 402
C8201 20% 10V CERM 402
2
94 74
BI
94 74
BI
94 74
BI
94 74
BI
94 74
BI
94 74
BI
L8200 FERR-220-OHM
94 74
BI
2 0402
0.1UF 2
BI
BI
1
1
94 74
94 74
MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.1V
2
94 74
BI
94 74
BI
94 74
BI
C8200
94 74
BI
1UF
94 74
BI
94 74
BI
94 74
BI
10% 6.3V CERM 402
72 8
=PP1V8_GPU_FBIO
1
R8293
1% 1/16W MF-LF 402 2
R82901 48.7
94 74
BI
94 74
BI
94 74 94 74
BI BI
1% 1/16W MF-LF 402 2
1
1% 1/16W U8000.MF-LF 402
R8291 1 33.2
40.2
1% 1/16W MF-LF 402
D11 E11 F10 D8 F8 F9 E8 F12 B11 C13 A11 B8 A8 C8 C11 C10 D12 E13 F17 F15 F16 E16 F14 F13 D13 A13 B13 A14 C16 A17 B16 D16 D24 D26 E25 F25 F27 E28 F28 D29 A25 B25 D25 C26 C28 B28 A28 A29 E29 F29 D30 E31 C33 D33 F32 E32 B29 C29 B31 C31 B32 C32 B34 B35 G11
PLACEMENT_NOTE=Place close to U8000.
R8292 PLACEMENT_NOTE=Place close to
BI
94 74
76
60.4
K27 L27 M27
94 74
OUT
AG27 AF27 T30
BI
OUT
OUT
PP1V1_GPU_FBPLLAVDD_F N31
94 74
FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ
NC G12 NC G14 NC G15 NC G24 NC G25 NC G27 NC NCG28
SYMBOL 4 OF 9 FBC_D0 FBC_CMD0 FBC_D1 FBC_CMD1 FBC_D2 FBC_CMD2 FBC_D3 FBC_CMD3 FBC_D4 FBC_CMD4 FBC_D5 FBC_CMD5 FBC_D6 FBC_CMD6 FBC_D7 FBC_CMD7 FBC_CMD8 FBC_D8 FBC_D9 FBC_CMD9 FBC_D10 FBC_CMD10 FBC_CMD11 FBC_D11 FBC_D12 FBC_CMD12 FBC_D13 FBC_CMD13 FBC_D14 FBC_CMD14 FBC_D15 FBC_CMD15 FBC_D16 FBC_CMD16 FBC_D17 FBC_CMD17 FBC_D18 FBC_CMD18 FBC_D19 FBC_CMD19 FBC_D20 FBC_CMD20 FBC_D21 FBC_CMD21 FBC_D22 FBC_CMD22 FBC_D23 FBC_CMD23 FBC_CMD24 FBC_D24 FBC_D25 FBC_CMD25 FBC_D26 FBC_CMD26 FBC_D27 FBC_CMD27 FBC_CMD28 FBC_D28 FBC_D29 FBC_CMD29 FBC_D30 FBC_CMD30 FBC_D31 FBC_CLK0 FBC_D32 FBC_CLK0* FBC_D33 FBC_CLK1 FBC_D34 FBC_CLK1* FBC_D35 FBC_D36 FBC_D37 FBC_D38 FBC_D39 FBC_D40 FBC_D41 FBC_D42 FBC_D43 FBC_D44 FBC_D45 FBC_D46 FBC_D47 FBC_D48 FBC_D49 FBC_D50 FBC_D51 FBC_D52 FBC_D53 FBC_D54 FBC_D55 FBC_D56 FBC_D57 FBC_D58 FBC_D59 FBC_D60 FBC_D61 FBC_D62 FBC_D63 FBC_RFU0 FBC_RFU1* FBC_RFU2 FBC_RFU3* FBC_RFU4 FBC_RFU5* FBC_RFU6 FBC_RFU7*
C17 B19 D18 F21 A23 D21 B23 E20 G21 F20 F19 F23 A22 C22 B17 F24 C25 E22 C20 B22 A19 D22 D20 E19 D19 F18 C19 F22 C23 B20 A20
FB_B_LMA FB_B_RAS_L FB_B_LMA FB_B_BA FB_B_UMA FB_B_UMA FB_B_UMA FB_B_CS1_L FB_B_CS0_L FB_B_MA FB_B_CAS_L FB_B_WE_L FB_B_BA FB_B_UMA FB_B_MA FB_B_DRAM_RST FB_B_MA FB_B_MA FB_B_CKE FB_B_MA FB_B_MA FB_B_MA FB_B_LMA FB_B_MA FB_B_LMA FB_B_MA FB_B_MA FB_B_BA TP_FBC_CMD28 TP_FBC_CMD29 TP_FBC_CMD30
E17 D17 D23 E23
FB_B_CLK_P FB_B_CLK_N FB_B_CLK_P FB_B_CLK_N
FBC_DQM0 FBC_DQM1 FBC_DQM2 FBC_DQM3 FBC_DQM4 FBC_DQM5 FBC_DQM6 FBC_DQM7
F11 D10
D28 D34 A34
FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L
FBC_DQS_RN0 FBC_DQS_RN1 FBC_DQS_RN2 FBC_DQS_RN3 FBC_DQS_RN4 FBC_DQS_RN5 FBC_DQS_RN6 FBC_DQS_RN7
D9 B10 E14 B14 F26 A26 D31 A31
FB_B_RDQS FB_B_RDQS FB_B_RDQS FB_B_RDQS FB_B_RDQS FB_B_RDQS FB_B_RDQS FB_B_RDQS
D15 A16 D27
FBC_DQS_WP0 FBC_DQS_WP1 FBC_DQS_WP2 FBC_DQS_WP3 FBC_DQS_WP4 FBC_DQS_WP5 FBC_DQS_WP6 FBC_DQS_WP7
E10 A10 D14 C14 E26 B26 D32 A32
FB_DLLAVDD1 FB_PLLAVDD1
J19 J18
FBC_DEBUG
G19
FB_VREF
J27
FB_B_WDQS FB_B_WDQS FB_B_WDQS FB_B_WDQS FB_B_WDQS FB_B_WDQS FB_B_WDQS FB_B_WDQS
OUT
74 94
OUT
74 94
OUT
74 94
OUT
74 94
OUT
74 94
OUT
74 94
OUT
74 94
OUT
76
OUT
74 94
OUT
74 94
OUT
74 94
OUT
74 94
OUT
74 94
OUT
74 94
OUT
74 94
OUT
74 94
D
74 94
OUT
OUT
74 94
OUT
74 94
1
OUT
OUT
74 94
OUT
74 94
OUT
74 94
OUT
74 94
1
R8250 10K
74 94
R8251
2
5% 1/16W MF-LF 402
10K
2
5% 1/16W MF-LF 402
74 94
OUT OUT
74 94
OUT
76
OUT
74 94
C
76 76 76
OUT
74 94
OUT
74 94
OUT
74 94
OUT
74 94
BI
74 94
BI
74 94
BI
74 94
BI
74 94
BI
74 94
BI
74 94
BI
74 94
BI
74 94
IN
74 94
IN
74 94
IN
74 94
IN
74 94
IN
74 94
IN
74 94
IN
74 94
IN
74 94
OUT
74 94
OUT
74 94
OUT
74 94
OUT
74 94
OUT
74 94
OUT
74 94
OUT
74 94
OUT
74 94
72 8
=PP1V1_GPU_FBPLLAVDD
C8290
1
1
0.1UF
72 8
C8291 0.1UF
20% 10V CERM 402
2
2
20% 10V CERM 402
B
=PP1V8_GPU_FBIO
R82941 60.4
R8295 1 1.07K
1% 1/16W MF-LF 402 2
FBC_DEBUG
1% 1/16W MF-LF 402
2
GPU_FB_VREF NO STUFF
C8296
NO STUFF 1 1
10% 16V X5R 402
R8296 1
R8297 1.02K
0.1uF
PLACEMENT_NOTE=Place close to U8000.
1% 1/16W MF-LF 402
2
2.49K 1% 1/16W MF-LF 402
2
2
GPU_FB_VREF_UNTERM_L
2
MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm
2
NO STUFF
Q8295
D
6
SSM6N15FEAPE
NV G96 Frame Buffer I/F
SOT563
A
SYNC_MASTER=MUXGFX 2 76 74 73
IN
G
S
SYNC_DATE=07/10/2008
NOTICE OF PROPRIETARY PROPERTY
1
FB_VREF_UNTERM
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE
DRAWING NUMBER
D APPLE INC.
7
6
5
4
3
2
REV.
051-7546
SCALE
SHT NONE
8
www.laptop-schematics.com
Signal aliases required by this page: (NONE)
A.0.0 OF
72
1
96
A
6
2
3
4
5 CRITICAL
=PP1V8_GPU_FB_VDD
74 73 8
1
1
10UF 20% 6.3V X5R 603
2
2
C8401
1
C8402
1
C8403
1
C8404
0.1uF
0.1uF
0.1uF
0.1uF
10% 16V X5R 402
10% 16V X5R 402
10% 16V X5R 402
10% 16V X5R 402
2
2
2
VDD0 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7
U8400 BGA (2 OF 2)
K1 VDDA0 K12 VDDA1
D 1
2
C8410
1
C8415
0.1uF
0.1uF
10% 16V X5R 402
10% 16V X5R 402
2
U8400.J1
A1 VDDQ0 A12 VDDQ1 C1 VDDQ2 C4 VDDQ3 C9 VDDQ4 C12 VDDQ5 E1 VDDQ6 E4 VDDQ7 E9 VDDQ8 E12 VDDQ9 J4 VDDQ10 J9 VDDQ11 N1 VDDQ12 N4 VDDQ13 N9 VDDQ14 N12 VDDQ15 R1 VDDQ16 R4 VDDQ17 R9 VDDQ18 R12 VDDQ19 V1 VDDQ20 V12 VDDQ21
U8400.J12
Connect to designated pin, then GND 74 73 9 8
=PP1V8_GPU_FB_VDDQ
C8420
1
1
10UF 20% 6.3V X5R 603
73 9
2
2
C8421
1
C8422
1
C8423
1
C8424
1
C8425
1
C8426
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
10% 16V X5R 402
10% 16V X5R 402
10% 16V X5R 402
10% 16V X5R 402
10% 16V X5R 402
10% 16V X5R 402
2
2
2
2
2
=PP1V8_GPU_FB_VREF_A
R8430
1
R8433
549
549
1% 1/16W MF-LF 402
1% 1/16W MF-LF 402
2
1
2
FB_A0_VREF
R8431
1
R8432
1.33K
1
1
1% 1/16W MF-LF 402 2
C8431
R8434
0.01UF
931 1% 1/16W MF-LF 402 2
2
1
R8435
1.33K
10% 16V CERM 402
1
1
C8450
VSS2 G1 VSS3 G12 VSS4 L1
1
1
10UF 20% 6.3V X5R 603
VSS5 L12 VSS6 V3
1% 1/16W MF-LF 402 2
2
A2 A11 F1 F12 M1 M12 V2 V11
2
2
C8451
1
C8452
C8453
1
1
C8454
0.1uF
0.1uF
0.1uF
0.1uF
10% 16V X5R 402
10% 16V X5R 402
10% 16V X5R 402
10% 16V X5R 402
2
2
2
VSS7 V10
VSSA0 J1 VSSA1 J12 VSSQ0 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14 VSSQ15 VSSQ16 VSSQ17 VSSQ18 VSSQ19
B1 B4 B9 B12 D1 D4 D9 D12 G2 G11 L2
C8460
1
1
0.1uF 2
C8465
2
U8400.J1
10% 16V X5R 402
U8400.J12
Connect to designated pin, then GND 74 73 9 8
=PP1V8_GPU_FB_VDDQ
C8470
1
1
10UF
L11 P1 P4 P9 P12 T1 T4 T9 T12
20% 6.3V X5R 603
73 9
2
2
C8471
1
C8472
1
C8473
1
C8474
1
C8475
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
10% 16V X5R 402
10% 16V X5R 402
10% 16V X5R 402
10% 16V X5R 402
10% 16V X5R 402
2
2
2
2
1
C8476 0.1uF 10% 16V X5R 402
2
=PP1V8_GPU_FB_VREF_A
R8480 1
R8483 1
549
549
1% 1/16W MF-LF 402
1% 1/16W MF-LF 402
2
2
FB_A1_VREF
C8432
R8481
1
R8482
1.33K
10% 16V CERM 402
1
1
C8481
R8484
0.01uF
931
1% 1/16W MF-LF 402 2
1% 1/16W MF-LF 402 2
2
1
R8485
1.33K
10% 16V CERM 402
1
1
1% 1/16W MF-LF 402 2
2
B
IN
94 73 72
IN
94 72
IN
94 72
IN
94 72
IN
94 72
IN
94 73 72
IN
94 73 72
IN
94 73 72
IN
94 73 72
IN
94 73 72
IN
94 73 72
IN
94 73 72
IN
94 73 72
94 72 94 72
IN IN IN
94 73 72
IN
94 73 72
IN
94 73 72 94 73 72
IN IN
2
VRAM4 1
R8443
2
R8445 121
243
1% 1/16W MF-LF 402 2
1% 1/16W MF-LF 402 2
1% 1/16W MF-LF 402 2
94 72
OUT FB_A_RDQS
94 72
OUT FB_A_RDQS
94 72 94 72
94 72
A
IN
IN
94 72
IN
94 72
IN
94 72
IN
94 73 72
IN
94 73 72
IN
94 73 72
IN
J11 J10 F4 H4 F9 H10 A4 A9 V4 V9
U8400
DM0
E3
BGA (1 OF 2)
DM1
E10 N10
CK
CK* CS0* WE* CAS* RAS* ZQ MF SEN RESET
D3 RDQS0 D10 RDQS1 P10 RDQS2 P3 RDQS3
OUT FB_A_RDQS
D2 D11 P11 P2
FB_A_WDQS FB_A_WDQS FB_A_WDQS FB_A_WDQS
WDQS0 WDQS1 WDQS2 WDQS3
G9 BA0 G4 BA1 H3 BA2
FB_A_BA FB_A_BA FB_A_BA
S
5
1
G
S
4
R8492
DM2 DM3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6
N3 B2 B3 C2 C3 E2 F3 F2 G3
DQ7 DQ8
B11
DQ9 DQ10
B10 C11
DQ11
C10 E11
DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21
F10 F11 G10 M11 L10 N11 M10 R11 R10
DQ22 T11 DQ23 T10 DQ24 M2 DQ25 L3 DQ26 N2 DQ27 M3 DQ28 R2 DQ29 R3 DQ30 T2 DQ31 T3
FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ
IN
72 94
94 73 72
IN
IN
72 94
94 73 72
IN
IN
72 94
94 72
IN
IN
72 94
94 72
IN
94 72
IN
BI
72 94
BI
72 94
BI
72 94
BI
94 72
IN
94 73 72
IN
94 73 72
IN
94 73 72
IN
94 73 72
IN
94 73 72
IN
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
94 73 72
IN
94 73 72
IN
94 73 72
IN
94 72
IN
BI
72 94
94 72
BI
72 94
94 73 72
IN
BI
72 94
94 73 72
IN
BI
72 94
94 73 72
BI
72 94
94 73 72
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
IN
IN IN
VOLTAGE=0.9V
VRAM4 1
R8494
1
R8496
1K
121
121
243
5% 1/16W MF-LF 402
1% 1/16W MF-LF 402
1% 1/16W MF-LF 402
1% 1/16W MF-LF 402
2
OMIT CRITICAL
J3 A12/CS1*
OUT FB_A_RDQS
G
1
2
VRAM4 1
L9 A11 H9 CKE
FB_A_DRAM_RST
R8490
FB_VREF_UNTERM 2
K3 A6 L4 A7 K2 A8/AP M4 A9 K11 A10
FB_A_CLK_P FB_A_CLK_N FB_A_CS0_L FB_A_WE_L FB_A_CAS_L FB_A_RAS_L
VRAM4
2
K9 A0 H11 A1 K10 A2 M9 A3 K4 A4 H2 A5
FB_A_MA FB_A_MA FB_A_LMA FB_A_LMA FB_A_LMA FB_A_LMA FB_A_MA FB_A_MA FB_A_MA FB_A_MA FB_A_MA FB_A_MA FB_A_CKE FB_A_MA
SOT563
3
R8447
121
FB_A0_ZQ FB_A0_MF FB_A0_SEN 94 73 72
1
SOT563
D
2
R8493
VRAM4 1
1
243 1% 1/16W MF-LF 402
10% 16V CERM 402
IN
L11 P1 P4 P9 P12 T1 T4 T9 T12
121
243
1% 1/16W MF-LF 402 2
1% 1/16W MF-LF 402 2
OUT FB_A_RDQS
94 72
OUT FB_A_RDQS
94 72
72 94
94 72
IN
BI
72 94
94 72
IN
BI
72 94
94 72
IN
BI
72 94
94 72
IN
BI
72 94 94 73 72 72 94
IN
BI BI
72 94
94 73 72
IN
94 73 72
IN
IN
SOT563
D
3
S
4
FB_VREF_UNTERM
U8450
DM0
E3
BGA (1 OF 2)
DM1
E10 N10
J3 A12/CS1* J11 J10 F4 H4 F9 H10 A4 A9 V4 V9
CK
CK* CS0* WE* CAS* RAS* ZQ MF SEN RESET
DQ1 DQ2 DQ3 DQ4 DQ5 DQ6
N3 B2 B3 C2 C3 E2 F3 F2 G3
DQ7 DQ8
B11
DQ9 DQ10
B10 C11
DQ11
C10 E11
DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21
F10 F11 G10 M11 L10 N11 M10 R11 R10
DQ22 T11 DQ23 T10 DQ24 M2 DQ25 L3 DQ26 N2
WDQS0 WDQS1 WDQS2 WDQS3
G9 BA0 G4 BA1 H3 BA2
DQ0
DQ14
P3 RDQS3
D2 D11 P11 P2
DM2 DM3
DQ12 DQ13
D3 RDQS0 D10 RDQS1 P10 RDQS2
FB_A_BA FB_A_BA FB_A_BA
Q8450
G
S
5
1
G
OMIT CRITICAL
L9 A11 H9 CKE
FB_A_WDQS FB_A_WDQS FB_A_WDQS FB_A_WDQS
6
SSM6N15FEAPE
2
K3 A6 L4 A7 K2 A8/AP M4 A9 K11 A10
OUT FB_A_RDQS
BI
74 73 72 76
K9 A0 H11 A1 K10 A2 M9 A3 K4 A4 H2 A5
FB_A_DRAM_RST
94 72
2
D
SOT563
R8497
1% 1/16W MF-LF 402 2
FB_A_CLK_P FB_A_CLK_N FB_A_CS0_L FB_A_WE_L FB_A_CAS_L FB_A_RAS_L
OUT FB_A_RDQS
1
121
FB_A_MA FB_A_MA FB_A_UMA FB_A_UMA FB_A_UMA FB_A_UMA FB_A_MA FB_A_MA FB_A_MA FB_A_MA FB_A_MA FB_A_MA FB_A_CKE FB_A_MA
94 72
DQ27 M3 DQ28 R2 DQ29 R3 DQ30 T2 DQ31 T3
FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ
IN
72 94
IN
72 94
IN
72 94
IN
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
B
BI
GDDR3 Frame Buffer A (Top)
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
SYNC_MASTER=MUXGFX
SYNC_DATE=07/10/2008
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NC J2 RFU
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
R8449 R8498 1
100
2
B1 B4 B9 B12 D1 D4 D9 D12 G2 G11 L2
SSM6N15FEAPE
2
FB_A1_ZQ FB_A1_MF FB_A1_SEN 94 73 72
1
0.01UF
R8495
NC J2 RFU
R8448 1
VSSQ0 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14 VSSQ15 VSSQ16 VSSQ17 VSSQ18 VSSQ19
C
Q8450
C8496
1
K4J10324QD-HC11
VRAM4
IN
Q8400 SSM6N15FEAPE
MFHIGH
2
74 73 72 76
6
32MX32-900MHZ-MFH
2
0.01UF 10% 16V CERM 402
D
VSSA0 J1 VSSA1 J12
10% 16V CERM 402
MFHIGH
243 1% 1/16W MF-LF 402
BOM options provided by this page: VRAM4
VSS7 V10
C8482
MFHIGH
121 1% 1/16W MF-LF 402
D
SSM6N15FEAPE 1
K4J10324QD-HC11
121 1% 1/16W MF-LF 402
C8446
32MX32-900MHZ-MFH
1K 5% 1/16W MF-LF 402
1
94 73 72
R8446
MFHIGH
R8444
MFHIGH
R8442
VSS5 L12 VSS6 V3
FB_A3_VREF_UNTERM_L FB_A1_VREF_UNTERM_L
Q8400
1
MFHIGH
R8440
1
Signal aliases required by this page: (NONE)
0.01uF
931
1% 1/16W MF-LF 402 2
VSS2 G1 VSS3 G12 VSS4 L1
FB_A_CLK1_TERM
VOLTAGE=0.9V
VRAM4 1
BGA (2 OF 2)
Power aliases required by this page: - =PP1V8_S0_FB_VDD - =PP1V8_S0_FB_VREFA
VSS0 A3 VSS1 A10
H1 VREF0 H12 VREF1
FB_A3_VREF
FB_A_CLK0_TERM VRAM4
U8450
A1 VDDQ0 A12 VDDQ1 C1 VDDQ2 C4 VDDQ3 C9 VDDQ4 C12 VDDQ5 E1 VDDQ6 E4 VDDQ7 E9 VDDQ8 E12 VDDQ9 J4 VDDQ10 J9 VDDQ11 N1 VDDQ12 N4 VDDQ13 N9 VDDQ14 N12 VDDQ15 R1 VDDQ16 R4 VDDQ17 R9 VDDQ18 R12 VDDQ19 V1 VDDQ20 V12 VDDQ21
0.1uF
10% 16V X5R 402
FB_A2_VREF_UNTERM_L FB_A0_VREF_UNTERM_L
1
VDD0 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7
K1 VDDA0 K12 VDDA1
0.01UF
931
1% 1/16W MF-LF 402 2
CRITICAL
=PP1V8_GPU_FB_VDD
VSS0 A3 VSS1 A10
H1 VREF0 H12 VREF1
FB_A2_VREF
C
K4J10324QD-HC11
C8400
A2 A11 F1 F12 M1 M12 V2 V11
32MX32-900MHZ-MFH
74 73 8
1 Page Notes
OMIT
www.laptop-schematics.com
OMIT
K4J10324QD-HC11
7
32MX32-900MHZ-MFH
8
2
5% 1/16W MF-LF 402
1
R8499
243
100
1% 1/16W MF-LF 402 2
5% 1/16W MF-LF 402 2
SIZE
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
73
1
96
A
6
2
3
4
5 CRITICAL
=PP1V8_GPU_FB_VDD
74 73 8
1
1
10UF 20% 6.3V X5R 603
2
2
C8501
1
C8502
C8503
1
1
C8504
0.1uF
0.1uF
0.1uF
0.1uF
10% 16V X5R 402
10% 16V X5R 402
10% 16V X5R 402
10% 16V X5R 402
2
2
2
VDD0 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7
U8500 BGA (2 OF 2)
K1 VDDA0 K12 VDDA1
D C8510
1
2
1
C8515
0.1uF
0.1uF
10% 16V X5R 402
10% 16V X5R 402
2
U8500.J1
A1 VDDQ0 A12 VDDQ1 C1 VDDQ2 C4 VDDQ3 C9 VDDQ4 C12 VDDQ5 E1 VDDQ6 E4 VDDQ7 E9 VDDQ8 E12 VDDQ9 J4 VDDQ10 J9 VDDQ11 N1 VDDQ12 N4 VDDQ13 N9 VDDQ14 N12 VDDQ15 R1 VDDQ16 R4 VDDQ17 R9 VDDQ18 R12 VDDQ19 V1 VDDQ20 V12 VDDQ21
U8500.J12
Connect to designated pin, then GND 74 73 9 8
=PP1V8_GPU_FB_VDDQ
C8520
1
1
10UF 20% 6.3V X5R 603
74 9
2
2
C8521
1
C8522
1
C8523
1
C8524
1
C8525
C8526
1
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
10% 16V X5R 402
10% 16V X5R 402
10% 16V X5R 402
10% 16V X5R 402
10% 16V X5R 402
10% 16V X5R 402
2
2
2
2
2
=PP1V8_GPU_FB_VREF_B
R8530
1
R8533 1
549 1% 1/16W MF-LF 402
549 1% 1/16W MF-LF 402 2
2
FB_B0_VREF
R8531
1
R8532
1.33K
1
1
1% 1/16W MF-LF 402 2
C8531
R8534
0.01uF
931 1% 1/16W MF-LF 402 2
2
1
R8535
1.33K
10% 16V CERM 402
1
1
C8550
VSS2 G1 VSS3 G12 VSS4 L1
1
1
10UF 20% 6.3V X5R 603
VSS5 L12 VSS6 V3
1% 1/16W MF-LF 402 2
2
A2 A11 F1 F12 M1 M12 V2 V11
2
2
C8551
1
C8552
C8553
1
1
C8554
0.1uF
0.1uF
0.1uF
0.1uF
10% 16V X5R 402
10% 16V X5R 402
10% 16V X5R 402
10% 16V X5R 402
2
2
2
VSS7 V10
VSSA0 J1 VSSA1 J12 VSSQ0 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14 VSSQ15 VSSQ16 VSSQ17 VSSQ18 VSSQ19
B1 B4 B9 B12 D1 D4 D9 D12 G2 G11 L2
C8560
1
1
0.1uF 2
C8565
2
U8500.J1
10% 16V X5R 402
U8500.J12
Connect to designated pin, then GND 74 73 9 8
=PP1V8_GPU_FB_VDDQ
C8570
1
1
10UF
L11 P1 P4 P9 P12 T1 T4 T9 T12
20% 6.3V X5R 603
74 9
2
2
C8571
1
C8572
1
C8573
1
C8574
1
C8575
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
10% 16V X5R 402
10% 16V X5R 402
10% 16V X5R 402
10% 16V X5R 402
10% 16V X5R 402
2
2
2
2
1
C8576 0.1uF 10% 16V X5R 402
2
=PP1V8_GPU_FB_VREF_B
R8580 1 R8583 1
549 1% 1/16W MF-LF 402
549 1% 1/16W MF-LF 402 2
2
FB_B1_VREF
C8532
R8581
1
R8582
1.33K
10% 16V CERM 402
1
1
C8581
R8584
0.01uF
931
1% 1/16W MF-LF 402 2
1% 1/16W MF-LF 402 2
2
1
R8585
1.33K
10% 16V CERM 402
1
1
1% 1/16W MF-LF 402 2
2
B
IN
94 74 72
IN
94 72
IN
94 72
IN
94 72
IN
94 72
IN
94 74 72
IN
94 74 72
IN
94 74 72
IN
94 74 72
IN
94 74 72
IN
94 74 72
IN
94 74 72
IN
94 74 72
94 72 94 72
IN IN IN
94 74 72
IN
94 74 72
IN
94 74 72 94 74 72
IN IN
2
VRAM4 1
R8543
R8545 121
243
1% 1/16W MF-LF 402 2
1% 1/16W MF-LF 402 2
OUT FB_B_RDQS
94 72
OUT FB_B_RDQS
94 72
94 72
IN
94 72
IN
94 72
IN
94 72
IN
94 74 72
IN
94 74 72
IN
94 74 72
IN
U8500
DM0
E3
BGA (1 OF 2)
DM1
E10 N10
J3 A12/CS1* J11 J10 F4 H4 F9 H10 A4 A9 V4 V9
CK
CK* CS0* WE* CAS* RAS* ZQ MF SEN RESET
D3 RDQS0 D10 RDQS1 P10 RDQS2 P3 RDQS3
D2 D11 P11 P2
FB_B_WDQS FB_B_WDQS FB_B_WDQS FB_B_WDQS
WDQS0 WDQS1 WDQS2 WDQS3
G9 BA0 G4 BA1 H3 BA2
FB_B_BA FB_B_BA FB_B_BA
G
S
5
1
G
S
4
R8592
DM2 DM3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8
N3 B2 B3 C2 C3 E2 F3 F2 G3 B11
DQ9 DQ10
B10 C11
DQ11
C10 E11
DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21
F10 F11 G10 M11 L10 N11 M10 R11 R10
DQ22 T11 DQ23 T10 DQ24 M2 DQ25 L3 DQ26 N2 DQ27 M3 DQ28 R2 DQ29 R3 DQ30 T2 DQ31 T3
FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ
IN
72 94
94 74 72
IN
IN
72 94
94 74 72
IN
IN
72 94
94 72
IN
IN
72 94
94 72
IN
94 72
IN
BI
72 94
BI
72 94
BI
72 94
BI
94 72
IN
94 74 72
IN
94 74 72
IN
94 74 72
IN
94 74 72
IN
94 74 72
IN
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
94 74 72
IN
94 74 72
IN
94 74 72
IN
94 72
IN
BI
72 94
94 72
BI
72 94
94 74 72
IN
BI
72 94
94 74 72
IN
BI
72 94
94 74 72
BI
72 94
94 74 72
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
IN
IN IN
VOLTAGE=0.9V
VRAM4 1
R8594
1
R8596
1K
121
121
243
5% 1/16W MF-LF 402
1% 1/16W MF-LF 402
1% 1/16W MF-LF 402
1% 1/16W MF-LF 402
2
OMIT CRITICAL
L9 A11 H9 CKE
FB_B_RDQS OUT FB_B_RDQS
R8590
1
2
VRAM4 1
K3 A6 L4 A7 K2 A8/AP M4 A9 K11 A10
OUT
VRAM4
FB_VREF_UNTERM 2
K9 A0 H11 A1 K10 A2 M9 A3 K4 A4 H2 A5
FB_B_CLK_P FB_B_CLK_N FB_B_CS0_L FB_B_WE_L FB_B_CAS_L FB_B_RAS_L
3
R8547
1% 1/16W MF-LF 402 2
FB_B_MA FB_B_MA FB_B_LMA FB_B_LMA FB_B_LMA FB_B_LMA FB_B_MA FB_B_MA FB_B_MA FB_B_MA FB_B_MA FB_B_MA FB_B_CKE FB_B_MA
94 72
94 72
A
IN
1
121
FB_B_DRAM_RST
SOT563
2
FB_B0_ZQ FB_B0_MF FB_B0_SEN 94 74 72
SOT563
D
2
VRAM4 1
R8593
1
243 1% 1/16W MF-LF 402
IN
L11 P1 P4 P9 P12 T1 T4 T9 T12
OUT FB_B_RDQS
94 72
OUT FB_B_RDQS
94 72
121
243
1% 1/16W MF-LF 402 2
1% 1/16W MF-LF 402 2
72 94
94 72
IN
BI
72 94
94 72
IN
BI
72 94
94 72
IN
BI
72 94
94 72
IN
BI
72 94 94 74 72 72 94
IN
BI BI
72 94
94 74 72
IN
94 74 72
IN
74 73 72 76
IN
SOT563
D
3
S
4
FB_VREF_UNTERM
U8550
DM0
E3
BGA (1 OF 2)
DM1
E10 N10
L9 A11 H9 CKE
J3 A12/CS1* J11 J10 F4 H4 F9 H10 A4 A9 V4 V9
CK
CK* CS0* WE* CAS* RAS* ZQ MF SEN RESET
DQ1 DQ2 DQ3 DQ4 DQ5 DQ6
N3 B2 B3 C2 C3 E2 F3 F2 G3
DQ7 DQ8
B11
DQ9 DQ10
B10 C11
DQ11
C10 E11
DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21
F10 F11 G10 M11 L10 N11 M10 R11 R10
DQ22 T11 DQ23 T10 DQ24 M2 DQ25 L3 DQ26 N2
WDQS0 WDQS1 WDQS2 WDQS3
G9 BA0 G4 BA1 H3 BA2
DQ0
DQ14
P3 RDQS3
D2 D11 P11 P2
DM2 DM3
DQ12 DQ13
D3 RDQS0 D10 RDQS1 P10 RDQS2
FB_B_BA FB_B_BA FB_B_BA
Q8550
G
S
5
1
G
OMIT CRITICAL
K3 A6 L4 A7 K2 A8/AP M4 A9 K11 A10
FB_B_WDQS FB_B_WDQS FB_B_WDQS FB_B_WDQS
6
SSM6N15FEAPE
2
K9 A0 H11 A1 K10 A2 M9 A3 K4 A4 H2 A5
OUT FB_B_RDQS
BI
2
D
SOT563
R8597
1% 1/16W MF-LF 402 2
FB_B_DRAM_RST
94 72
1
121
FB_B_CLK_P FB_B_CLK_N FB_B_CS0_L FB_B_WE_L FB_B_CAS_L FB_B_RAS_L
OUT FB_B_RDQS
DQ27 M3 DQ28 R2 DQ29 R3 DQ30 T2 DQ31 T3
FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ
IN
72 94
IN
72 94
IN
72 94
IN
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
B
BI
GDDR3 Frame Buffer B (Top)
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
BI
72 94
SYNC_MASTER=MUXGFX
R8598 1
1
243 1% 1/16W MF-LF 402
5% 1/16W MF-LF 402
SYNC_DATE=07/10/2008
NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NC J2 RFU
R8549
2
10% 16V CERM 402
FB_B_MA FB_B_MA FB_B_UMA FB_B_UMA FB_B_UMA FB_B_UMA FB_B_MA FB_B_MA FB_B_MA FB_B_MA FB_B_MA FB_B_MA FB_B_CKE FB_B_MA
94 72
100
2
B1 B4 B9 B12 D1 D4 D9 D12 G2 G11 L2
SSM6N15FEAPE
2
FB_B1_ZQ FB_B1_MF FB_B1_SEN 94 74 72
1
0.01UF
R8595
NC J2 RFU
R8548 1
VSSQ0 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14 VSSQ15 VSSQ16 VSSQ17 VSSQ18 VSSQ19
C
Q8550
C8596
1
K4J10324QD-HC11
VRAM4
IN
Q8500 SSM6N15FEAPE
MFHIGH
2
74 73 72 76
6
32MX32-900MHZ-MFH
2
2
D
SSM6N15FEAPE
0.01UF 10% 16V CERM 402
D
VSSA0 J1 VSSA1 J12
10% 16V CERM 402
MFHIGH
243 1% 1/16W MF-LF 402
BOM options provided by this page: VRAM4
VSS7 V10
C8582
MFHIGH
121 1% 1/16W MF-LF 402
K4J10324QD-HC11
121 1% 1/16W MF-LF 402
32MX32-900MHZ-MFH
1K 5% 1/16W MF-LF 402
1
94 74 72
R8546
MFHIGH
R8544
1
MFHIGH
R8542
VSS5 L12 VSS6 V3
FB_B3_VREF_UNTERM_L FB_B1_VREF_UNTERM_L
Q8500
C8546
1
MFHIGH
R8540
1
Signal aliases required by this page: (NONE)
0.01uF
931
1% 1/16W MF-LF 402 2
VSS2 G1 VSS3 G12 VSS4 L1
FB_B_CLK1_TERM
VOLTAGE=0.9V
VRAM4 1
BGA (2 OF 2)
Power aliases required by this page: - =PP1V8_S0_FB_VDD - =PP1V8_S0_FB_VREF_B
VSS0 A3 VSS1 A10
H1 VREF0 H12 VREF1
FB_B3_VREF
FB_B_CLK0_TERM VRAM4
U8550
A1 VDDQ0 A12 VDDQ1 C1 VDDQ2 C4 VDDQ3 C9 VDDQ4 C12 VDDQ5 E1 VDDQ6 E4 VDDQ7 E9 VDDQ8 E12 VDDQ9 J4 VDDQ10 J9 VDDQ11 N1 VDDQ12 N4 VDDQ13 N9 VDDQ14 N12 VDDQ15 R1 VDDQ16 R4 VDDQ17 R9 VDDQ18 R12 VDDQ19 V1 VDDQ20 V12 VDDQ21
0.1uF
10% 16V X5R 402
FB_B2_VREF_UNTERM_L FB_B0_VREF_UNTERM_L
1
VDD0 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7
K1 VDDA0 K12 VDDA1
0.01uF
931
1% 1/16W MF-LF 402 2
CRITICAL
=PP1V8_GPU_FB_VDD
VSS0 A3 VSS1 A10
H1 VREF0 H12 VREF1
FB_B2_VREF
C
K4J10324QD-HC11
C8500
A2 A11 F1 F12 M1 M12 V2 V11
32MX32-900MHZ-MFH
74 73 8
1 Page Notes
OMIT
www.laptop-schematics.com
OMIT
K4J10324QD-HC11
7
32MX32-900MHZ-MFH
8
II NOT TO REPRODUCE OR COPY IT
R8599
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
100
2
2
SIZE
5% 1/16W MF-LF 402
DRAWING NUMBER
D APPLE INC.
SCALE
SHT NONE
8
7
6
5
4
3
2
REV.
051-7546
A.0.0 OF
74
1
96
A
8 Page Notes
6
7 110mA
Power aliases required by this page: - =PP3V3_GPU_VDD33 - =PP3V3_GPI_MIO - =PP1V2_GPU_PLLVDD - =PP1V2_GPU_H_PLLVDD - =PP1V2_GPU_VID_PLLVDD
76 75 8 6
U8000 NB9P-GS BGA
1 2
1 =PP3V3_GPU_VDD33 Typically
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