AMIE Lab Report Ravi Kumar

LABORATORY EXPERIMENTS REPORT FILE COMPUTER SCIENCE & ENGINEERING NOV/DEC 2013 SESSION PERFORMED AT

RAYAT COLLEGE OF ENGINEERING AND TECHNOLOGY, ROPAR

Submitted By

Submitted To

Ravi Kumar Rachuri

Mr Harish Kundra

ST-332396-5

Head Of Department CSE & IT

INDEX SL No 1 2

3

4

5

6

7 8

9

10

Laboratory Experiment Pulse & Digital Circuits To design a 4-bit synchronous counter & study its function. To design a 4-bit asynchronous counter & study its function. Data Structures To obtain the given tree type structure using a suitable structure. (Binary Search Tree) To define a node with the given structure and to implement insert, delete & search. (Singly Linked List) Programming To develop a function on ‘C’ that splits a list into two other lists so that the entries that were in odd-numbered positions are now in one list (in the same relative order as before) and those from evennumbered position are in another new list. To write a ‘C’ program to print the day for an input of date, month and year. Computer Architecture To design on paper a full 18 X 16 barrel shifter. To design a 4-bit, 8 function arithmetic unit that will meet the given specifications. System Analysis To draw the systems flow-chart showing the given steps in processing customer’s sales order. To describe in detail a pay roll data processing application giving inputs, outputs and files required. Draw the system flowchart and show the structure of input documents and output reports.

Date

Page Number 01-02 03-04

05-06

07-11

12-12

13-13

14-15 16-19

20-21

22-23

Teacher’s Remarks Initials

1 Experiment No: 1 (Pulse & Digital Circuits) Objective:

To design a 4-bit synchronous counter and study its function.

Requirements: 4 JK flip-flops, Square clock generator, 7-segment LED to display the decimal number. Preparation: In the Asynchronous binary counter, the output of one counter stage is connected directly to the input of the next counter stage and so on along the chain, and as a result the asynchronous counter suffers from what is known as "Propagation Delay". However, with Synchronous Counters, the external clock signal is connected to the clock input of EVERY individual flip-flop within the counter so that all of the flip-flops are clocked together simultaneously (in parallel) at the same time giving a fixed time relationship. Feed the output Q0, Q1, Q2 and Q4 to 7-segment LED.

Counter State & Required Inputs:

Q3

Q2

Q1

Q0

JA

KA

JB

KB

JC

KC

JD

KD

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X

X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1

0 1 X X 0 1 X X 0 1 X X 0 1 X X

X X 0 1 X X 0 1 X X 0 1 X X 0 1

0 0 0 1 X X X X 0 0 0 1 X X X X

X X X X 0 0 0 1 X X X X 0 0 0 1

0 0 0 0 0 0 0 1 X X X X X X X X

X X X X X X X X 0 0 0 0 0 0 0 1

RAVI KUMAR RACHURI

COMPUTER SCIENCE & ENGINEERING 332396-5

ST-

2 A 4-bit Synchronous counter made by using JK flip-flops is shown below.

Observation: It can be seen that the external clock pulses (pulses to be counted) are fed directly to each JK flip-flop in the counter chain and that both the J and K inputs are all tied together, but only in the first flip-flop, flip-flop A (LSB) are they connected HIGH, logic “1” allowing the flip-flop to toggle on every clock pulse. The J and K inputs of flip-flop B are connected to the “Q” of flip-flop A, but the J and K inputs of flip-flops C and D are driven from AND gates which are also supplied with signals from the input and output of the previous stage, If we enable each J-K flip-flop to toggle based on whether or not all preceding flip-flop outputs (Q) are “HIGH” we can obtain the same counting sequence as with the asynchronous circuit but without the ripple effect, since each flip-flop in this circuit will be clocked at exactly the same time. Result: 4-bit synchronous waveform diagram is shown below.

The counter counts sequentially on every clock pulse the resulting outputs count upwards from 0000 to 1111. RAVI KUMAR RACHURI

COMPUTER SCIENCE & ENGINEERING 332396-5

ST-

3 Experiment No: 2 (Pulse & Digital Circuits) Objective:

To design a 4-bit asynchronous counter and study its function.

Requirements: 4 T flip-flops, Square clock generator, 7-segment LED to display the decimal number. Preparation: Connect the T flip-flop, input clock as per the below given figure. Connect the four outputs QA, QB, QC and QD to the input of 7-segment LED. The T-type flip-flop is an edge-triggered device based on the standard RS flip-flop. They can be triggered to switch on either the leading or trailing edge of the input clock signal. A 4-bit Asynchronous counter made by using JK flip-flops is shown below.

Observation: This type of counter is commonly known as an Asynchronous 4-bit binary counter as the output on QA to QD, which is 4-bit wide, is a binary count from 0 to 15 for each clock pulse, with the output of one flip-flop stage providing the clocking signal for the next flipflop stage. This arrangement is commonly known as Asynchronous, Output QA will be the LSB and QD will be the MSB, as the clocks arrives the corresponding number will get display in LED increments by one. Result: 4-bit asynchronous waveform diagram is shown below.

RAVI KUMAR RACHURI

COMPUTER SCIENCE & ENGINEERING 332396-5

ST-

4

The counter counts sequentially on every clock pulse the resulting outputs count upwards from 0000 to 1111.

RAVI KUMAR RACHURI

COMPUTER SCIENCE & ENGINEERING 332396-5

ST-

5 Experiment No: 3 (Data Structures) Objective: Determination of Passes, Comparisons and Exchanges for Bubble Sort. Objective To find expected number of passes, comparisons and exchanges for bubble sort when n=12 and compare them with actual number of these operations when the given sequence is as follows:8, 6, 4, 3, 7, 9, 5, 12, 1, 11, 10, 2 Minimum Requirements: Desktop/Laptop with Windows XP or higher with C compiler. Bubble sort Implementation: #include #include int main() { int a[10],i,j,n,temp; cout