ALU 4 bit verilog

Bach Khoa University Faculty of Electrical & Electronics Engineering Department of Electronics Engineering

EE3043 - COMPUTER ARCHITECTURE Lab 2 report : Design a 4-bit Arithmetic Logic Unit Instructor

: Dr. Trần Hoàng Linh

Student

: Hoàng Minh Nhường – 1412770

Submission Date : Mar, 2017

1. Objective The objective of this lab are review the sequential logic, apply knowledge to design a simple 4-bit ALU using HDL and then simulate the result that designed with ModelSim. 2. ALU specification Design a simple ALU following: - Length of the parameters is 4 bits - The input of ALU involved of 3 funtion-selects are M, S0 and S1 - The instruction set : M

S0

S1

function

Description

0

0

0

Ai.Bi

AND

0

0

1

Ai+Bi

OR

0

1

0

Ai (+) Bi

XOR

0

1

1

~( Ai (+) Bi)

XNOR

1

0

0

A+C0

Add A to Carry

1

0

1

A+B+C0

Add A to B and Carry

1

1

0

A+’B+C0

Add A to ‘B and Carry

1

1

1

‘A+B+C0

Add ‘A to B and Carry

- Block Diagram of the ALU :

- Result of the design process must a logic circuit that can implement in reality with minimum of hardware resource 3. Procedures

- In a simple ALU consist of 2 modules: AU ( Arithmetic Unit) and LU ( Logic Unit) so we can split the ALU into two parts to design and then using a MUX 2:1 for the output.

3.1

Design the 4-bit Arithmetic Unit Fist at all, we notice that all the instructions is involved with addition operation so we have to build a 4-bit full adder module and then use gates to change the values of full-adder’s input correspondingly. So, with this idea, I made a truth-table of the full-adder’s inputs: S0

S1

A

0 0 0 0 1 1 1 1 S0

0 0 1 1 0 0 1 1 S1

0 1 0 1 0 1 0 1 B

A_adde r 0 1 0 1 0 1 1 0 B_adde

note A+C_in A+C_in A+B+C_in A+B+C_in A+’B+C_in A+’B+C_in ‘A+B+C_in ‘A+B+C_in note

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

r 0 0 0 1 1 0 0 1

A+C_in, B_add=0 A+C_in, B_add=0 A+B+C_in A+B+C_in A+’B+C_in A+’B+C_in ‘A+B+C_in ‘A+B+C_in

According to the truth table, We use Karnaugh map to make a Boolean equations and simplify it, thus:. A adder = A ⊕ (S 0 . S1 ) ´ S1 . B B adder =S0 . S´ 1 . B+

Code Verilog HDL for Arithmetic Unit : /* Arithmetic Unit function module AU( Out, Co, S0, S1, A, B, Ci ) ; output [3:0] Out ;

*/

output Co ; input [3:0] A, B ; input S0, S1, Ci ; wire [3:0] A_in, B_in ; preAU inputs of full

pre0(A_in[0], B_in[0], S0, S1, A[0], B[0]); //calculate

preAU corresponding with

pre1(A_in[1], B_in[1], S0, S1, A[1], B[1]); //adder

preAU and S1

pre2(A_in[2], B_in[2], S0, S1, A[2], B[2]); //opcode S0

preAU

pre3(A_in[3], B_in[3], S0, S1, A[3], B[3]);

Fulladder_4bit

add0(Out, Co, A_in, B_in, Ci );

endmodule /* this function calculate the input for full adder module correspondingly */ module preAU ( A_o, B_o, S0, S1, A, B ) ; output A_o , B_o ;

//A_o , B_o is the inputs of full-adder

input S0, S1, A, B ; assign A_o = A ^ ( S0 & S1 ), B_o = ( S0 & ~S1 & ~B) | (S1 & B) ; endmodule /* 4-bit adder function

*/

module Fulladder_4bit ( SUM, C_out , A, B, C_in) ; output [3:0] SUM; output C_out ; input [3:0] A , B ; input C_in ; wire C1, C2, C3 ; Fulladder_1bit fa_0(SUM[0], C1, A[0], B[0], C_in); Fulladder_1bit fa_1(SUM[1], C2, A[1], B[1], C1) ;

Fulladder_1bit fa_2(SUM[2], C3, A[2], B[2], C2) ; Fulladder_1bit fa_3(SUM[3], C_out, A[3], B[3], C3) ; endmodule // Module Ripper Full Adder 1-bit module Fulladder_1bit(sum, c_out, a, b, c_in); output sum, c_out ; input a, b, c_in; assign sum = a ^ b ^ c_in ; assign c_out = ( a & b) | ( ( a ^ b) & c_in ) ; endmodule

3.2

Design of the 4-bit Logic Unit There’re a lot of way to make a Logic Unit, for simple and reduce the amout of transistor needed, I made a truth table for 1-bit ALU with opcodes S0,S1 correspondingly: S0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

S1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

A 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

B 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

LU_out Note 0 AND 0 0 1 0 OR 1 1 1 0 XOR 1 1 0 1 XNOR 0 0 1

LU out =S1 ( S 0 ⊕ ( A+ B )) + AB ( S´0 + S 1) + S 0 S´1 ( A ⊕ B)

We use 4 module 1-bit LU for 4-bit LU. Code Verilog HDL for 4-bit Logic Unit: /* Logic Unit function */ module LU( Lu_out, A, B, S0, S1); output [3:0] Lu_out ; input [3:0] A, B ; input S0, S1 ; LU_1bit LU_1bit LU_1bit LU_1bit

Logic1(Lu_out[0], Logic2(Lu_out[1], Logic3(Lu_out[2], Logic4(Lu_out[3],

S0, S0, S0, S0,

S1, S1, S1, S1,

A[0], A[1], A[2], A[3],

B[0] B[1] B[2] B[3]

endmodule /* 1-bit LU function */ module LU_1bit ( F0, S0, S1, Ai, Bi); output F0 ; input S0, S1, Ai, Bi ; assign F0 = (S1 & (S0 ^ ( Ai | Bi ) ) ) | ((Ai & Bi ) & ( ~S0 | S1) ) | ((S0 & ~S1 ) & ( Ai ^ Bi )) ; Endmodule

); ); ); );

3.3

Design a 4 bit Mux 2:1 According to two above designed module ( AU and LU), both of AU and LU will work concurently because is not depend on M ( bit-select). So, we have to buid a Mux 2:1 to choose the output that we expected. The idea is we will buid a 4 modules Mux 2:1 bit for 4 bit inout with common bit select (M). Mux 2:1 :

´ ( L U out [i]) + M ( A U out [i]) Fout [ i ] = M

Code: module mux2to1_4bit( F , A, B, M) ; output [3:0] F ; input [3:0] A, B ; input M ; assign F[0] = (~M & A[0] ) | (M & B[0]), F[1] = (~M & A[1] ) | (M & B[1]), F[2] = (~M & A[2] ) | (M & B[2]), F[3] = (~M & A[3] ) | (M & B[3]) ; // respectively endmodule

3.4

Final ALU module After made the sub-modules completely, we’re gonna combine all of those to main ALU module with full of inputs and outputs that exercise required : module ALU_4bit(F, Cout, A, B, Cin, S0, S1 , M ); output [3:0] F ; // F is 4-bit output of ALU output Cout ; //Cout is ouput Carry of ALU for Arithmetic operands input [3:0] A, B ; input Cin, S0, S1, M ; wire [3:0] Lu_out , AU_out ; wire co ; LU lu1 (Lu_out , A , B , S0, S1 ) ; AU au1 (AU_out , Cout, S0, S1, A , B , Cin ) ; Mux2to1_4bit mux1 ( F, Lu_out, AU_out, M ) ; assign Cout = co & M ; //to ensure Cout always equa zero in LU endmodule

3.5

Test file and results The module below is test module, simulating in ModelSim. module stimulus ; reg [3:0] A, B ; reg c_in ; reg [2:0] opcode ; wire [3:0] F_out ; wire c_out ;

ALU_4bit alu1( F_out, c_out, A, B, c_in, opcode[1], opcode[0], opcode[2] ) ; initial begin opcode //AND #50 opcode #50 opcode #50 opcode //XNOR #50 opcode #50 opcode //A+B+C #50 opcode //A+'B+C

= 3'b000 ; A = 4'd12 ; B = 4'd9 ; c_in =1'b0 ; = 3'b001 ; A = 4'd8 ; B = 4'd5 ; c_in =1'b0 ; //OR = 3'b010 ; A = 4'd7 ; B = 4'd6 ; c_in =1'b0 ; //XOR = 3'b011 ; A = 4'd8 ; B = 4'd5 ; c_in =1'b0 ; = 3'b100 ; A = 4'd7 ; B = 4'd4 ; c_in =1'b0 ; //A+C = 3'b101 ; A = 4'd2 ; B = 4'd9 ; c_in =1'b1 ; = 3'b110 ; A = 4'd15; B = 4'd9 ; c_in =1'b0 ;

#50 opcode = 3'b111 ; A = 4'd2 ; B = 4'd13 ; c_in =1'b1 ; //'A+B+C end endmodule

Waveforms result:

Truth table of above simulation result : M

S0 S1

A

B 1001 B 0101 B 0110 B 0101 B 4H

C_i n 0

F_out 1000B

C_o ut 0

note A and B

0

1101B

0

A or B

0

0001B

0

A xor B

0

0010B

0

A xnor B

0

7H

0

A+C

0

0

0

0

0

1

0

1

0

0

1

1

1

0

0

1100 B 1000 B 0111 B 1000 B 7H

1

0

1

2H

9H

1

CH

0

A+B+C

1

1

0

FH

9H

0

5H

1

A+’B+C

1

1

1

2H

DH

1

BH

1

‘A+B+C

So, according to the result of simulation wave-form,wee see that the ALU has worked correctly. All of results as we expected.

4. Conclusion & Discussion - The Lab has finished with correct results. - The ALU is an important part of every CPU. I learnt how to produre different arithmetic and logic function by divide it into smaller parts and then design one by one from idea to logic gate and then test the idea with Verilog HDL and simulate with ModelSim. - Actually, the design in my lab above is not the best way to make a ALU. For instance, we can use the full-adder with carry look-ahead instead of ripple full-adder for the best performative… - The lab helped me review and enhance my poor knowledge about digital design. It’s very interesting and I’m gonna study harder for this.