ADC LAB MANUAL _ CYCLE 2

EXPT NO:

DIGITAL CIRCUITS LABORATORY

DATE:

LOYOLA – ICAM COLLEGE OF ENGINEERING AND TECHNOLOGY (LICET) DEPARTMENT OF ECE

LAB MANUAL FOR EC6311 – ANALOG AND DIGITAL CIRCUITS LABORATORY

CYCLE II

List of experiments: Design and implementation of code converters using logic gates (i) BCD to excess-3 code and vice versa (ii) Binary to gray and vice-versa Design and implementation of 4 bit binary Adder/ Subtractor and BCD adder using IC 7483 Design and implementation of Multiplexer and De-multiplexer using logic gates Design and implementation of encoder and decoder using logic gates Construction and verification of 4 bit ripple counter and Mod-10 / Mod-12 Ripple counters Design and implementation of 3-bit synchronous up/down counter Implementation of SISO, SIPO, PISO and PIPO shift registers using Flip- flops

Add-on content:  System design using above experiments

EXPT NO:

DIGITAL CIRCUITS LABORATORY

DATE:

CODE CONVERTERS BINARY CODE TO GRAY CODE AIM: To Design and Implement BINARY TO GRAY & GRAY TO BINARY using logic gates.

APPARATUS REQUIRED:

PROCEDURE: 1. The connections are made as per the circuit diagram. 2. Give the logical inputs as per the truth table. 3. The corresponding output is verified with their truth table.

EXPT NO:

DIGITAL CIRCUITS LABORATORY

DATE:

BINARY TO GRAY TRUTH TABLE INPUT C 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 0

D 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1

CODE

B3

B2

TO

B1

Y 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1

Z 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1

CONVERTER

GRAY

CODE

B0

IC7486

1

BINARY

OUTPUT X 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0

W 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

3

G0

6

G1

8

G2

2

IC7486

4

B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

5

IC7486

9

A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

10

G3

EXPT NO:

DIGITAL CIRCUITS LABORATORY

DATE:

GRAY TO BINARY TRUTH TABLE

W 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

GRAY G3 G2

X 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0

INPUT Y 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0

Z 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

OUTPUT B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

TO BINARY CODE G1 G0 IC7486 1

2

3

IC7486 10

9 8

B0

IC7486 4

5

6

IC7486

IC7486 3

12

13

2

1

11

B1

IC7486 5

4

RESULT: Thus the Code Converters were designed and implemented.

6

B2 B3

EXPT NO:

DIGITAL CIRCUITS LABORATORY

DATE:

BCD TO EXCESS 3 CODE AND VICE VERSA

AIM: To Design and Implement BCD TO EXCESS 3 & EXCESS TO BCD converter using logic gates.

APPARATUS REQUIRED: 1. IC trainer kit. 2. IC 7486 3. Connecting wires

PROCEDURE: 1. The connections are made as per the circuit diagram. 2. Give the logical inputs as per the truth table. 3. The corresponding output is verified with their truth table.

EXPT NO:

DIGITAL CIRCUITS LABORATORY

DATE:

TRUTH TABLE:

BCD TO EXCESS 3 CODES:

B3 0 0 0 0 0 0 0 0 1 1

INPUT B1 0 0 1 1 0 0 1 1 0 0

B2 0 0 0 0 1 1 1 1 0 0

B0 0 1 0 1 0 1 0 1 0 1

OUTPUT E2 E1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0

E3 0 0 0 0 0 1 1 1 1 1

E0 1 0 1 0 1 0 1 0 1 0

BCD TO EXCESS-3 CODE

IC7404

8

E0 IC7486

1

2

3

1

2

E1

IC7404 IC7411 1 2 13

IC7432 1 3

2

12

IC7432

E2

IC7408

4 6

1 3 2

IC7408

IC7432

4 6 1 5

2

5

IC7404

6

IC7404

9

B0

5

B1

3

B2

4

B3

3

E3

EXPT NO:

DIGITAL CIRCUITS LABORATORY

DATE:

EXCESS 3 TO BCD CODE:

E3 0 0 0 0 0 1 1 1 1 1

INPUT E1 1 0 0 1 1 0 0 1 1 0

E2 0 1 1 1 1 0 0 0 0 1

E0 1 0 1 0 1 0 1 0 1 0

B3 0 0 0 0 0 0 0 0 1 1

OUTPUT B1 0 0 1 1 0 0 1 1 0 0

B2 0 0 0 0 1 1 1 1 0 0

B0 0 1 0 1 0 1 0 1 0 1

EXCESS-3 TO BCD CODE

IC7404

8

IC7404

6

IC7404

4

E0 9

E1 5

E2 3

E3

B0 IC7486 1

B1

3 2

IC7408 1

IC7432

3 2 1

3

IC7411

2

IC7432

1 2 13

12

4 6 5

B2

IC7411 3 4 5

6

IC7408 IC7432

1 3 2

1 3

IC7411 1 2 13

2 12

RESULT: Thus the Code Converters were designed and implemented.

B3

EXPT NO:

DIGITAL CIRCUITS LABORATORY

4 BIT BINARY ADDER / SUBTRACTOR

AIM:

To design and implement 4 bit parallel binary adder and Subtractor.

APPARATUS REQUIRED:

PROCEDURE: 1. The connections are made as per the circuit diagram. 2. Apply the binary inputs for A and B. 3. Observe the output for the corresponding input .

PIN Diagram

DATE:

EXPT NO:

DIGITAL CIRCUITS LABORATORY

DATE:

4 BIT BINARY ADDER/SUBTRACTOR B3

1

IC7486 3 2

B2

4

IC7486 6 5

B1

9

IC7486 8

B0

12

10

A0 A3 A1 A2 A3

IC7486 11

Cin

14

2

15

6

9

SUM1 C0 B1 SUM2 B2 B3 SUM3 B4 A1 SUM4 A2 A3 C4 A4

GND/VCC

13 11 7 4 16 10 8 3 1

13

S0 S1 S2 S3 Cout RESULT: Thus the 4 bit binary adder and Subtractor circuit was designed and implemented.

EXPT NO:

DIGITAL CIRCUITS LABORATORY

BCD ADDER

AIM: To design and implement BCD adder.

APPARATUS REQUIRED:

PROCEDURE: 1. The connections are made as per the circuit diagram. 2. Apply the binary inputs for X and Y. 3. Observe the output for the corresponding input .

DATE:

EXPT NO:

DIGITAL CIRCUITS LABORATORY

DATE:

BCD ADDER

X0

Y2

X1

Y1

X2

Y0

X3 13 11 7 4 16 10 8 3 1

Y3

14

15

2

6

9

SUM1 C0 B1 SUM2 B2 B3 SUM3 B4 A1 SUM4 A2 A3 C4 A4

0

IC 7408 1 3 2 5

4

2

1 3

IC 7432

0

14

15

2

6

9

SUM1 C0 B1 SUM2 B2 B3 SUM3 B4 A1 SUM4 A2 A3 C4 A4

0

13 11 7 4 16 10 8 3 1

6

IC 7432

S0 S1 S2 S3

RESULT: Thus the BCD adder circuit was designed and implemented

Cout

EXPT NO:

DIGITAL CIRCUITS LABORATORY

DATE:

MULTIPLEXER AND DEMULTIPLEXER AIM: To Design and Implement Multiplexer, DeMultiplexer using logic gates and MSI devices.

APPARATUS REQUIRED:

PROCEDURE: 1. The connections are made as per the circuit diagram. 2. Give the logical inputs as per the truth table. 3. The corresponding output is verified with their truth table.

EXPT NO:

DIGITAL CIRCUITS LABORATORY

DATE:

TRUTH TABLE: MULTIPLEXER

INPUT S0 0 0 1 1

OUTPUT Y D0 D1 D2 D3

S1 0 1 0 1

MULTIPLEXER

IC7404

4

IC7404

2

3

S0

1

S1

IC7411

D0

1 2 13

12

IC7432 1 3 2

IC7411

D1

3 4 5

IC7432

6 9

8 10

IC7411

D2

9 10 11

8

IC7432 4 6 5

IC7411

D3

1 2 13

12

Y

EXPT NO:

DIGITAL CIRCUITS LABORATORY

DATE:

TRUTH TABLE: DEMULTIPLEXER INPUT A 0 0 1 1

D 1 1 1 1

B 0 1 0 1

OUTPUT D1 0 1 0 0

D0 1 0 0 0

D2 0 0 1 0

D3 0 0 0 1

DEMULTIPLEXER

IC7404

4

IC7404

2

3

S0

1

S1

IC7411

D0

9 10 11

D1

3 4 5

D2

9 10 11

D3

1 2 13

8

Y0

6

Y1

8

Y2

12

Y3

IC7411

IC7411

IC7411

RESULT: Thus the Multiplexer circuit is designed and implemented.

EXPT NO:

DIGITAL CIRCUITS LABORATORY

ENCODER AND DECODER AIM: To Design and Implement encoder and decoder using logic gates .

APPARATUS REQUIRED:

S.No

Components IC trainer kit. OR Gate 3 Input AND Not Gate Patch chords

Specification IC 7432 IC 7411 IC 7404

Quantity 1 2 2 1 35

PROCEDURE: 1. The connections are made as per the circuit diagram. 2. Give the logical inputs as per the truth table. 3. The corresponding output is verified with their truth table.

DATE:

EXPT NO:

DIGITAL CIRCUITS LABORATORY

DATE:

TRUTH TABLE: ENCODER

A0 1 0 0 0 0 0 0 0

A1 0 1 0 0 0 0 0 0

A2 0 0 1 0 0 0 0 0

A3 0 0 0 1 0 0 0 0

INPUT A4 0 0 0 0 1 0 0 0

A5 0 0 0 0 0 1 0 0

A6 0 0 0 0 0 0 1 0

A7 0 0 0 0 0 0 0 1

OUTPUT D1 0 0 1 1 0 0 1 1

D0 0 0 0 0 1 1 1 1

D2 0 1 0 1 0 1 0 1

ENCODER (OCTAL TO BINARY) A4 A5 A6 A7 IC7432 2

1

IC7432

3

IC7432

10

9 8

D0

6

D1

3

D2

5

4 6

IC7432 13

12

IC7432

11

IC7432

5

4

2

1 3

IC7432 10

9 8

IC7432 IC7432

12 11

2

1

13

A0 A1 A2 A3

EXPT NO:

DIGITAL CIRCUITS LABORATORY

DATE:

TRUTH TABLE: DECODER I0 0 0 0 0 1 1 1 1

INPUT I1 0 0 1 1 0 0 1 1

I2 0 1 0 1 0 1 0 1

A0 1 0 0 0 0 0 0 0

A1 0 1 0 0 0 0 0 0

OUTPUT A3 A4 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0

A2 0 0 1 0 0 0 0 0

A5 0 0 0 0 0 1 0 0

A6 0 0 0 0 0 0 1 0

DECODER (BINARY TO OCTAL) IC7404

5 6

IC7404

3

I2

4

2

IC7404

I1 1

I0

IC7411 1 2 13

12

A0

IC7411 3 4 5

6

A1

IC7411 9 10 11

8

A2

IC7411 1 2 13

12

A3

IC7411 3 4 5

6

A4

IC7411 9 10 11

1 2 13

8

A5

IC7411 12

A6

IC7411 3 4 5

6

RESULT: Thus the encoder and decoder circuit is designed and implemented.

A7

A7 0 0 0 0 0 0 0 1

EXPT NO:

DIGITAL CIRCUITS LABORATORY

ASYNCHRONOUS COUNTER

AIM:

To Design and Implement 4-bit ripple counter.

APPARATUS REQUIRED:

PROCEDURE:

1. The connections are made as per the circuit diagram. 2. Give the logical inputs as per the truth table. 3. The corresponding output is verified with their truth table. PIN DIAGRAM FOR IC 7476

DATE:

EXPT NO:

DIGITAL CIRCUITS LABORATORY

DATE:

LOGIC DIAGRAM:

TRUTH TABLE: CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

QA 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0

QB 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0

QC 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

QD 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

EXPT NO:

DIGITAL CIRCUITS LABORATORY

DATE:

EXPT NO:

DIGITAL CIRCUITS LABORATORY

DATE:

RESULT: Thus the Asynchronous Counter circuits are designed and verified with their truth table.

EXPT NO:

DIGITAL CIRCUITS LABORATORY

SYNCHRONOUS COUNTER AIM:

To Design and Implement 3-bit Synchronous counter.

APPARATUS REQUIRED:

PROCEDURE: 1. The connections are made as per the circuit diagram. 2. Give the logical inputs as per the truth table. 3. The corresponding output is verified with their truth table.

STATE DIAGRAM:

DATE:

EXPT NO:

STATE TABLE:

DIGITAL CIRCUITS LABORATORY

DATE:

EXPT NO:

DIGITAL CIRCUITS LABORATORY

DATE:

K-MAP:

LOGIC DIAGRAM:

RESULT: Thus the Synchronous Counter circuits are designed and verified with their truth table.

EXPT NO:

DIGITAL CIRCUITS LABORATORY

SHIFT REGISTERS AIM: To Design a 4bit Shift Register using flip-flops. (1). Serial In Serial Out (2). Serial In Parallel Out (3). Parallel In Parallel Out.

APPARATUS REQUIRED:

PROCEDURE: 1. The connections are made as per the circuit diagram. 2. Give the logical inputs as per the truth table. 3. The corresponding output is verified with their truth table.

DATE:

EXPT NO:

DIGITAL CIRCUITS LABORATORY

SERIAL IN SERIAL OUT:

TRUTH TABLE: CLK 0 1 2 3 4

SERIAL IN PARALLEL OUT:

DATA 1 1 0 0 0

QD 0 0 0 0 1

DATE:

EXPT NO:

DIGITAL CIRCUITS LABORATORY

DATE:

TRUTH TABLE: CLK 0 1 2 3 4

DATA 1 1 0 0 0

QA 0 1 0 0 0

QB 0 0 1 0 0

QC 0 0 0 1 0

QD 0 0 0 0 1

PARALLEL IN PARALLEL OUT:

TRUTH TABLE:

CLOCK 0 1

D1 1 1

D2 1 1

D3 0 0

D4 0 0

QA 0 1

QB 0 1

QC 0 0

QD 0 0

EXPT NO:

DIGITAL CIRCUITS LABORATORY

DATE:

PARALLEL IN SERIAL OUT:

RESULT: Thus the Shift Registers circuits are designed and verified with their truth table.