Acer Aspire e1-421 - Quanta Zqz - Rev 1a

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Short Description

Esquema elétrico...

Description

1

2

3

4

PCB STACK UP

5

7

8

ZQZ SYSTEM DIAGRAM

LAYER 1 : TOP LAYER 2 : GND LAYER 3 : IN1

DDR3- SODIMM2

DDR3- SODIMM1

PAGE 7

PAGE 6

LAYER 4 : IN2

DDR3 Channel A

LAYER 5 : VCC A

6

LAYER 6 : BOT

FT1

 FAN SCH.

CPU (PROCHOT) 32.768KHz

CRT

TDP~18W 

LVDS

PAGE 23

25MHz

HDMI HDMI

PAGE 14

CRT

PAGE 13

LVDS LVDS

PAGE 13

eDP

PAGE 13

A

19mmX19mm 413pin BGA

E.C. (CPUFAN#)

eDP@ -----> eDP panel lvds@ -----> lvds panel

HDMI

AMD Brazos

UMA only 

CPU SideBand TemperatureSense I2C

PAGE 3,4,5

HT3 1.8GHz

PCI-Expresss

AMD

B

P0

LAN

B

Hudson-M3

Atheros AR8151

24.5mmX24.5mm, 656pin BGA

(10/100/1000)

TDP~4.7W

PAGE 16

25MHz

RJ45 PAGE 16 P0

C

SATA0 150MB

SATA - HDD CHARGER (BQ24707A) PAGE 26

PAGE 28

CPU 

PAGE 8,9,10,11,12 PCLK_DEBUG

LPC

1.-05V (TPS51211) PAGE30

NB 

CLK_PCI_775

CPU SideBand TemperatureSense I2C

DDR 1.5V(TPS51216)

PAGE 21

PAGE 13

P4

3 Gb/s

PAGE 18

Web-Camera C

PAGE 21

SATA1 150MB

SATA - ODD

AMD CPU CORE (OZ8380)

      C       F       F

P13

Blue Tooth

on board x1

3 Gb/s

PAGE 18

P9

USB2.0 Port

Azalia

Winbond KBC

Audio CODEC

NPCE885

Conexant CX20584-11Z PAGE 19

PAGE 31

PAGE 24

P10

Mini Card

CardReader

WLAN & Debug & mSATA

AU6435

PAGE 17

USB BOARD USB2.0 Ports x2 PAGE

PAGE 15

12MHz

SYSTEM 5V/3V (RT8223M) PAGE 27 D

D

Keyboard TouchPad

1.1V(TPS51211) PAGE 29

SPI ROM

INT MIC

AUDIO CONN

Speaker CN

(H.P./ MIC)

PAGE 23

PAGE 10

PAGE 20

PAGE 20

PAGE 20

Quanta Computer Inc. PROJECT : ZQZ

Discharge /Thermal protec PAGE 31 1

S i ze

Docum ent Num ber

Date:

Thursday, February 23, 2012

Rev 1A

Block Diagram 2

3

4

5

6

7

Sheet

1 8

of

32

5

4

INDEX  PAGE#

3

2

1

02

Power Sequence DESCRIPTION

NOTE

AC IN

1

BLOCK DIAGRAM

2

SYSTEM INFORMATION

3

ONTARIO MEM & PCIE I/F(1/3)

4

ONTATIO DISPLAY/CLK/MI(2/3)

5

ONTARIO POWER & DECOUP(3/3)

6

DDR3 SO-DIMM (STD)

7

DDR3 SO-DIMM (STD)

Hudson M1 SM BUS 3V/5VPCU SB820 SMBUS

8

08 -- FCH 1/5(GPIO/USB/AZ)

9

09 -- FCH 2/5(ACPI/PCI/CLK)

10

10 -- FCH 3/5(SATA/VGA/GND/SPI)

11

11 -- FCH 4/5(POWER)

12

12 -- FCH 5/5(Strap/PWRGD)

13

13-- CRT/LVDS&CCD

14

14 -- HDMI_CONN

15

15 -- CardReader AU6435-GDL

16

16 -- LAN AR8151

C

B

17

17 -- MINI PCIE

18

18 -- SATA-HDD/ODD

19

19--Codec(CX20584-21Z)

20

20--AUDIO-JACK/MDC/MIC

21

21 -- INT&EXT USB/BT

22

22 -- LED/ EMI/ Screw Hole& Nut

23

23 -- KB/TP/FAN

24

24 -- NPCE885/FLASH

25

25 -- NPCE895L

26

26 -- Charger (BQ24707A)

27

27 -- SYSTEM 5V/3V (RT8223M)

28

28 -- CPU_CORE_Br azos (OZ8380 )

29

29 -- +1.1V_S5(TPS51211)

30

30 -- +1.05V(TPS51211)

31

31 -- DDR 1.5V(TPS51216)

32

32 -- +1.8V/Discharge /Thermal

33

33--CHANGE LIST

Pin NO.

SMBUS Function Define

NBSWON#

D

DNBSWON#

PCLK_SMB

AD22

PDAT_SMB

AE22

D

DDR / RFID

(+3V) S5_ON/S5 RSMRST#

SB_SMBCLK1

F5

SB_SMBDATA1

F4

not used

(+3V_S5)

PCIE_WAKE#

SB_SCLK2

D25

SB_SDATA2

F23

not used

(+3V_S5)

SUSC SUSB

SB_SCLK3

B26

SB_SDATA3

E26

not used

(+3V_S5) SUSON MAINON

SB_SCLK3

B26

SB_SDATA3

E26

not used

(+3V_S5)

VR_ON

C

CPU_CORE

KBC(EC SM BUS

VRM_PWRGD KBC SMBUS

Pin NO.

MBCLK

110

MBDATA

111

SMBUS Function Define

HWPG ECPWROK

Battery

(+3VPCU) SB_PWRGD_IN CPU RESET

MBCLK_THRM

115

MBDATA_THRM

116

Thermal

(+3VPCU)

CPU POWER OK

B

A

A

Quanta Computer Inc. PROJECT : ZQZ Si ze

Document Number

Dat e:

Thursday, February 23, 2012

Rev 1A

System Information 5

4

3

2

1

Sheet

2

of

32

1

2

3

4

5

M_A_DQ[0..63]

6

{6,7}

M_A_A0 M _A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M _A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

A

{6,7} M_A_BS[2..0]

R17 H19 J17 H18 H17 G17 H15 G18 F19 E19 T19 F17 E18 W17 E16 G15

 

M_ADD0

M_DATA0

 

M_ADD1

 

M_ADD2

M_DATA2

 

M_ADD3

M_DATA3

 

M_ADD4

M_DATA4

 

M_ADD5

M_DATA5

 

M_ADD6

M_DATA6

 

M_ADD7

M_DATA7

 

M_ADD8

 

M_ADD9

 

M_ADD10

M_DATA9

 

M_ADD11

M_DATA10

 

M_ADD12

M_DATA11

 

M_ADD13

M_DATA12

 

M_ADD14

M_DATA13

 

M_ADD15

M_DATA14

 

M_BANK0

 

M_BANK1

M_DATA16 M_DATA17

ONTARIO (2.0)

M_DATA1

PART 1 OF 5

M_DATA8

M_DATA15

M_A_BS0 R18 M_A_BS1 T18 M_A_BS2 F16

 

M_BANK2

D15 B19 D21 H22 P23 V23 AB20 AA16

 

M_DM0

M_DATA19

 

M_DM1

M_DATA20

 

M_DM2

M_DATA21

 

M_DM3

M_DATA22

 

M_DM4

M_DATA23

 

M_DM5

 

M_DM6

M_DATA24

M_DM7

M_DATA25

M_A_DQSP0 M_A_DQSN0 M_A_DQSP1 M_A_DQSN1 M_A_DQSP2 M_A_DQSN2 M_A_DQSP3 M_A_DQSN3 M_A_DQSP4 M_A_DQSN4 M_A_DQSP5 M_A_DQSN5 M_A_DQSP6 M_A_DQSN6 M_A_DQSP7 M_A_DQSN7

A16 B16 B20 A20 E23 E22 J22 J23 R22 P22 W22 V22 AC20 AC21 AB16 AC16

 

M_DQS_H0

M_DATA27

 

M_DQS_L0

M_DATA28

 

M_DQS_H1

M_DATA29

 

M_DQS_L1

M_DATA30

M_A_CLKP0 M_A_CLKN0 M_A_CLKP1 M_A_CLKN1 M_A_CLKP2 M_A_CLKN2 M_A_CLKP3 M_A_CLKN3

M17 M16 M19 M18 N18 N19 L18 L17

{6,7} M_A_DM[7..0]

M_DATA18

M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

 

M_DATA26

B

C

{6,7} {6,7} {6,7} {6,7} {6,7} {6,7} {6,7} {6,7} {6,7} {6,7} {6,7} {6,7} {6,7} {6,7} {6,7} {6,7} {6} {6} {6} {6} {7} {7} {7} {7}

 

M_DQS_H2

 

M_DQS_L2

 

M_DQS_H3

 

M_DQS_L3

 

M_DQS_H4

 

M_DQS_L4

 

M_DQS_H5

 

M_DQS_L5

M_DATA31

   F    /    I    Y    R    O    M    E    M

M_DATA32 M_DATA33 M_DATA34 M_DATA35 M_DATA36 M_DATA37

 

M_DQS_H6

M_DATA38

 

M_DQS_L6

M_DATA39

 

M_DQS_H7

 

M_DQS_L7

M_DATA40 M_DATA41

 

M_CLK_H0

M_DATA42

 

M_CLK_L0

M_DATA43

 

M_CLK_H1

M_DATA44

 

M_CLK_L1

M_DATA45

 

M_CLK_H2

M_DATA46

 

M_CLK_L2

M_DATA47

 

M_CLK_H3

 

M_CLK_L3

M_DATA48 M_DATA49

{6,7} M_A_RST# {6,7} M_A_EVENT#

L23 N17

 

M_RESET_L

M_DATA50

M_A_EVENT#

 

M_EVENT_L

M_DATA51

M_A_CKE0 M_A_CKE1

F15 E15

 

M_CKE0

M_DATA54

 

M_CKE1

M_DATA55

M_DATA52 M_DATA53

{6,7} M_A_CKE0 {6,7} M_A_CKE1

M_DATA56 M_DATA57

D

{6} {6} {7} {7}

M_A_ODT0 M_A_ODT1 M_A_ODT2 M_A_ODT3

W19 V15 U19 W15

 

M0_ODT0

M_DATA58

 

M0_ODT1

M_DATA59

 

M1_ODT0

M_DATA60

 

M1_ODT1

M_DATA61

{6} {6} {7} {7}

M_A_CS#0 M_A_CS#1 M_A_CS#2 M_A_CS#3

T17 W16 U17 V16

 

M0_CS_L0

 

M0_CS_L1

 

M1_CS_L0

 

M1_CS_L1

{6,7} M_A_RAS# {6,7} M_A_CAS# {6,7} M_A_WE#

U18 V19 V17

 

M_RAS_L

M_DATA62

   

M_DATA63

B14 A15 A17 D18 A14 C14 C16 D16

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7

C18 A19 B21 D20 A18 B18 A21 C20

M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15

C23 D23 F23 F22 C22 D22 F20 F21

M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23

H21 H23 K22 K21 G23 H20 K20 K23

M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31

N23 P21 T20 T23 M20 P20 R23 T22

M_A_DQ32 M _A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39

V20 V21 Y23 Y22 T21 U23 W23 Y21

M_A_DQ40 M_A_DQ41 M_A_DQ42 M _A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47

Y20 AB22 AC19 AA18 AA23 AA20 AB19 Y18

M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55

AC17 Y16 AB14 AC14 AC18 AB18 AB15 AC15

M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

M_VREF

M23

M_ZVDDIO_MEM_S

M22

8

03

+1.5VSUS {4,5,6,7,10,11,23,30} VDD_10 {5}

U16E

{6,7} M_A_A[15:0]

7

This page is different AMD Nile A

U16A {16} PCIE_RXP0_LAN {16} PCIE_RXN0_LAN

AA6 Y6

  P_GPP_RXP0

{17} PCIE_RXP1 {17} PCIE_RXN1

AB4 AC4

  P_GPP_RXP1   P_GPP_RXN1

P_GPP_TXN1

AA1 AA2

  P_GPP_RXP2

P_GPP_TXP2

Y4 Y3

  P_GPP_RXP3

VDD_10

R 33 5

2 K/ K/ F_ F_ 4 ON_ZVDD

Y14

P_GPP_TXP0

  P_GPP_RXN0

P_GPP_TXN0 ONTARIO (2.0) PART 2 OF 5

  P_GPP_RXN2

P_GPP_TXP1

   F    /    I    E    I    C    P

  P_GPP_RXN3

P_GPP_TXN2 P_GPP_TXP3 P_GPP_TXN3

  P_ZVDD_10

P_ZVSS

{9} {9}

UMI_RXP0 UMI_RXN0

AA12 Y12

  P_UMI_RXP0

P_UMI_TXP0

  P_UMI_RXN0

P_UMI_TXN0

{9} {9}

UMI_RXP1 UMI_RXN1

AA10 Y10

  P_UMI_RXP1

{9} {9}

UMI_RXP2 UMI_RXN2

AB10 AC10

  P_UMI_RXP2

{9} {9}

UMI_RXP3 UMI_RXN3

AC7 AB7

  P_UMI_RXP3

P_UMI_TXP3

  P_UMI_RXN3

P_UMI_TXN3

P_UMI_TXP1

   F    /    I    I    M    U

  P_UMI_RXN1

  P_UMI_RXN2

P_UMI_TXN1 P_UMI_TXP2 P_UMI_TXN2

AB6 PCIE_TXP0_LAN_C AC6 PCIE_TXN0_LAN_C

C361 C361 C362 C362

0.1u/1 0.1u/10V_ 0V_4 0.1u/1 0.1u/10V_ 0V_4

PCIE_TXP0_LAN {16} LAN PCIE_TXN0_LAN {16}

AB3 PCIE_TXP1_C AC3 PCIE_TXN1_C

C354 C354 C355 C355

0.1u/1 0.1u/10V_ 0V_4 0.1u/1 0.1u/10V_ 0V_4

PCIE_TXP1 {17} PCIE_TXN1 {17}

WLAN

Y1 Y2 V3 V4 AA14 ON_ZVSS

R 34 34 5

1 .2 .2 7K 7K /F /F _4 _4

AB12 UMI_TXP0_C C386 AC12 UMI_TXN0_C

0.1u/1 0.1u/10V_ 0V_4 4 C387 C387

0.1u/1 0.1u/10V_ 0V_4

UMI_TXP0 {9} UMI_TXN0 {9}

AC11 UMI_TXP1_C C380 AB11 UMI_TXN1_C

0.1u/1 0.1u/10V_ 0V_4 4 C384 C384

0.1u/1 0.1u/10V_ 0V_4

UMI_TXP1 {9} UMI_TXN1 {9}

AA8 UMI_TXP2_C C373 UMI_TXN2_C Y8

0.1u/1 0.1u/10V_ 0V_4 4 C376 C376

0.1u/1 0.1u/10V_ 0V_4

UMI_TXP2 {9} UMI_TXN2 {9}

AB8 UMI_TXP3_C C366 AC8 UMI_TXN3_C

0.1u/1 0.1u/10V_ 0V_4 4 C371 C371

0.1u/1 0.1u/10V_ 0V_4

UMI_TXP3 {9} UMI_TXN3 {9}

B

SP@FT1_ONTARIO

+M_VREF

+1.5VSUS +1.5VSUS

R368 1K/F_4

R 37 37 2

+1.5VSUS

R 36 36 9

+1.5VSUS

* 2. 2. 2K 2K _4 _4

R367 1K/F_4

C404

C403

0.1u/10V_4

1000p/50V_4

    2

* 1K 1K /F /F _4 _4

M_A_EVENT#

1

Q20 *MMBT3904 R370 3

*0_4

APU_MEMHOT#

C

Brazos APU B0 CKE Race condition issue workaround : a resistor of 68 ohms between M_CKE [ 1:0 ] and ground eliminates the floating signal . M_A_CKE0 M_A_CKE1

R113 *68_4

+M_VREF

R125 *68_4

M_CAS_L M_WE_L

SP@FT1_ONTARIO

?

P/N AJ01200TT00 AJ01200TT01 AJ01800VT00 AJ01800VT01

39.2/F_4 3 9. 9. 2/ 2/ F_ F_ 4

R366 R 36 36 6

+1.5VSUS

D

Item Description CPU(413P)EM1200GBB22GV 1.4G(BGA) CPU(413P)EM1200GBB22GV 1.4G(BGA)STN BSQ CPU(413P)EM1800GBB22GV 1.7G(BGA) CPU(413P)EM1800GBB22GV 1.7G(BGA)STN BSQ

Quanta Computer Inc. PROJECT : ZQZ Size

Document Number

Dat e:

Thursday, February 23, 2012

ONTARIO MEM & PCIE I/F(1/3) 1

{8}

2

3

4

5

6

7

Sheet

3

of 8

32

Rev 1A

+1.8V

+1.8V +3V R 20 8 R 20 7

1 K/ F_ 4 1 K/ F_ 4

04

{5,23,31} {5,6,7,8,9,10,11,12,13,14,15,17,18,19,20,22,23,24,26,27,28,29,30,31}

APU_SVC APU_SVD

R199

300_4

LDT_RST#

R298

300_4

APU _PWRGD

U16B

ANALOG/DISPLAY/MISC

{14} TX2_HDMI+ {14} TX2_HDMI-

+3V

R 30 3 R 21 4

R 30 2 R302

1 K/ F_ 4 1 K/ F_ 4

 

1K/F_4 1 K/ F_ 4

INT_CRT_RED R 33 8 INT_CRT_GRE R 33 9 INT_CRT_BLU R 34 3

H_PROCHOT#

1 50 F / _4 1 50 F / _4 1 50 F / _4

INT_EDIDCLK R314 R 31 4 R304 R 30 4 INT_EDIDDATA

PEG_HDMI_TXDP2 PEG_HDMI_TXDN2

0.1u/10V_4   C367 C372 C372

A8 B8

PEG_HDMI_TXDP1 PEG_HDMI_TXDN1

B9 A9

 

TDP1_TXP1

 

TDP1_TXN1

{14} TX0_HDMI+ {14} TX0_HDMI-

PEG_HDMI_TXDP0 D10 PEG_HDMI_TXDN0 C10

 

TDP1_TXP2

0.1u/10V_4 0.1u/10V_4

0.1u/10V_4   C379 C381 C381

 

TDP1_TXN2

{14} {14}

0.1u/10V_4 0.1u/10V_4

0.1u/10V_4   C382 C385 C385

0.1u/10V_4 0.1u/10V_4

C375 C375

PEG_HDMI_TXCP PEG_HDMI_TXCN

{8}

SB_SCLK3

Q6 Q6 R 43

{24} APU_SIC_EC

 

SB_SDATA3

{13} INT_TXLOUTP1 {13} INT_TXLOUTN1

D6 C6

 

LTDP0_TXP1

LTDP0_HPD

D3

 

LTDP0_TXN1

{13} INT_TXLOUTP0 {13} INT_TXLOUTN0

A6 B6

 

LTDP0_TXP2

 

LTDP0_TXN2

{13} INT_TXLCLKP {13} INT_TXLCLKN

D8 C8

{9} {9}

CLK_APU_P CLK_APU_N

V2 V1

   

CLKIN_H CLKIN_L

{9} {9}

CLK_DP_P CLK_DP_N

D2 D1

 

DISP_CLKIN_H

 

DISP_CLKIN_L

R 25 5 R 29 7

H_PROCHOT# APU_THERMTRIP# APU_ALERT#

APU_SIC

*2N7002K *2 N7 00 2K

APU_TDI APU_TDO APU_TCK APU _TMS APU_TRST# DBRDY DBREQ#

   C    A    D    A    G    V

   K    L    C

PWROK

U1 U2 T2

 

PROCHOT_L

 

THERMTRIP_L

 

ALERT_L

TEST18 TEST19 TEST25_H

R 41

* Sh or _ t 4

3

TDO TCK

TEST28_H TEST28_L TEST31

APU_TCK

TMS

APU_TMS

TEST33_H

   G    A    T    J

 APU_TRST# TRST_L  DBRDYDBRDY  

DBREQ_L

F4 G1 F3

 

VDDCR_NB_SENSE

 

VDDIO_MEM_S_SENSE

F1

 

VSS_SENSE

B4 W11 V5

   

RSVD_1 RSVD_2

 

RSVD_3

TEST33_L TEST34_H TEST34_L TEST35 TEST36

VDDCR_CPU_SENSE

TEST37

TEST38 DMAACTIVE_L

INT_CRT_GRE {13} INT_CRT_BLU {13}

INT_DDCCLK {13} INT_DDCDATA {13}

D12 DAC_RSET

R75

499/F_4

T30 T28 T2 T4 T16 APU_BP3_SCANSHIFTEND_USDATA1 T27 APU_BP2_SCANSHIFTEN_USDATA0 T31 TEST18 R 21 7 1 K/ F_ 4 TEST19 R 22 0 1 K/ F_ 4 R226   510/F_4 R 20 9 R209   510/F_4 5 10 /F _4 APU_TEST28_H_PLLCHARZ T26 APU_TEST28_L_PLLCHARZ T3 APU_TEST31_MEM_TEST T36 APU_TEST33_H_M_CLKTST_H C187 0.1u/1 0V_4 R81 APU_TEST33_H_M_CLKTST_L C176 0.1u/1 0V_4 R76 APU_TEST34_H_TSTCLKIN_H T20 APU_TEST34_L_TSTCLKIN_L T22 APU_TEST35 R 22 3 * 1K /F _4 APU_TEST36 R 21 0 1 K_ 4 +1.8V APU_TEST37_GIO_TSTDTM0_CLKINIT T1

R300

*Short _4

T29 ALLOW_LDTSTP {9}

ONTARIO(2.0) PART3 OF5

VSS_SENSE R 29 5 VDDCR_CPU_SENSE R 29 6

*2N7002K *2 N7 00 2K

+1.8V

51/F_4 51/F_4

UNNAMED_7_CAP_I33 7_B

APU_FDO ON_DMAACTIVE#

K3 T1

 

APU_THERMDA APU_THERMDC APU_TEST6_DIRECRACKMON APU_BP0_TSTCLK_USCLK0

R1 R2 R6 T5 E4 K4 L1 L2 M2 K1 K2 L5 M5 M21 J18 J19 U15 T15 H4 N5 R5

R206 1K/F_4

?

APU_SID

1  

R 40

TEST25_L

   T    S    E    T

APU_TDO

 

INT_CRT_HSYNC {13} INT_CRT_VSYNC {13}

TEST6

   L    R    T    C

{13}

F2 D4

TEST16 TEST17

TDI

INT_eDPI_HPD

DAC_SCL

TEST14 TEST15

APU_TDI

INT_HDMI_HPD {14} INT_EDIDCLK {13} INT_EDIDDATA {13} INT_eDPI_HPD

E1 E2

TEST4 TEST5

INT_LVDS_BLON {13} INT_LVDS_DIGON {13} INT_LVDS_PWM {13}

1 00 K_ 4

HDMI_DDCCLK {14} HDMI_DDCDATA {14}

DAC_BLUEB

   R    E    S

SIC SID RESET_L

 

* Sh or t_ 4 * Sh or t_ 4 * Sh or t_ 4 R 20 5

DAC_HSYNC DAC_VSYNC

DAC_ZVSS

 

1 50 /F _4 R 23 7 R 20 4 R 22 2

INT_CRT_RED {13}

DAC_SDA

SVC SVD

R 22 1

C12 D13 A12 B12 A13 B13

DAC_RED DAC_REDB DAC_GREEN DAC_GREENB DAC_BLUE

LTDP0_TXN3

T3 T4

N2 N1 P1 P2 M4 M3 M1

   0    T    R    O    P    Y    A    L    P    S    I    D

LTDP0_TXP3

 

P3 P4

* Sh or t_ 4 LDT_RST#_R * Sh or t_ 4 APU_PWRGD_R

{9,24} H_PROCHOT#

 

J1 J2

* Sh or _ t 4

Q7 Q7 {24} APU_SID_EC

A3 B3

LTDP0_TXP0 LTDP0_TXN0

SP@FT1_ONTARIO {8}

C1

TDP1_TXN3

R45 1K/F_4

A

TDP1_HPD LTDP0_AUXP LTDP0_AUXN

TDP1_TXP3

    2 *0_4

TDP1_AUXN

B2 C2

TDP1_AUXP

   

+3V

R35

G2 H2 H1

 

* Sh or _ t 4 R 42

H3

DP_BLON

 

    2 1

DP_ZVSS

DP_DIGON DP_VARY_BL

B5 A5

APU_SIC APU_SID

3

   1    T    R    O    P    Y    A    L    P    S    I    D

A10 B10

TXC_HDMI+ TXC_HDMI-

{9,23} LDT_RST# {9,23} APU_PWRGD

*0_4

   C    S    I    M    P    D

{13} INT_TXLOUTP2 {13} INT_TXLOUTN2

+3V

R37

TDP1_TXP0 TDP1_TXN0

C378

APU_SVC APU_SVD

R44 1K/F_4

   

0.1u/10V _4 0.1u/10V_4

{14} TX1_HDMI+ {14} TX1_HDMI-

APU_THERMTRIP# APU_ALERT#

+3V [email protected]/F_4 vd s @4 .7 K/ F_ 4 l vd s @4 .7 K/ F_ 4 [email protected]/F_4

0.1u/10V_4 0.1u/10V_4

* Sh or t_ 4 * Sh or t_ 4

R299 1K/F_4

CPU_VDD0_FB_L {27} CPU_VDD0_FB_H {27}

A

+1.8V

+1.8V

+1.8V

0831---follow AMD request for HDMI function

* Sh or _ t 4 +3V

VDDIO_SUS_SENSE

R2 59

* 0_ 4

VSS_SENSE VDDCR_NB_SENSE

R 29 4 R 29 3

* Sh or t_ 4 * Sh or t_ 4

* 10 K/ F_ 4 CNTR_VREF

R 21 5

    2

+1.5VSUS {3,5,6,7,10,11,23,30} CPU_VDDNB_FB_L {27} CPU_VDDNB_FB_H {27}

LDT_ RST #

R262 10K/F_4

1

R202 *1K/F_4

Q12 *MMBT3904 CPU_LDT _RST _HT PA# 3

Can remove on MP------>LX

DIFFERENTIALROUTING     2

R 29 1

{25,26,31} SYS_SHDN#

* Sh or t_ 4

Q14 MMST3904-7-F 3

APU_THERMTRIP#

1

VID Override Circuit +1.8V +3V

R292 *10K/F_4

R 30 9

{8} FCH_THERMTRIP#

*0 _4

    2 Q15 *MMST3904-7-F 3

R48 *300_4 APU_SVC

R225

0_4

APU_SVD

R224

0_4

APU_PWRGD

R 25 6

* 0_ 4

R47 *300_4

R258 *2.2K/F_4

CPU_SVC {27}

1

for normal operation openall switches

CPU_SVD {27} CPU_PWRGD_SVID_REG

R49 *220/F_4

R46 *220/F_4

CPU_PWRGD_SVID_REG

{27}

R257 *220/F_4

+3V

0830---add circuit

{23,24} SML1ALERT#

R 23 0

R211 10K/F_4

* Sh or t_ 4

    2 Q11 MMST3904-7-F 3

1

+ 1. 8V

R301 *10K/F_4

SML1ALERT#

R2 34

*0 _4

HDT+ Connector

1

+1.8V

HDT+ HEADER /PLACE ON TOP

R212 1K/F_4

+3V

    2 Q13 *MMST3904-7-F 3

+ 1. 8V

APU_ALERT#

H_PROCHOT#

APU_TRST#

+1.8V

+1.8V

CN9

R 23 1 R 25 4 R 28 5 R 31 0

* Sh o tr _4 HDT_TRST# 1 0K _4 1 0K _4 1 0K _4

1 3 5 7 9 11 13 15 17 19

CPU_VDDIO GND GND GND CPU_TRST_L CPU_DBRDY3 CPU_DBRDY2 CPU_DBRDY1 GND CPU_VDDIO

2 4 6 CPU_TDI 8 CPU_TDO CPU_PWROK_BUF 10 CPU_RST_L_BUF 12 CPU_DBRDY0 14 CPU_DBREQ_L 16 18 CPU_PLLTEST0 20 CPU_PLLTEST1 CPU_TCK

CPU_TMS

R 20 1 R 21 3 R 21 6

APU_TCK APU_TMS APU_TDI

    5

1 K/ F_ 4 1 K/ F_ 4 1 K/ F_ 4

C350 0.1u/10V_4

U15

VCC

APU_TDO

LDT _RST #_R

1 1A

1Y 6

LDT _RST# _BUF

R2 65

1 K/F _4

APU_PWRGD

3 2A

2Y 4

APU_PWRGD_BUF R2 64

1 K/F _4

APU_PWRGD_BUF LDT_RST#_BUF DBRDY

R 31 5 R219 R 21 9 R218 R2 18

DBREQ# J108_PLLTST0 J108_PLLTST1

1 K/ F_ 4 *Short _4 *Short_4 **Shor S ho rt_ t_4 4

Quanta Computer Inc.

TEST19 TEST18

GND

*SN74LVC2G07DCKR

    2

PROJECT : ZQZ

*HDP+ Size

Document Number

Date:

Thursday,February23,2012

Rev 1A

ONTATIO DISPLAY/CLK/MI(2/3) 1

Sheet

4

of

32

1

+1.5VSUS {3,4,6,7,10,11,23,30} +1.05V {23,29} +1.8V {4,23,31} +3V {4,6,7,8,9,10,11,12,13,14,15,17,18,19,20,22,23,24,26,27, 28,29,30,31} +VCORE {23,27} +NBCORE {27} VDD_10 {3}

+VCORE

11A 440mil viax22

+NBCORE

10A 400mil viax20

+1.5VSUS

U16C

E5 E6 F5 F7 G6 G8 H5 H7 J6 J8 L7 M6 M8 N7 R8

  VDDCR_CPU_1

VDD_18_1

  VDDCR_CPU_2   VDDCR_CPU_3

VDD_18_2 VDD_18_3

  VDDCR_CPU_4

VDD _18_4

  VDDCR_CPU_5

VDD_18_5

  VDDCR_CPU_6

VDD_18_6

  VDDCR_CPU_7

VDD_18_7

1u/6.3V_4

R 20 0

10u/6.3V_8

* sh or t_ 8

+1.8V

C71

C97

C341

C80

C79 C65

1u/6.3V_4

0.1u/10V_4

1u/6.3V_4

10u/6.3V_8 C337

10u/6.3V_8

C93

C340

10u/6.3V_8

  VDDCR_CPU_11   VDDCR_CPU_12   VDDCR_CPU_13

L10

C58 10u/6.3V_8

C18

C59 10u/6.3V_8

10u/6.3V_8 C338

10u/6.3V_8

C75

C120 10u/6.3V_8

10u/6.3V_8

+1.8V

BLM18PG221SN1D(220_1.4A)_6 VDD_18_DAC W9

C339

+VCORE

150mA 10mil viax1

VDDAN_18_DAC

  VDDCR_CPU_14   VDDCR_CPU_15

C19

+VCORE

C107 1u/6.3V_4

1u/6.3V_4 C87 1u/6.3V_4

ONTARIO (2.0)

0.1u/10V_4

PART 4 OF 5

0.1u/10V_4

0.1u/10V_4

C74

1u/6.3V_4 C63

C91 1u/6.3V_4

0.1u/10V_4 C89

C67

+1.05V T15    R    E    W    O    P

VDDPL_10

C98

C64

C66

C88

C83

C68 0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

200mA 10mil viax1 R 32 5

VDDPL_10

U11

C92

0.1u/10V_4 * sh or t_ 6

+NBCORE

+NBCORE

0.1u/10V_4 C364

C111

10u/6.3V_8

C110 +1.05V

1u/6.3V_4

10u/6.3V_8

VDD_10 C76

VDD_10_1 VDD_10_3

G16   VDDIO_MEM_S_1 G19   VDDIO_MEM_S_2 E17   VDDIO_MEM_S_3 J16   VDDIO_MEM_S_4 L16   VDDIO_MEM_S_5 L19   VDDIO_MEM_S_6 N16   VDDIO_MEM_S_7 R16   VDDIO_MEM_S_8 R19   VDDIO_MEM_S_9 W18   VDDIO_MEM_S_10 U16   VDDIO_MEM_S_11

VDD_10_4

5.5A 220mil viax11

U13 W13 V12 T12

10u/6.3V_8 C393

0.1u/10V_4 C159

C134

10u/6.3V_8

R 34 7 R 34 0

* sh or t_ 8 * sh or t_ 8

C144

10u/6.3V_8 C62

10u/6.3V_8

1u/6.3V_4

C147

C129 10u/6.3V_8

10u/6.3V_8

C112 1u/6.3V_4

C118

1u/6.3V_4 C130

1u/6.3V_4

C90

C116 1u/6.3V_4

0.1u/10V_4 C133

1u/6.3V_4

C135

C132 +NBCORE

1u/6.3V_4

+3V 0.1u/10V_4

500mA 20mil viax1 VDD_33

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4 C143

C114

A4

C102

C119

C113

C139

C142

C141

C122 0.1u/10V_4

0.1u/10V_4 SP@FT1_ONTARIO

This page is different AMD Nile

+VCORE

0.1u/10V_4

  VDDCR_CPU_10

E8   VDDCR_NB_1 E11   VDDCR_NB_2 E13   VDDCR_NB_3 F9   VDDCR_NB_4 F12   VDDCR_NB_5 G11   VDDCR_NB_6 G13   VDDCR_NB_7 H9   VDDCR_NB_8 H12   VDDCR_NB_9 K11   VDDCR_NB_10 K13   VDDCR_NB_11 L10   VDDCR_NB_12 L12   VDDCR_NB_13 L14   VDDCR_NB_14 M11   VDDCR_NB_15 M12   VDDCR_NB_16 M13   VDDCR_NB_17 N10   VDDCR_NB_18 N12   VDDCR_NB_19 N14   VDDCR_NB_20 P11   VDDCR_NB_21 P13   VDDCR_NB_22

05

1u/6.3V_4 C70

  VDDCR_CPU_8   VDDCR_CPU_9

VDD_10_2

2A 80mil viax4

2A 80mil viax4

VDD_18

U8 W8 U6 U9 W6 T7 V7

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

?

C356 1u/6.3V_4 +1.5VSUS +1.5VSUS

GND

1u/6.3V_4 A

C190 C153 1u/6.3V_4

C160

C209 10u/6.3V_8

C180 1u/6.3V_4

180P/50V_4

+1.5VSUS

U16D

A7   B7   B11   B17   B22   C4   D5   D7   D9   D11   D14   B15   D17   D19   E7   E9   E12   E20   F8   F11   F13   G4   G5   G7   G9   G12   G20   G22   H6   H11   H13   J4   J5   J7   J20   K10   K14   L4   L6   L8   L11   L13   L20   L22   M7   N4   N6   N8   N11  

VSS_1

ONTARIO (2.0)

VSS_50

VSS_2

PART 5 OF 5

VSS_51

VSS_3

VSS_52

VSS_4

VSS_53

VSS_5

VSS_54

VSS_6

VSS_55

VSS_7

VSS_56

VSS_8

VSS_57

VSS_9

VSS_58

VSS_10

VSS_59

VSS_11

VSS_60

VSS_12

VSS_61

VSS_13

VSS_62

VSS_14

VSS_63

VSS_15

VSS_64

VSS_16

VSS_65

VSS_17

VSS_66

VSS_18

VSS_67

VSS_19

VSS_68

VSS_20

VSS_69

VSS_21

VSS_70

VSS_22

VSS_71

VSS_23

VSS_72

VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29

VSS_73 VSS_74

   D    N    U

VSS_75 VSS_76

   O    R    G

VSS_77 VSS_78

VSS_30

VSS_79

VSS_31

VSS_80

VSS_32

VSS_81

VSS_33

VSS_82

VSS_34

VSS_83

VSS_35

VSS_84

VSS_36

VSS_85

VSS_37

VSS_86

VSS_38

VSS_87

VSS_39

VSS_88

VSS_40

VSS_89

VSS_41

VSS_90

VSS_42

VSS_91

VSS_43

VSS_92

VSS_44

VSS_93

VSS_45

VSS_94

VSS_46

VSS_95

VSS_47

VSS_96

VSS_48

VSS_97

VSS_49

SP@FT1_ONTARIO

A

C210 10u/6.3V_8

VSSBG_DAC

N13 N20 N22 P10 P14 R4 R7 R20 T6 T9 T11 T13 U4 U5 U7 U12 U20 U22 V8 V9 V11 V13 W1 W2 W4 W5 W7 W12 W20 Y5 Y7 Y9 Y11 Y13 Y15 Y17 Y19 AA4 AA22 AB2 AB5 AB9 AB13 AB17 AB21 AC5 AC9 AC13 A11

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4 C208

C156 C152 180P/50V_4

C177

C157

C155

C165

C188

C181 0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

place capacitors under BGA EMC CAPS +1.5VSUS

C154 180P/50V_4

C172 180P/50V_4

VDD_18

C96 180P/50V_4

+VCORE

180P/50V_4 C69

+NBCORE

180P/50V_4 C72

VDDAN_18_DAC

C82 180P/50V_4

C106 180P/50V_4

C115 180P/50V_4

VDD_10

+1.5VSUS

C128 180P/50V_4

0.1u/10V_4 C151

VDDPL_10

C131 180P/50V_4

C109 180P/50V_4

C189 0.1u/10V_4

+3V

C351 0.1u/10V_4

?

GND GND

Quanta Computer Inc. PROJECT : ZQZ Size

Document Number

Rev 1A

ONTARIO POWER & DECOUP(3/3) Date: 1

Thursday, February 23, 2012

Sheet

5

of

32

1

2

3

4

5

6

7

+1.5VSUS

0830--P/N and footprint are follow ZR7B

8

06

{3,4,5,7,10,11,23,30}

+0.75V_DDR_VTT {7,30} +3V {4,5,7,8,9,10,11,12,13,14,15,17,18,19,20,22,23,24,26,27,28,29,30,31}

A

{3,7} M_A_BS[0..2]

R8 9 R9 0 B

{3} {3} {3} {3} {3} {3} {3,7} {3,7} {3,7} {3,7} {3,7}

M_A_CS#0 M_A_CS#1 M_A_CLKP0 M_A_CLKN0 M_A_CLKP1 M_A_CLKN1 M_A_CKE0 M_A_CKE1 M_A_CAS# M_A_RAS# M_A_WE# 1 0K/ F_ 4 1 0K/ F_ 4

{7,8,17,23} PCLK_SMB {7,8,17,23} PDAT_SMB {3} M_A_ODT0 {3} M_A_ODT1 {3,7} M_A_DM[0..7]

{3,7} M_A_DQSP[7:0]

{3,7} M_A_DQSN[7:0]

SM_MEM BUS ADDRESS C

SO-DIMM0

1010 000

SO-DIMM1

1010 001

M_A_DQ[0..63]

CN15A

{3,7} M_A_A[0..15]

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A14 A15

M_A_BS0 M_A_BS1 M_A_BS2 M_A_CS#0 M_A_CS#1 M_A_CLKP0 M_A_CLKN0 M_A_CLKP1 M_A_CLKN1 M_A_CKE0 M_A_CKE1 M_A_CAS# M_A_RAS# M_A_WE# DIMM0_SA0 DIMM0_SA1 PCLK_SMB PDAT_SMB

109 108 79 114 121 101 103 102 104 73 74 115 110 113 197 201 202 200

BA0 BA1 BA2 S0# S1# CK0 CK0# CK1 CK1# CKE0 CKE1 CAS# RAS# WE# SA0 SA1 SCL SDA

M_A_ODT0 M_A_ODT1

116 120

ODT0 ODT1

M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

11 28 46 63 136 153 170 187

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

M_A_DQSP0 M_A_DQSP1 M_A_DQSP2 M_A_DQSP3 M_A_DQSP4 M_A_DQSP5 M_A_DQSP6 M_A_DQSP7 M_A_DQSN0 M_A_DQSN1 M_A_DQSN2 M_A_DQSN3 M_A_DQSN4 M_A_DQSN5 M_A_DQSN6 M_A_DQSN7

12 29 47 64 137 154 171 188 10 27 45 62 135 152 169 186

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7

BUS1_A2

   M    M    I    D      O    S    M    A    R    D    S    3    R    D    D    0   )    0   P    1   4    2   0    C   2    P   (

{3,7}

M_A_DQ0 M_A_DQ1 M_A_DQ7 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ2 M_A_DQ8 M_A_DQ9 M _A_DQ14 M_A_DQ11 M_A_DQ13 M_A_DQ12 M_A_DQ10 M_A_DQ15 M_A_DQ20 M_A_DQ17 M_A_DQ22 M _A_DQ23 M_A_DQ21 M_A_DQ16 M_A_DQ18 M_A_DQ19 M_A_DQ24 M_A_DQ29 M_A_DQ27 M_A_DQ26 M_A_DQ28 M_A_DQ25 M_A_DQ31 M_A_DQ30 M_A_DQ36 M_A_DQ37 M_A_DQ39 M_A_DQ34 M_A_DQ32 M_A_DQ33 M_A_DQ38 M_A_DQ35 M_A_DQ40 M_A_DQ45 M_A_DQ43 M _A_DQ42 M_A_DQ44 M_A_DQ41 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ52 M_A_DQ54 M_A_DQ50 M_A_DQ53 M_A_DQ49 M_A_DQ51 M_A_DQ55 M_A_DQ60 M_A_DQ61 M_A_DQ63 M_A_DQ62 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59

5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

+1.5VSUS CN15B

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124 +3V

199 77 122 125

R106 R106

{3,7} M_A_EVENT# {3,7} M_A_RST#

{7} +DDR_VREF2 {7} +DDR_VREF

*Short_ 4 MEM_A_HOT#

1 126

+DDR_VREF C242   0.1u/10V_4 C242 0.1u/1 0V_4

2 3 8 9 13 14 19 20 25 26 31 32 37 38 43

C243   1000p/50V_4 C243 1000p/50V_4

C212

0.1u/1 0V_4

C216

*1000p/50V_4

198 30

+DDR_VREF2

A

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52

44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196

VTT2

203 204

   M    M    I    D      O VDDSPD    S NC1    M NC2 NCTEST    A EVENT#    R RESET#    D    S VREF_DQ    3 VREF_CA    R    D VSS1    D VSS2 VSS3    0   ) VSS4    0   P VSS5    1   4 VSS6    2   0 VSS7    C VSS8    2    ( VSS9    P VSS10 VTT1 VSS11 VSS12 VSS13 VSS14 VSS15

B

600mA  +0.75V_DDR_VTT C232

    D     D     N     N     G     G

4.7u/6.3V_6

C231

C226

0.1u/10V_4

4.7u/6.3V_6

DDR3-DIMM1_H=9.2_STD     5     6     0     0     2     2

+1.5VSUS C

DDR3-DIMM1_H=9.2_STD

 3mA +1.5VSUS

{7,30} +SMDDR_VREF

R152 1K/F_4

+SMDDR_VREF R150

* 0_6

+DDR_VREF

+1.5VSUS C239

C222

C237

0.1u/10V_4 0.1u/10V_4

C252

C219

0.1u/10V_4 0.1u/10V_4

0.1u/10V_4

R146 1K/F_4

C225

C218

C233

C249

C234

C220

C254

4.7u/6.3V_6

4.7u/6.3V_6

2.2u/6.3V_6

2.2u/6.3V_6

1u/6.3V_4

1u/6.3V_4

1u/6.3V_4

0.1u/10V_4

+1.5VSUS +1.5VSUS C224

C223

C236

C238

C217

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

D

C241 C235 180P/50V_4

0.1u/10V_4

D

C221

C253

0.1u/10V_4

0.1u/10V_4

Quanta Computer Inc. PROJECT : ZQZ Size

Document Number

Rev 1A

DDR3 SO-DIMM (STD) Date: 1

2

3

4

5

6

Thursday, February 23, 2012 7

Sheet

6 8

of

32

1

2

3

4

5

6

7

0830--P/N and footprint are follow ZR7B

A

{3,6} M_A_BS[2..0]

+3V

{3} {3} {3} {3} {3} {3} {3,6} {3,6} {3,6} {3,6} {3,6}

R1 48 R1 49

{6,8,17,23} {6,8,17,23}

B

M_A_CS#2 M_A_CS#3 M_A_CLKP2 M_A_CLKN2 M_A_CLKP3 M_A_CLKN3 M_A_CKE0 M_A_CKE1 M_A_CAS# M_A_RAS# M_A_WE# 1 0K /F_ 4 1 0K /F_ 4 PCLK_SMB PDAT_SMB

{3} M_A_ODT2 {3} M_A_ODT3 {3,6} M_A_DM[0..7]

{3,6} M_A_DQSP[7:0]

{3,6} M_A_DQSN[7:0]

SM_MEM BUS ADDRESS

C

SO-DIMM0

1010 000

SO-DIMM1

1010 001

M_A_DQ[0..63]

CN17A

{3,6} M_A_A[0..15]

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78

M_A_BS0 M_A_BS1 M_A_BS2 M_A_CS#2 M_A_CS#3 M_A_CLKP2 M_A_CLKN2 M_A_CLKP3 M_A_CLKN3 M_A_CKE0 M_A_CKE1 M_A_CAS# M_A_RAS# M_A_WE# DIMM1_SA0 DIMM1_SA1 PCLK_SMB PDAT_SMB

109 108 79 114 121 101 103 102 104 73 74 115 110 113 197 201 202 200

M_A_ODT2 M_A_ODT3

116 120

M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

11 28 46 63 136 153 170 187

M_A_DQSP0 M_A_DQSP1 M_A_DQSP2 M_A_DQSP3 M_A_DQSP4 M_A_DQSP5 M_A_DQSP6 M _A_DQSP7 M_A_DQSN0 M_A_DQSN1 M_A_DQSN2 M_A_DQSN3 M_A_DQSN4 M_A_DQSN5 M_A_DQSN6 M_A_DQSN7

12 29 47 64 137 154 171 188 10 27 45 62 135 152 169 186

BUS1_A2

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A14 A15 BA0 BA1 BA2 S0# S1# CK0 CK0# CK1 CK1# CKE0 CKE1 CAS# RAS# WE# SA0 SA1 SCL SDA ODT0 ODT1 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7

   M    M    I    D      O    S    M    A    R    D    S    3    R    D    D    0   )    0   P    1   4    2   0    C   2    P   (

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194

8

07

+1.5VSUS {3,4,5,6,10,11,23,30} +0.75V_DDR_VTT {6,30} +3V {4,5,6,8,9,10,11,12,13,14,15,17,18,19,20,22,23,24,26,27,28,29,30,31} {3,6}

M_A_DQ0 M_A_DQ1 M_A_DQ7 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ2 M_A_DQ8 M_A_DQ9 M_A_DQ14 M_A_DQ11 M_A_DQ13 M_A_DQ12 M_A_DQ10 M_A_DQ15 M_A_DQ20 M_A_DQ17 M _A_DQ22 M_A_DQ23 M_A_DQ21 M_A_DQ16 M_A_DQ18 M_A_DQ19 M_A_DQ24 M_A_DQ29 M _A_DQ27 M_A_DQ26 M_A_DQ28 M_A_DQ25 M_A_DQ31 M_A_DQ30 M_A_DQ36 M_A_DQ37 M_A_DQ39 M_A_DQ34 M_A_DQ32 M_A_DQ33 M_A_DQ38 M_A_DQ35 M_A_DQ40 M_A_DQ45 M_A_DQ43 M_A_DQ42 M_A_DQ44 M_A_DQ41 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ52 M_A_DQ54 M_A_DQ50 M_A_DQ53 M_A_DQ49 M_A_DQ51 M_A_DQ55 M_A_DQ60 M_A_DQ61 M_A_DQ63 M _A_DQ62 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59

+1.5VSUS CN17B

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

   M    M    I    D      O VDDSPD    S NC1 NC2    M NCTEST    A EVENT#    R RESET#    D    S VREF_DQ   3 VREF_CA    R    D VSS1    D VSS2 VSS3    0   ) VSS4    0   P VSS5    1   4 VSS6    2   0 VSS7    C VSS8    2 VSS9    P   ( VTT1 VSS10

199

+3V

77 122 125 {3,6} M_A_EVENT# {3,6} M_A_RST#

{6} {6}

R 14 7

* Sh or t_ 4

MEM_B_HOT#

+DDR_VREF2 +DDR_VREF

+DDR_VREF2 +DDR_VREF

0.1u/10V_4

C276

1000p/50V_4

C246

0.1u/10V_4

C259

*1000p/50V_4

198 30 1 126

C277

2 3 8 9 13 14 19 20 25 26 31 32 37 38 43

+DDR_VREF2

VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52

VSS11 VSS12 VSS13 VSS14 VSS15

VTT2

A

44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196

B

203 204

+0.75V_DDR_VTT C264

C266

4.7u/6.3V_6

    D     D     N     N     G     G

C245

0.1u/10V_4

4.7u/6.3V_6

DDR3-DIMM0_H=5.2_Standard

    5     6     0     0     2     2

DDR3-DIMM0_H=5.2_Standard C

+1.5VSUS

 3mA {6,30} +SMDDR_VREF

+1.5VSUS

R153 1K/F_4

+SMDDR_VREF R1 42

* 0_ 6

+DDR_VREF2

+1.5VSUS

C268

C279

4.7u/6.3V_6

4.7u/6.3V_6

C247

C284

2.2u/6.3V_6

2.2u/6.3V_6

C255 1u/6.3V_4

C280 1u/6.3V_4

R133 1K/F_4

C267 C278

C271

C273

C274

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

1u/6.3V_4

+1.5VSUS +1.5VSUS

D

C250

C275

C269

C251

C256

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

C281

C272

C270

C283

C240

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

D

Quanta Computer Inc. PROJECT : ZQZ Size

Document Number

Rev 1A

DDR3 SO-DIMM (STD) Date: 1

2

3

4

5

6

Thursday, February 23, 2012 7

Sheet

7 8

of

32

5

4

3

2

1

10 SATA HDD/SSD

C392 C394

{18} SATA_TXP0 {18} SATA_TXN0

SATA_TXP0_C SATA_TXN0_C

AK19   SATA_TX0P AM19 SATA_TX0N

HUDSON-M3  

{18} SATA_RXN0 {18} SATA_RXP0 C399 C400 C400

{18} SATA_TXP1 {18} SATA_TXN1

0.01U/2 5V_4 0.01U/25V_4 0.01U/ 2 5V_4

SATA_TXP1_C SATA_TXN1_C

AN22   SATA_TX1P AL22 SATA_TX1N

   D    R    D   A    S   C

AH20   SATA_RX1N AJ20 SATA_RX1P

{18} SATA_RXN1 {18} SATA_RXP1

Part2of5

SD_CLK/SCLK_2/GPIO73 SD_CMD/SLOAD_2/GPIO74 SD_CD#/GPIO75 SD_WP/GPIO76 SD_DATA0/SDATI_2/GPIO77 SD_DATA1/SDATO_2/GPIO78 SD_DATA2/GPIO79 SD_DATA3/GPIO80

AL20   SATA_RX0N AN20 SATA_RX0P

D

SATA ODD

0.01U/2 5V_4X 0.01U/2 5V_4

20120104:  Add R449, R450, R451  Add net N30960722

U17B

PLACE SATA AC COUPLING CAPSCLOSE TOHUDSON-M2/M3

GBE_COL GBE_CRS GBE_MDCK GBE_MDIO GBE_RXCLK GBE_RXD3 GBE_RXD2 GBE_RXD1 GBE_RXD0 GBE_RXCTL/RXDV GBE_RXERR GBE_TXCLK GBE_TXD3 GBE_TXD2 GBE_TXD1 GBE_TXD0 GBE_TXCTL/TXEN GBE_PHY_PD GBE_PHY_RST# GBE_PHY_INTR

AJ22   SATA_TX2P AH22 SATA_TX2N AM23   SATA_RX2N AK23 SATA_RX2P AH24   SATA_TX3P AJ24 SATA_TX3N

   E   N    B   A    G   L

AN24   SATA_RX3N AL24 SATA_RX3P AL26   SATA_TX4P AN26 SATA_TX4N AJ26   SATA_RX4N AH26 SATA_RX4P AN29   SATA_TX5P AL28 SATA_TX5N

   L    A    I    R   A    E   T    S   A

AK27   SATA_RX5N AM27 SATA_RX5P AL29 AN31

C

NC6 NC7

VGA_RED

AL31 AL33

PLACE SATA_CAL RES VERY CLOSE TO BALL OF HUDSON-M2/M3

NC8 NC9

AH33 AH31 AJ33 AJ31

R377 +1.1V_AVDD_SATA

R80

 

1K/F_4

931/F_4

+3V

R 18 3

SATA_CALRP SATA_CALRN

VGA_GREEN

NC10 NC11

VGA_BLUE

NC12 NC13

VGA_HSYNC/GPO68 VGA_VSYNC/GPO69

   A   C    G   A    V   D

AF28   SATA_CALRP AF27 SATA_CALRN

1 0K /F _4 SATA_LED# AD22

{22} SATA_LED#

SPI_DI/GPIO164 SPI_DO/GPIO163 SPI_CLK/GPIO162 SPI_CS1#/GPIO165

   I    M ROM_RST#/SPI_WP#/GPIO161    P   O    S   R

VGA_DDC_SDA/GPO70 VGA_DDC_SCL/GPO71 VGA_DAC_RSET AUX_VGA_CH_P AUX_VGA_CH_N

SATA_ACT#/GPIO67

AUXCAL

AF21

SATA_X1 ML_VGA_L0P ML_VGA_L0N ML_VGA_L1P ML_VGA_L1N ML_VGA_L2P ML_VGA_L2N ML_VGA_L3P ML_VGA_L3N

IntegratedClock Mode: Leaveuncon nected. +3V

AG21

R332 *10K/F_4 {18} FCH_ODD_EN

BOARD_ID1 FCH_ODD_EN FCH_PROCHOT#_C BOARD_ID2 BOARD_ID3 BOARD_ID4 BOARD_ID5 BOARD_ID6 BOARD_ID7 TEMPIN3

B

R60 10K_4

SATA_X2

AH16   FANOUT0/GPIO52 AM15 FANOUT1/GPIO53 AJ16 FANOUT2/GPIO54 AK15   FANIN0/GPIO56 AN16 FANIN1/GPIO57 AL16 FANIN2/GPIO58

   K    N    I    L    N    A   I    G   A    V   M

HW MONITOR

K6   TEMPIN0/GPIO171 K5 TEMPIN1/GPIO172 K3 TEMPIN2/GPIO173 M6 TEMPIN3/TALERT#/GPIO174

ML_VGA_HPD/GPIO229 VIN0/GPIO175 VIN1/GPIO176 VIN2/SDATI_1/GPIO177 VIN3/SDATO_1/GPIO178 VIN4/SLOAD_1/GPIO179 VIN5/SCLK_1/GPIO180 VIN6/GBE_STAT3/GPIO181 VIN7/GBE_LED3/GPIO182 NC1 NC2 NC3 NC4 NC5

+3VPCU +3V_S5

AL14 AN14 AJ12 AH12 AK13 AM13 AH15 AJ14 AC4 AD3 AD9 W10 AB8 AH7 AF7 AE7 AD7 AG8 AD1 AB7 AF9 AG6 AE8 AD8 AB9 AC2 AA7 W9 V6 V5 V3 T6 V1

R449

0_4

R 27 4 R 27 7 R278 R 27 8 R 27 5

 

* sh or t_ 4 * sh or t_ 4 *short_4 * sh or t_ 4 * sh or t_ 4

SPI_CS SPI _SCK SPI_SDO SPI_SDI

R248

 

D

N30960722

33_4

FCH_SPI1_SI_R

C346 *22P/50V_4

1 6 5 2 3

CE# SCK SI SO

HOLD#

VDD

WP#

VSS

R203 10K_4

8 7

SPI_HOLD#

{8}

4

W25Q32BVSSIG(SOIC) C49 0.1U/10V_4

N30960722

GBE_PHY_INTR

R68

10K_4

{24} {24} {24} {24}

+3V_S5

FCH_SPI_SI FCH_SPI_SO FCH_SPI_CLK FCH_SPI_CS0# FCH_SPI_WP

TP40

L32

TP46

M29

TP47

M28 N30

TP41 TP45

M33 N32

TP35 TP36

K31

TP34

V28 V29

TP52 TP51

U28

TP39

T31 T33 T29 T28 R32 R30 P29 P28

TP50 TP38 TP44 TP43 TP49 TP37 TP42 TP48

N2 M3 L2 N4 P1 P3 M1 M5

110K_4 0 K_ 4

U14 FCH_SPI_CS0# FCH_SPI_CLK FCH_SPI_SO FCH_SPI_SI

L30

C29

R450

*0_4 R R451 45 1

R27 6

10K_4 FCH_SPI_WP

20120111: Connect R451 net from FCH_SPI_CS0# to SPI_CS

SPI_CS SPI_SCK SPI_SDO SPI_SDI

SPI_CS SPI_SCK SPI_SDO SPI_SDI

C

+1.5VSUS

+3V_S5

R244 *1K/F_4

R243 *1K/F_4

VIN_VDDIO

VIN_VDDR R272 *1K/F_4

R270 *1K/F_4

TP4 VIN0 VIN1 VIN2 MEM_P1V5 MEM_P1V35 VIN_VDDIO VIN_VDDR VIN7

R271 R54 R56

10K_4 10K_4 10K_4

R57

10K_4

T13 T9

AG16 AH10 A28 G27 L4

+3V

R 33 6 R317 R330 R321 R379 R365

l vd s@ 10 K_ 4BOARD_ID1 10K_4 BOARD_ID2 10K_4 BOARD_ID3 10K_4 BOARD_ID4 *10K_4 BOARD_ID8 *10K_4 BOARD_ID9

+3V_S5

R238 R240 R241

*10K_4 10K_4 10K_4

R341

10K_4

R 33 7 R316 R333 R320 R374 R363

* eD P@ 10 K_ 4 *10K_4 *10K_4 *10K_4 *10K_4 *10K_4

BOARD_ID5 BOARD_ID6 BOARD_ID7

R266 R268 R269

10K_4 *10K_4 *10K_4

BOARD_ID10

R342

*10K_4

B

?

BOARD ID SETTING BOARD_ID1

LCD

BOARD_ID2

BOARD_ID3

0

eDP

0

1

1

LVDS

1

0

1

1

{8} {8} {8} {23} {23}

For TP

BOARD_ID8 BOARD_ID9 BOARD_ID10 BOARD_ID2 BOARD_ID3

BOARD_ID8 BOARD_ID9 BOARD_ID10 BOARD_ID2 BOARD_ID3

 ALPS

ELAN

Synaptics

A

A

Quanta Computer Inc. PROJECT : ZQZ Size

Document Number

Date:

Thursday,February 23,2012

Rev 1A

FCH 3/5(SATA/VGA/GND/SPI) 5

4

3

2

1

Sheet

10

of

32

5

4

3

2

11

PLACE ALL THE DECOUPLING CAPS ON THIS SHEET CLOSE TO SB AS POSSIBLE.

U17D

 VDD-- S/B CORE power

+3.3V_FCH_R

 VDDQ--3.3V I/O power R 72

+3V

C124 22U/6.3V_8 22U/6.3V_8

C140 0.1U/10V_4

U17C

102mA

* sh or _ t 8

+3V

L24

C103 0.1U/10V_4

C123 0.1U/10V_4

TRACEWIDTH >=15mil

HCB1608KF-221T20 C205 2.2U/6.3V_4

C206 *0.1U/10V_4

47mA

+VDDPL_3.3V

+3V

L25

+FCH_VDDPL_33_SSUSB_S +FCH_VDDPL_33_SUSB_S

C204 2.2U/6.3V_4

C203 *0.1U/10V_4

11mA 14mA 11mA 12mA

+FCH_VDDPL_33_PCIE +FCH_VDDPL_33_SATA R376 C 4 09

+1.5VSUS

*0_4 LDO_CAP *22 . U6 / . 3V _ 6

M31

L19 U3@HCB1608KF-221T20 U3@HCB1608KF-221T20

AB10 C184 [email protected]/10V_4

VDDAN_11_SATA_1 VDDAN_11_SATA_4 VDDAN_11_SATA_2 VDDAN_11_SATA_3 VDDAN_11_SATA_5    L VDDAN_11_SATA_6    A    I VDDAN_11_SATA_7    R   A    E   T VDDAN_11_SATA_8    S   A VDDAN_11_SATA_9 VDDAN_11_SATA_10

   E    B   N    A    G   L

*U2@0_4

AB11   VDDCR_11_GBE_S_1 AA11 VDDCR_11_GBE_S_2

+FCH_VDDPL_33_SUSB_S

AA9   VDDIO_GBE_S_1 AA10 VDDIO_GBE_S_2

+3V_AVDD_USB C

VDDAN_11_PCIE_1 VDDAN_11_PCIE_2 VDDAN_11_PCIE_3 VDDAN_11_PCIE_4 VDDAN_11_PCIE_5 VDDAN_11_PCIE_6 VDDAN_11_PCIE_7 VDDAN_11_PCIE_8

   S    S    E    R    I    P    N   K    I    C   X    P   E    A   N    I    M   L

R79 C193 [email protected]/6.3V_6

   N    E    G    K    L   O    /    C   I

VDDIO_33_GBE_S

VDDCR_11_2 VDDCR_11_3 VDDCR_11_4 VDDCR_11_5 VDDCR_11_6 VDDCR_11_7 VDDCR_11_8 VDDCR_11_9

VDDAN_11_CLK_1 VDDAN_11_CLK_2 VDDAN_11_CLK_3 VDDAN_11_CLK_4 VDDAN_11_CLK_5 VDDAN_11_CLK_6 VDDAN_11_CLK_7 VDDAN_11_CLK_8

VDDPL_11_DAC

Y22   VDDAN_11_ML_1 V23 VDDAN_11_ML_2 V24 VDDAN_11_ML_3 V25 VDDAN_11_ML_4

+ FC H_ VD DP L_ 33 _S SU SB _S

   E    R    O   0    C   S

LDO_CAP

V21

+ 3V _S 5

   O    /    I    O    I    P    G    /    I    C    P

H24   VDDPL_33_SYS V22 VDDPL_33_DAC U22 VDDPL_33_ML T22 VDDAN_33_DAC L18 VDDPL_33_SSUSB_S D7 VDDPL_33_USB_S AH29 VDDPL_33_PCIE AG28 VDDPL_33_SATA

TRACEWIDTH >=15mil

HCB1608KF-221T20

TRACEWIDTH >=100mil

1007mA

T14 T17 T20 U16 U18 V14 V17 V20 Y17

R 74

C136 0.1U/10V_4

C158 0.1U/10V_4

C137 1U/10V_4

C127 1U/10V_4

+1.1V

C125 10U/6.3V_8

CKVDD_1.1V-Internal clock Generator I/O  power

+1.1V_CKVDD

340mA

H26 J25 K24 L22 M22 N21 N22 P22

* sh or _ t 8

TRACEWIDTH >=30mil

L21 HCB1608KF-181T15_1.5A C175 1U/10V_4

C197 1U/10V_4

C174 0.1U/10V_4

C196 0.1U/10V_4

+1.1V

C171 22U/6.3V_8

+1.1V_PCIE_VDDR

AB24 Y21 AE25 AD24 AB23 AA22 AF26 AG27 AA21 Y20 AB21 AB22 AC22 AC21 AA20 AA18 AB20 AC19

TRACEWIDTH >=100mil

1088mA

PCIE_VDDR--PCIE I/O power L18 HCB1608KF-181T15_1.5A

C191 0.1U/10V_4

C183 0.1U/10V_4

C195 1U/10V_4

C200 1U/10V_4

+1.1V

C198 22U/6.3V_8

+1.1V_AVDD_SATA TRACEWIDTH >=100mil

1337mA

 AVDD_SATA--SATA phy power

L13 HCB1608KF-181T15_1.5A

C168 0.1U/10V_4

C162 0.1U/10V_4

C173 1U/10V_4

C167 1U/10V_4

+1.1V

C170 22U/6.3V_8

L35 HCB1608KF-221T20

S5_3.3--3.3v standby power C368 2.2U/6.3V_6

C369 1U/10V_4

+3V_AVDD_USB TRACEWIDTH >=50mil

G7   VDDAN_33_USB_S_1 H8 VDDAN_33_USB_S_2 J8 VDDAN_33_USB_S_3 K8 VDDAN_33_USB_S_4 K9 VDDAN_33_USB_S_5 M9 VDDAN_33_USB_S_6 M10 VDDAN_33_USB_S_7 N9 VDDAN_33_USB_S_8 N10 VDDAN_33_USB_S_9 M12 VDDAN_33_USB_S_10 N12 VDDAN_33_USB_S_11 M11 VDDAN_33_USB_S_12

470mA

L11

+3V_S5

HCB1608KF-221T20 EMI

C100 0.1U/10V_4

C84 10U/6.3V_8

L5

+1.1V_S5

C85 10U/6.3V_8

C77 1U/10V_4

+FCH_VDDAN_11_USB_S C50 2 . 2U / 6. 3 V_ 6 C51 0 . 1U / 10 V _4

HCB1608KF-221T20

C78 1U/10V_4

TRACEWIDTH >=20mil

140mA L8

+1.1V_S5

+FCH_VDDCR_11_USB_S TRACEWIDTH >=15mil

HCB1608KF-221T20 +1.1V_S5

C56 0.1U/10V_4

+FCH_VDD_11_SSUSB_S

L36 U3@HCB1608KF-221T20

B

A3   VSS_1 A33 VSS_2 B7 VSS_3 B13 VSS_4 D9 VSS_5 D13 VSS_6 E5 VSS_7 E12 VSS_8 E16 VSS_9 E29 VSS_10 F7 VSS_11 F9 VSS_12 F11 VSS_13 F13 VSS_14 F16 VSS_15 F17 VSS_16 F19 VSS_17 F23 VSS_18 F25 VSS_19 F29 VSS_20 G6 VSS_21 G16 VSS_22 G32 VSS_23 H12 VSS_24 H15 VSS_25 H29 VSS_26 J6 VSS_27 J9 VSS_28 J10 VSS_29 J13 VSS_30 J28 VSS_31 J32 VSS_32 K7 VSS_33 K16 VSS_34 K27 VSS_35 K28 VSS_36 L6 VSS_37 L12 VSS_38 L13 VSS_39 L15 VSS_40 L16 VSS_41 L21 VSS_42 M13 VSS_43 M16 VSS_44 M21 VSS_45 M25 VSS_46 N6 VSS_47 N11 VSS_48 N13 VSS_49 N23 VSS_50 N24 VSS_51 P12 VSS_52 P18 VSS_53 P20 VSS_54 P21 VSS_55 P31 VSS_56 P33 VSS_57 R4 VSS_58 R11 VSS_59 R25 VSS_60 R28 VSS_61 T11 VSS_62 T16 VSS_63 T18 VSS_64

+1.1V_VCC_FCH_R of5 HUDSON-M3   P a r t 3VDDCR_11_1

AB17   VDDIO_33_PCIGP_1 AB18 VDDIO_33_PCIGP_2 AE9 VDDIO_33_PCIGP_3 AD10 VDDIO_33_PCIGP_4 AG7 VDDIO_33_PCIGP_5 AC13 VDDIO_33_PCIGP_6 AB12 VDDIO_33_PCIGP_7 AB13 VDDIO_33_PCIGP_8 AB14 VDDIO_33_PCIGP_9 AB16 VDDIO_33_PCIGP_10

D

1

C55 0.1U/10V_4

C57 10U/6.3V_8

R 70

* sh or _ t 8

+FCH_VDDAN_11_SSUSB_S_R

R 69

* sh or _ t 8

+FCH_VDDCR_11_SSUSB_S

C148 U3@10U/6.3V_8

R71 *U2@0_4

C101 U3@1U/10V_4

C117 [email protected]/10V_4

C108 [email protected]/10V_4

C86 U3@1U/10V_4

VDDXL_33_S

U12   VDDAN_11_USB_S_1 U13 VDDAN_11_USB_S_2

VDDCR_11_S_1 VDDCR_11_S_2

T12   VDDCR_11_USB_S_1 T13 VDDCR_11_USB_S_2

42mA

VDDPL_11_SYS_S VDDAN_33_HWM_S

P16   VDDAN_11_SSUSB_S_1 M14 VDDAN_11_SSUSB_S_2 N14 VDDAN_11_SSUSB_S_3 P13 VDDAN_11_SSUSB_S_4 P14 VDDAN_11_SSUSB_S_5

282mA

N16   VDDCR_11_SSUSB_S_1 N17 VDDCR_11_SSUSB_S_2 P17 VDDCR_11_SSUSB_S_3 M17 VDDCR_11_SSUSB_S_4

424mA

C145 [email protected]/10V_4

C149 U3@1U/10V_4

   B    S    U

   O    /    I    5    S _    V    3  .    3

VDDIO_33_S_1 VDDIO_33_S_2 VDDIO_33_S_3 VDDIO_33_S_4 VDDIO_33_S_5 VDDIO_33_S_6 VDDIO_33_S_7 VDDIO_33_S_8

N18 L19 M18 V12 V13 Y12 Y13 W11 G24 N20 M20

S5 plus mode

TRACEWIDTH >=20mil +VDDIO_33_S

59mA

C105 1U/10V_4

5mA

R 64

C121 1U/10V_4

C164 2.2U/6.3V_6

* sh or t_ 6

+3V_S5

C95 10u/10V_8

+VDDXL_3.3V

L22 HCB1608KF-221T20

S5_1.1V--1.1V standby power

187mA

+VDDCR_1.1V TRACEWIDTH >=15mil

R 78

C169 1U/10V_4

J24

70mA

+VDDPL_1.1V

M8

12mA

+VDDAN_3.3V_HWM

* sh o tr _6 +1.1V_S5

C199 *0.1U/10V_4

+3V_S5

C207 2.2U/6.3V_6

N8

C161 1U/10V_4

K25 H25

HUDSON-M3 P a rt 5 o f 5

   D    N    U    O    R    G

VSSAN_HWM

T25 T27 U6 U14 U17 U20 U21 U30 U32 V11 V16 V18 W4 W6 W25 W28 Y14 Y16 Y18 AA6 AA12 AA13 AA14 AA16 AA17 AA25 AA28 AA30 AA32 AB25 AC6 AC18 AC28 AD27 AE6 AE15 AE21 AE28 AF8 AF12 AF16 AF33 AG30 AG32 AH5 AH11 AH18 AH19 AH21 AH23 AH25 AH27 AJ18 AJ28 AJ29 AK21 AK25 AL18 AM21 AM25 AN1 AN18 AN28 AN33

VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128

VSSPL_SYS

R6

EFUSE VDDIO_AZ_S

AA4

26mA

C

T21 L28 K33 N28

VSSPL_DAC VSSAN_DAC VSSANQ_DAC VSSIO_DAC

VSSXL

D

?

+VDDIO_AZ

Tracewidth>=20mil    B    S   S    U   S

R73

B

*U2@0_4 C146 [email protected]/10V_4

POWER

?

+1.1V_S5

+1.1V

+VDDPL_1.1V

+VDDIO_AZ +3V +3V_S5

R 62

+3V_S5

C94 2.2U/6.3V_6

C104 *0.1U/10V_4

+VDDPL_3.3V

+VDDAN_3.3V_HWM

L20 *U2@HCB1608KF-221T20 L16 U3@HCB1608KF-221T20

* sh or _ t 8

L15 HCB1608KF-221T20

L12 HCB1608KF-221T20 C194 2.2U/6.3V_6

C192 0.1U/10V_4

C81 2.2U/6.3V_6

C73 0.1U/10V_4

C179 2.2U/6.3V_6

C178 0.1U/10V_4

A

A

Quanta Computer Inc. PROJECT : ZQZ Size

Document Number

Date:

Thursday,February 23,2012

Rev 1A

FCH 4/5(POWER) 5

4

3

2

1

Sheet

11

of

32

5

4

3

2

1

12

OVERLAP COMMON PADS WHERE POSSIBLE FOR DUAL-OP RESISTORS. +3V

+3 V

+3V

+3V_S5

+3V_S5

+3V_S5

+3 V_S5

STRAPS PINS D

D

R250 10K_4

{9}

PCI_CLK1

PCI_CLK1

{9}

PCI_CLK3

PCI_CLK3

{9}

PCI_CLK4

PCI_CLK4

{9}

LPC_CLK0

LPC_CLK0

{9}

LPC_CLK1

LPC_CLK1

{8}

EC_PWM2

EC_PWM2

{9}

RTC_CLK

RTC_CLK

R251 *10K_4

R252 *10K_4

R360 *10K_4

R355 10K_4

R352 *10K_4

R307 10K_4

+3V_S5

System PWR_OK(CLG) C344 *0.1u/10V_4

U3 R249 *10K_4

R283 10K_4

R253 10K_4

R361 10K_4

R354 *10K_4

R353 2.2K_4

R308 *2.2K_4

{8} FCH_PWRGD

EC_PWM2--> SPI ROM: 2.2-KΩ 5% pull-down LPC ROM: Pull-up to 3.3V_S5. External pull-up resistor is not required as FCH has integrated 10-K Ω pull-up to 3.3V_S5.

FCH_PWRGD

   5

2 4 1

CPU_COREPG PWROK_EC

PWROK_EC

{23,27}

{23,24}

TC7SH08FU    3 R39 100K_4

C

C

Remove PCI_CLK2 function

--------

REQUIRED STRAPS

PULL HIGH

PULL LOW

--------

--------

PCI_CLK1 ALLOW PCIEGen2 DEFAULT

FORCE PCIEGen1

PCI_CLK2

--------

--------

PCI_CLK3

PCI_CLK4

LPC_CLK0

USE DEBUG STRAP

non_Fusion CLOCKMODE

IGNORE DEBUG STRAP

FUSION CLOCKMODE

EC DISABLED

DEFAULT

DEFAULT

EC ENABLED

LPC_CLK1

EC_PWM2

RTC_CLK

CLKGEN ENABLED

LPC ROM

S5 PLUSMODE

DISABLED

DEFAULT

CLKGEN DISABLED

FCH PWRGD CKT

DEFAULT

SPIROM

S5 PLUSMODE

ENABLED DEFAULT

DEFAULT

B

B

DEBUG STRAPS FCH HAS 15K INTERNAL PU FO R PCI_AD[27:23]

{9}

PCI_AD27

{9}

PCI_AD26

{9}

PCI_AD25

{9}

PCI_AD24

{9}

PCI_AD23

PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24

PULL HIGH

PCI_AD23

R287 *2.2K_4

R286 *2.2K_4

R311 *2.2K_4

R305 *2.2K_4

R306 *2.2K_4

PULL LOW

PCI_AD27

PCI_AD26

PCI_AD25

PCI_AD24

PCI_AD23

USEPCI PLL

DISABLEILA AUTORUN

USEFC PLL

USEDEFAULT PCIESTRAPS

DISABLE PCI MEM BOOT

DEFAULT

DEFAULT

DEFAULT

DEFAULT

DEFAULT

BYPASS PCI PLL

ENABLEILA AUTORUN

BYPASSFC PLL

USEEEPROM PCIESTRAPS

ENABLEPCI

MEM BOOT

A

A

Quanta Computer Inc. PROJECT : ZQZ Size

Document Number

Rev 1A

FCH 5/5(STRAP & PWRGD) Date: 5

4

3

2

Thursday,February 23,2012 1

Sheet

12

of

32

5

4

3

2

HDMI SDVO I2C Control

1

HDMI HPD SENSE (HDM)

14

UMA use +3V for the detect pin Dis use +3V_DELAY for the detect pin HDMI_DDCDATA HDMI_DDCCLK

{4} HDMI_DDCDATA {4} HDMI_DDCCLK

+3V

D

D

INT_HDMI_HPD

R383

*0_4

R394 10K_4

HDMI_DET

    3

+3V

HDMI_DET

2 R384 10K_4

Q21 2N7002K

    1 {4} INT_HDMI_HPD

2

Ramp 0223: Change R88, R94, R103, R109 value from 100 to 120ohm and stuff

HDMI (HDM)

R388 100K_4

*0.01U/25V_4

    3

HDMI_HPD_EC#

Q22 2N7002K C

C517

{24}

2011/08/25: Change R214 from 2000k to 100k

20120110:  Add C517 for hdmi detect issue

    1

C

EMI reserve for HDMI(EMC)

Close to HDMI Connector

Close connector

HDMI PORT (HDM)

TX2_HDMI+

+5V

HDMI_PL_MOS

R 10 7

4 99 /F _4

TX2_HDMI+

R 11 1

4 99 /F _4

TX2_HDMI-

R9 8

49 9/ F_ 4

TX1_HDMI+

R109 120/F_4

CN13

TX2_HDMI-

    3

TX2_HDMI+

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

TX1_HDMI+

Q9 2N7002K 2

R9 3

49 9/ F_ 4

TX1_HDMI-

R 10 4

4 99 /F _4

TX0_HDMI+

R 10 1

4 99 /F _4

TX0_HDMI-

TX2_HDMITX1_HDMI+

R94 120/F_4 TX1_HDMI-

TX1_HDMITX0_HDMI+

TX0_HDMI+

    1 B

R92

R9 1

49 9/ F_ 4

TXC_HDMI+

R8 7

49 9/ F_ 4

TXC_HDMI-

TX0_HDMITXC_HDMI+

R103 120/F_4 TX0_HDMI-

TXC_HDMI-

TXC_HDMI+

100K/F_4

+5V R88 120/F_4

DIS Stuff 499 ohm CS14992FB24

F2 SMD1206P100TF +5V_HDMI_R 2 1

TXC_HDMI-

HDMI_DDCCLK HDMI_DDCDATA D16 SBR2U30SA

+5V_HDMI HDMI_DET

SHELL1 D2+ D2 Shield D2D1+ D1 Shield D1D0+ D0 Shield D0CK+ CK Shield CKCE Remote NC DDC CLK DDC DATA GND +5V HP DET SHELL2

20

B

21

HDMI CONN C419 .22u/10V_4 C211 *1000P/50V_4 {4} {4} {4} {4} {4} {4} {4} {4}

A

TX2_HDMI+ TX2_HDMITX1_HDMI+ TX1_HDMITX0_HDMI+ TX0_HDMITXC_HDMI+ TXC_HDMI-

TX2_HDMI+ TX2_HDMITX1_HDMI+ TX1_HDMITX0_HDMI+ TX0_HDMITXC_HDMI+ TXC_HDMI-

D17 +5V

2

R381

D18 +5V

2

HDMI_DDCCLK

1 CH501H-40PT

2K/F_4

C421 *1000P/50V_4

R382 HDMI _DDCDATA

1 CH501H-40PT

A

2K/F_4

Quanta Computer Inc. PROJECT : ZQZ Size

Document Number

Rev 1A

HDMI Date: 5

4

3

2

Thursday, February 23, 2012

Sheet 1

14

of

32

A

B

C

D

E

5 in 1 CARD READER IC (SD,MMC,xD,MS)

15 C743 close PIN46, 47

+1.8V_VDD

C708 close PIN48, 47

+3V 4

C431

C429

0.1u/16V_4

0.1u/16V_4

   L    E    S    L    A    T    X

   K    L    9   C    0 _    1    3   S    D    D    T _ _    M    /   #   S   S    E   E   M    /   M    /    L   W    1    0   7    C _   D    D   D _ _ _ _    D   D    X   D    D   D    X    /   /    X   /    X   /    X    #   /    P   D    1   0   7    D    W    C    D    D   D    M _ _ _ _ _    B   D   D    D    D   D    N    S   S   S   S   S

PIN43=Power saving mode enable. '1' for enable [Default] '0' for disable

CTRL0, CRTL 1 trace length shorter , and surround with GND. 4

C1_IOP U19 +3V

R391 *100K_4 R 39 0

{9,17,24} PLTRST# {8} {8} *15P/5 0V_4C *15P/50V_4C

+3V USBP5+ USBP5C420 C420

* sh or t_ 4

R 38 5

R 39 5

{9} CardReader_48M

C424 *0.47u/10V_6 * sh or t_ 6

R 38 7

* 30 0_ 4

22 _4 EXT48MHZ_R R 38 9

3 30 _4

+3V_VDD

C427 4.7u/10V_6

C425

C426

XI XO

*5p/50V_4

*5p/50V_4 +1.8V_VDD C428 4.7u/10V_6

3

    1    3    1    0    7    M     D    D    L    I     D    D    L     M     L    A    A    A     E    H    M     H    N    D    S     R    R     T    T    H     D    G    V    L     B    T    T    T     A    A    A    S     D     A     N    C    C    D    D    D    S     V     V     T _     X     1 1     C LED C1_VDDHM 2 EXT48IN DATA6 3   RSTN CTRL0 4 REXT DATA5 5 VD33P CTRL2 6 DP DATA4 AU6435B52-GDL-GR 7 DM DATA3 8 VS33P DATA2 9 XI XDWPN 10 XO XDCEN 11 VDD EEPDATA 12     N V18 EEPCLK     Y     N     V     S     3    P    V     N    E     5    5     M _     4    D     3    O    D     P     D     H     A     L     V    I     D    N     D    S    D    D     C    W     R _ _     3     1    1    V    G    3    D    S    N    D    T    D    D     C    C    A    A    V    V    V    G    V    C    X    S

 pin13 output 20mils

+3V

*27P/50V_4

XO

PIN45=Clock input selection '1' for 48MHz input [Default,Internal PU] '0' for 12MHz input

SD_D6/XD_D6 SD_CLK/XD_ALE/MS_BS SD_D5/XD_D5 SD_CMD_/XD_RB# SD_D4/XD_D4 SD_D3/XD_D3/MS_D3 SD_D2/XD_D2/MS_D2 XD_WP# XD_CE# EEPDATA EEPCLK T40 TP65

*0 _4 *0_4

R396 R3 96

XTALSEL

SD write protect 1:decided by SDWP[Default] 0:disable SD write protect

3

+1.8V_VDD

C430 0.1u/16V_4 C430 0.1u/1 6V_4 C435

R392 *270K_4

* 0_ 4 *0_4 R397 R 39 7 XD_CD# XD_RE#/MS_INS#

VCC_XD

+3V

Y4 *12MHZ C423

36 35 34 33 32 31 30 29 28 27 26 25

XI

*27P/50V_4

C440 C442 0.1u/16V_4 *4.7u/10V_6

    3    4    5    6    7    8    9    0    1    2    3    4     1    1    1    1    1    1    1    2    2    2    2    2

C1_IOP

C422

    8    7    6    5    4    3    2    1    0    9    8    7     4    4    4    4    4    4    4    4    4    3    3    3

+3V

2.2u/6 .3V_6 .3V  _6 C433 0.1u/16V_4

C436 4.7u/10V_6 C436 4.7u/1 0V_6

5 IN 1 CARD READER CONN (SD/MMC) VCC_XD

SD_CLK/XD_ALE/MS_BS and SD_CLK_R trace length shorter , surround with GND.

VCC_XD SD_CLK_R

2

CN5 SD_CD#/XD_WE# SD_WP/XD_CLE/MS_CLK SD_D1/XD_D1/MS_D1 SD_D0/XD_D0/MS_D0 SD_CLK/XD_ALE/MS_BS SD_CMD_/XD_RB# SD_D3/XD_D3/MS_D3 SD_D2/XD_D2/MS_D2 SD_D7/XD_D7 SD_D6/XD_D6 SD_D5/XD_D5 SD_D4/XD_D4

R136 R137 R140 R400 R402 R403 R138 R139 R399 R401

33_4 SD_D1_R 33_4 SD_D0_R 33_4 SD_CLK_R 33_4 SD_CMD_R 33_4 SD_D3_R 33_4 SD_D2_R 33_4 SD_D7_R 33_4 SD_D6_R 33_4 SD_D5_R 33_4 SD_D4_R

13 1 2 3 4 10 19 23 25 5 8 17 21 7 15 26 27

SD_WP/XD_CLE/MS_CLK

SD_CLK/XD_ALE/MS_BS SD_D1/XD_D1/MS_D1 SD_D0/XD_D0/MS_D0 SD_D2/XD_D2/MS_D2 XD_RE#/MS_INS# SD_D3/XD_D3/MS_D3 MS_CLK_R R 13 0 * sh or t_ 4

22 9 11 12 14 16 18 20

1

C262 *10P/50V_4

6 24

SD-VCC SD-CD-SW SD-WP-SW SD-DAT1 SD-DAT0 SD-CLK SD-CMD SD-DATA3 SD-DAT2 MMC-DATA7 MMC-DATA6 MMC-DATA5 MMC-DATA4 SD-GND1 SD-GND2 SD-WP-GND SD-CD-GND MS-VCC MS-BS MS-DATA1 MS-DATA0 MS-DATA2 MS-INS MS-DATA3 MS-SCLK

2

Reserved for combo connector, which has MS adaptor short issue with XDCDN XD-VCC XD-CD XD-R/B XD-RE XD-CE XD-CLE XD-ALE XD-WE XD-WP XD-D0 XD-D1 XD-D2 XD-D3 XD-D4 XD-D5 XD-D6 XD-D7

XD-GND1 XD-GND2

C265 *10p/50V_4

45 28 29 SD_CMD_/XD_RB# 30 XD_RE#/MS_INS# 31 XD_CE# 32 SD_WP/XD_CLE/MS_CLK 33 SD_CLK/XD_ALE/MS_BS 34 SD_CD#/XD_WE# XD_WP# 35 37 38 39 40 41 42 43 44

SD_D0/XD_D0/MS_D0 SD_D1/XD_D1/MS_D1 SD_D2/XD_D2/MS_D2 SD_D3/XD_D3/MS_D3 SD_D4/XD_D4 SD_D5/XD_D5 SD_D6/XD_D6 SD_D7/XD_D7

R 44 5

* sh or t_ 4 XD_CD# VCC_XD

C449 4.7u/10V_6

C516 0.1u/16V_4

C452 0.1u/16V_4

C450 0.1u/16V_4

R398 5.1K/F_4

36 46

1

MS-GND1 MS-GND2 R013-P13-HM

Quanta Computer Inc. SD_WP/XD_CLE/MS_CLK and MS_CLK_R trace length shorter , surround with GND.

PROJECT : ZQZ Size

Document Number

Rev 1A

AU6433 CardReader Date: A

B

C

D

Thursday, February 23, 2012

Sheet E

15

of

32

5

4

close Pin1

+3V_S5 R 34

+3V_LAN

* sh or t_ 8

3

LAN (LAN) Arthorus AR8151

C46

C48

C36

C35

C45

4.7u/10V_6

*4.7u/10V_6

1u/6.3V_4

0.1u/10V_4

1000p/50V_4

2

1 U8

X-TX1N X-TX1P X-TX0N X-TX0P

1 2 3 4

1 2 3 4

8 7 6 5

16

U11 X-TX3N X-TX3P X-TX2N X-TX2P

8 7 6 5

1 2 3 4

*UCLAMP2512T.TCT

1 2 3 4

8 7 6 5

8 7 6 5

*UCLAMP2512T.TCT

U2

1

D

{9,17} PCIE_RST# {8} PCIE_WAKE#

PCIE_RST#

2

PCIE_WAKE#

3 4

{8} PCIE_REQ_LAN# 0.1u/10V_4 0 .1 u/ 10 V_ 4 +VDDCT

C 34 C34 C 33

1 u/ 6. 3V _4

C 30 C30

0.1u/10V_4 0 .1 u/ 10 V_ 4

C 26

1 u/ 6. 3V _4

C 28 C28

0.1u/10V_4 0 .1 u/ 10 V_ 4

5

AVDDL_REG

6

XTLO

7

XTLI

8

AVDDH_REG R 32 R32

 

2.37K/F_4 2 .3 7K /F _4

9 RBIAS

10

TX0P

11

TX0N

12

XTLI

C25   0.1u/10V_4 0.1u/10V_4 AVDDL_REG 13 R33 *1M/F_4

XTLO

Y1

3

C

C31

4 15P/50V_4C

TX1P

14

TX1N

15

1

C24   0.1u/10V_4 0.1u/10V_4 AVDDH_REG 16

C27 2 15P/50V_4C 25MHZ

TX2P

17

TX2N

18

C23   0.1u/10V_4 0.1u/10V_4 AVDDL_REG 19

20120109: Change C27 and C31 from10P_4 to 15p_4

TX3P

20

TX3N

21

VDD33

AVDDH

PERSTn

CLKREQn/LED2

WAKEn

DVDDL

CLKREQn

SMCLK

AR8151

VDDCT

SMDATA

5X5mm

AVDDL_REG

40-Pin QFN

TX_N

AVDDH_REG

TX_P

RBIAS

AVDDL

TRXP0

REFCLK_N

TRXN0

REFCLK_P

NC/AVDDL

RX_P

TRXN1

RX_N

NC/AVDDH

DVDDL_REG

NC/TRXP2

LED0

NC/TRXN2

LED1

NC/AVDDL

LX

NC/TRXP3

GND

24

DVDDL_REG

C29 C29

0.1u/10V_4 0.1u/10V_4

D

TP1 C32 C32

U9

0.1u/10V 0.1u/10V_  _4 4

25

TP2

26

TP3

TX1N TX1P TX0N TX0P

1 2 3 4

1 2 3 4

8 7 6 5

U12 TX3N TX3P TX2N TX2P

8 7 6 5

1 2 3 4

*UCLAMP2512T.TCT

29

PCIE_RXN0_LAN_C C37

0.1u/10V_4

30

PCIE_RXP0_LAN_C C38

0.1u/10V_4

1 2 3 4

8 7 6 5

8 7 6 5

*UCLAMP2512T.TCT

31

AVDDL_REG

C39 C39

PCIE_RXN0_LAN {3} PCIE_RXP0_LAN {3}

0.1u/10V 0.1u/10V_  _4 4

32 33 34

AVDDL

TRXP1

LED2

28

TEST_RST

XTLI

AVDDH_REG

23

27

TESTMODE

XTLO

22

AVDDL_REG

C40 C40

CLK_PCIE_LANN

{9}

CLK_PCIE_LANP

{9}

0.1u/10V_4 0.1u/10V_4

35

PCIE_TXP0_LAN {3}

36

PCIE_TXN0_LAN {3}

37

DVDDL_REG

C 41

1 u/ 6. 3V _4

38

LAN_ACTLED#

C 42 C42

0.1u/10V_4 0 .1 u/ 10 V_ 4

39

LAN_LINKLED#

40

LX

L 33 L33

 

C +VDDCT

4.7uH/1A_2X2 4 .7 uH /1 A_ 2X 2

41

NC/TRXN3

C336

C331

C335

4.7u/10V_6

0.1u/10V_4

1000p/50V_4

AR8151

RJ45(LAN) CN7

TRANSFORMER(LAN)    P    0    X    T

B

4    9   .  9    /     F    _ 4  

   P    1    X    T

   N    0    X    TR 

R  1    8    8  

LAN_N1

1    8    9  

R  1    9    0  

4    9   .  9    /     F    _ 4  

4    9   .  9    /     F    _ 4  

   N    1    X    TR 

20120113: Change L31 P/N from CX08T601010  to CX8AG601003

LAN_N2

4    9   .  9    /     F    _ 4  

C311

C313

C314

0.1U/10V_4

*1000p/50V_4

0.1U/10V_4

*1000p/50V_4

R  1    9   2  

4    9   .  9    /     F    _ 4  

   P    3    X    T

   N    2    X    TR 

LAN_N3

1    9    3  

R  1    9   4  

4    9   .  9    /     F    _ 4  

4    9   .  9    /     F    _ 4  

AVDD_CEN

BLM18AG601SN1D BLM18AG601SN1D C 31 2

1    9   1  

C309

   P    2    X    T

Close Transformer

C316 C316

0.1u/10V_4 0.1u/10V_4

C2

* 10 00 p/ 50 V_ 4

C1 C1

0.1u/10V_4 0 .1 u/ 10 V_ 4

C306

*1000p/50V_4

C318 C318

0.1u/10V_4 0.1u/10V_4

C308

*1000p/50V_4

C310 C310

0.1u/10V_4 0.1u/10V_4

C320

*1000p/50V_4

LAN_N4

C317

C319

C321

0.1U/10V_4

*1000p/50V_4

0.1U/10V_4

*1000p/50V_4

X-TX0P X-TX0N X-TX1P X-TX2P X-TX2N X-TX1N X-TX3P X-TX3N

R187 5.1K/F_4

1 U/ 10 V_ 4

TX0P TX0N

1 2 3

TX1P TX1N

4 5 6

TX2P TX2N

7 8 9

TX3P TX3N

10 11 12

TCT1 TD1+ TD1-

MCT1 MX1+ MX1-

TCT2 TD2+ TD2-

MCT2 MX2+ MX2-

TCT3 TD3+ TD3-

MCT3 MX3+ MX3-

TCT4 TD4+ TD4-

MCT4 MX4+ MX4-

24 23 22

+3V_LAN

X-TX0P X-TX0N

R8

21 20 19

X-TX1P X-TX1N

18 17 16

X-TX2P X-TX2N

15 14 13

X-TX3P X-TX3N

220_8

1 2 3 4 5 6 7 8

LAN_LINKLED# 11 LAN_LNK_LED_PWR 12

YELLOW_N YELLOW_P GND2 GND1

0+ 01+ 2+ 213+ 3-

14 13

LANGND

B

GREEN_N GREEN_P RJ45

LAN_ACTLED#

TRANSFORMER

R196

*SHORT_8 *SHORT_8

LAN_LINKLED#

1    9    5  

C315

+VDDCT

9 10

2 20 20__88 LAN_ACT_LED_PWR

R 18866 R1

U10

   N    3    X    TR 

4    9   .  9    /     F    _ 4  

L31 L31

LAN_ACTLED#

Delta LFE9276D-R (DB0ZY8LAN00)

R3 75/F_8

R5 *75/F_8

R6 *75/F_8

R7 *75/F_8

20120111:  modify surge solution change D14 P/N from CY003100Z06 to CY231T20Z00

C307

C5

*0.01u/25V_4

*0.01u/25V_4

LANGND 20120111: Change R196 footprint to 0805

    2 R4

A

D14 *SG@B88069X9231T203

C3

A

1M_8 220p/3KV_1808

    1

Quanta Computer Inc. PROJECT : ZQZ

LANGND Size

Document Number

Date:

Thursday, February 23, 2012

Rev 1A

LAN (AR8151)

5

4

3

2

Sheet

1

16

of

32

1

2

3

4

5

6

7

8

+3V

Check LED signal. (active high or low)

MINI-CARD WLAN(MPC) +3.3V: 1000mA +3.3Vaux:330mA +1.5V:500mA

R 42 8

   2

Q25

C485 10u/10V_8

R444 10K_4

Q28

DTC144EUA

R460

CN21 A

TP94 R438 R436

{9,16} PCIE_RST# {9} PCLK_DEBUG

Ramp 0221:  modify net name

CL_RST1#_WLAN 0_4 PCIE_RST#_C 0_4 PCLK_DEBUG_R

+WL_VDD

PCIE_TXP1 PCIE_TXN1 PCIE_RXP1 PCIE_RXN1

{9} CLK_PCIE_WLANP {9} CLK_PCIE_WLANN PCIE_REQ_WLAN#_R

{24} PCIE_WAKE#_WLAN_R

1 PCIE_WAKE#_WLAN

3

51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1

Reserved Reserved Reserved Reserved GND +3.3Vaux +3.3Vaux GND GND PETp0 PETn0 GND GND PERp0 PERn0 GND UIM_C4 UIM_C8

+3.3V GND +1.5V LED_WPAN# LED_WLAN# LED_WWAN# GND USB_D+ USB_DGND SMB_DATA SMB_CLK +1.5V GND +3.3Vaux PERST# W_DISABLE# GND

GND REFCLK+ REFCLKGND CLKREQ# Reserved Reserved WAKE#

UIM_VPP UIM_RESET UIM_CLK UIM_DATA UIM_PWR +1.5V    D GND    N +3.3V    G

MINI-CARD1 Q29 *DTC144EUA 3

{8} PCIE_REQ_WLAN#

1

   3    5

16 14 12 10 8 6 4 2

+WL_VDD +WL_1.5V WLAN_OFF_R

R 45 4

* VA @0 _4

R426 *10K_4

WLAN_OFF {24} RF_LED# {22}

R 45 5

{24} IOAC_LANPWR#

USBP7-

R 42 7

* 30 0_ 4 C483

*15P/5 0V_4C

U23

+WL_VDD

PLTRST#_R

R 42 5

* VA @4 .7 K_ 4

C489 *1000P/50V_4

C487 *0.1u/10V_4

* 0_ 6

A

C486 *10u/6.3V_8

   5

2

PLTRST# {9,15,24}

1

IOAC_RST# {24}

4

RF_EN {24} 0_4 0_4 0_4 0_4 0_4

+1.5V

+WL_1.5V

+WL_VDD

PDAT_SMB {6,7,8,23} PCLK_SMB {6,7,8,23} +WL_1.5V

R429 R430 R431 R432 R433

17

C488 *0.1u/10V_4

+3V USBP7+ {8} USBP7- {8}

DEBUG_LFRAME# DEBUG_LAD3 DEBUG_LAD2 DEBUG_LAD1 DEBUG_LAD0

C484 *0.1u/10V_4

3

   2 C518 *[email protected]/10V_6

*VA@47K_4

*VA@TC7SH08FU    3 LPC_LFRAME# {9,24} LPC_LAD3 {9,24} LPC_LAD2 {9,24} Debug LPC_LAD1 {9,24} LPC_LAD0 {9,24}

R 45 6 R 45 7

* VA @0 _4 N VA @0 _4

+WL_1.5V +WL_VDD

   4    5

Ramp 0221:  Add IOAC circuit

   2

PCIE_REQ_WLAN#_R

B

   D    N    G

52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18

C490 0.1u/10V_4

*VA@AO3413

1

+3VPCU

3BT_PWRON

1

{3} {3}

N VA @0 _8

+WL_VDD

{21,24} BT_POWERON#

{3} {3}

+WL_VDD

B

+WL_VDD Q30 DTC144EUA

Ramp 0221:  Add Q29, Q30, Add net PCIE_REQ_W LAN#_R, PCIE_WAKE#_WLAN_R 

   2

+WL_VDD

mSATA

C

C

D

D

Quanta Computer Inc. PROJECT : ZQZ Size

Document Number

Rev 1A

MINI PCI-E card Date: 1

2

3

4

5

6

7

Thursday, February 23, 2012

Sheet

17 8

of

32

1

2

3

4

18

SATA HDD CN16

    1

A

1 2 3 4 SATA_RXN0_C 5 SATA_RXP0_C 6 7 8 9 10 11 12 13 C454 14 + 15 *100u/6.3V_3528 16 17 18 19

SATA_TXP0 {10} SATA_TXN0 {10} C432 C434

.01u/16V_4 .01u/16V_4

120mil

A

SATA_RXN0 {10} SATA_RXP0 {10}

+5V_HDD

R 40 5

C448

C447

C441

C445

C451

10u/6.3V_6

*0.1u/16V_4

*0.1u/16V_4

0.01u/25V_4

0.01u/25V_4

* sh or t_ 8

+5V

    9     1

SATA HDD B

B

SATA ODD

Zero Power (ODD)

+15V

6 5 2 1

CN10

C

GND14

14

GND1 RXP RXN GND2 TXN TXP GND3

1 2 3 4 5 6 7

DP +5V +5V RSVD GND GND GND15

+3VPCU SATA_TXP1 {10} SATA_TXN1 {10} SATA_RXN1_C SATA_RXP1_C

C150 C138

.01u/16V_4 .01u/16V_4

   1

R331 *100K

SATA_RXN1 {10} SATA_RXP1 {10}

8 9 10 11 12 13

ODD_PLUGIN#

R 32 2

* 1K _4

{10} FCH_ODD_EN

+5V_ODD

1

*100K    3

R324

*0_4

C353

C358

C360

C359

C357

*100u/6.3V_3528

10u/6.3V_6

*0.1u/16V_4

*0.1u/16V_4

0.01u/25V_4

0.01u/25V_4

{24}

ODD_EN

*0_4

2

R327 *100K

15

0 _8

R319 22_8    3M  O D    _ E  N    _  5   V 

   3 C

ODD_EN_Q 2 Q17 *DMN601K-7

   2 *0.1u/25V_6

   1

   1

   1

C18534-11305-L

+5V

R 31188 R3

4

C365

Q18 *DMN601K-7 R323

+5V_ODD

   1

ODD_EN_Q 2

   3

+5V_ODD

C352

       +

2

R328

   2

ODD_PLUGIN# {8}

Q16 *AO6402A

+5V

Q19 *DMN601K-7    1

   2

ODD_EJ_EC {24} R459 R 26611 R2

1 0K _4

*0_4

ODD_EJ

{8}

+3V

D

D

Ramp 0221:  Add R459

Quanta Computer Inc. PROJECT : ZQZ Size

Document Number

Rev 1A

SATA-HDD/ODD/HOLE Date: 1

2

3

Thursday, February 23, 2012

Sheet 4

18

of

32

5

4

3

FILT_1.65V

AUDIO CODEC

C509 1u/16V_6

2

1

LDO_OUT_3.3V

AVDD_3.3 pin is output of internal LDO. Do NOT connect to external supply.

C504 C510

C507

0.1u/10V_4

19

Codec(ADO)

10u/10V_8 0.1u/10V_4

3V_DVDD

Port Configuration ADOGND ADOGND

C471

C506

 Notes:

C480

10u/10V_8 0.1u/10V_4

0.1u/10V_4

Port Port Port Port Port Port Port Port Port

+5VA

D

3V_DVDD

(3.3Vor 1.5V)

C514

C505

10u/10V_8 0.1u/10V_4 C499 C478 1u/16V_6

R435 0.1/F_1206

3V_DVDD

0.1u/10V_4

Layout Note: Path fr om +5V to LPWR_5.0 and RPWR_5.0 must be very low resistance (
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