A Practical on-Chip Clock Controller Circuit Design

AppNote MG580225

A Practical On-Chip Clock Controller Circuit Design & Example Tessent® ATPG Test Case

January 2014

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Table of Contents 1.

Introduction............................................................................................................................................... 3

2.

On-Chip Clock Controller (OCC) Design Description ............................................................................... 3 2.1.

Design Placement............................................................................................................................ 3

2.2.

Schematic ........................................................................................................................................ 4

2.3.

Scan Enable Synchronization .......................................................................................................... 5

2.4.

Clock Gater Cells ............................................................................................................................. 5

2.5.

Internal Clock Definition for ATPG ................................................................................................... 5

2.6.

Shift Register Block ......................................................................................................................... 6

2.7.

Clock Control Operation Modes ....................................................................................................... 7

2.7.1. Functional Mode ...........................................................................................................................................7 2.7.2. Shift Mode ....................................................................................................................................................7 2.7.3. Slow Capture Mode ......................................................................................................................................8 2.7.4. Fast Capture Mode.......................................................................................................................................8 2.8.

Timing Diagrams.............................................................................................................................. 8

2.9.

RTL Description ............................................................................................................................... 10

Synthesized Gate Area ........................................................................................................................................11 3.

Test Case Description .............................................................................................................................. 12 3.1.

Test Case Design Statistics ............................................................................................................. 12

3.2.

Directory Structure ........................................................................................................................... 12

3.3.

Test Case Steps .............................................................................................................................. 13

3.4.

OCC RTL Simulation and Synthesis ................................................................................................ 13

Simulation ............................................................................................................................................................13 RTL Synthesis ......................................................................................................................................................14 3.5.

Step 1: View OCC Muxes ................................................................................................................ 14

3.6.

Step 2: Insert Clock Control Logic ................................................................................................... 15

3.7.

Step 3: Uncompressed Pattern Generation ..................................................................................... 17

3.8.

Step 4: Pattern Verification .............................................................................................................. 20

3.9.

Steps 5 to 8: Compression Logic Insertion, ATPG, and Verification ................................................ 21

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1. Introduction In modern designs, on-chip clock control (OCC) circuits are commonly used to manage clocks during test to ensure the following requirements are met:  Independent control by ATPG of each clock domain to improve coverage, reduce pattern count, and achieve safe clocking with minimal user intervention  During capture, deliver correct number of clock pulses on a per-pattern basis  Cleanly switch between shift and capture clocks  Enable slow or fast clocks during capture for application of slow and at-speed patterns  Scan-programmable clock waveforms generated within a wrapped core are ideal for generating patterns at the core level that can be retargeted to the top level while simultaneously testing multiple cores without conflicts in how clocks are controlled within each core This application note describes a practical on-chip clock control circuit design and demonstrates its use in a test case using Tessent® ATPG tools. If the target EDT hardware uses the Low Pin Count Test (LPCT) controller, contact Mentor Customer Support for information on how to use a modified OCC design with the LPCT EDT hardware. A complete test case that demonstrates the use of this OCC design in a circuit is described in the last section. The test case is available from Mentor Graphics by downloading it from the following SupportNet page: http://supportnet.mentor.com/reference/tutorials/index.cfm?id=MG576857

2. On-Chip Clock Controller (OCC) Design Description 2.1.

Design Placement

In order to avoid delay on the clock path due to test logic, a multiplexer should already exist on the clock source to the core flops and timed for functional behavior. The mux should be controlled by the test mode signal as shown in Figure 1 where existing logic is shown in gray.

Figure 1 – Clock Control Logic Design Placement It is important to only balance the functional clock path of the mux in order to avoid over-constraining the clock tree synthesis flow and causing excessive clock latency. For example, if using a layout tool like ICCompiler, this can be accomplished by using a set_clock_tree_exceptions -exclude_pins command and listing slow and fast clock inputs of the clock control block. In tools such as Talus from Magma, a skew group definition for each clock control block can be used. The clock control design described in this application note should supply the clock when in test mode while using the clock output of the PLL as the fast clock for at-speed capture. A top-level slow clock will be used for shift and slow capture. The reference clock supplied to the PLL is a free-running clock. It is also recommended not to flatten the clock control blocks during layout in order to ease definition of the test procedure file after layout. Mentor Graphics Confidential

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2.2.

Schematic

The schematic for the clock control circuit is shown in Figure 2 and the corresponding RTL can be found in section 2.9 of this document.

Figure 2 – On-Chip Clock Controller Logic Schematic The following table describes the functionality of pins at the top of the clock control block as well as some of the internal signals: Name

Direction

Description

SCAN_EN

Input

CAP_CYCLE_CONFIG [1:0]

Input 

SCAN_IN

Input

FAST_CAP_MODE

Input 

Selects fast or slow capture clock (0 = slow, 1 = fast)

TEST_MODE

Input 

Selects test or functional mode (0 = functional, 1 = test). During functional mode, the clock control block is disabled to minimize power and cross talk.

FAST_CLK

Input

Clock for fast capture (typically output of PLL)

SLOW_CLK

Input

Clock for shift and slow capture

SCAN_OUT

Output

Scan chain output for unloading shift register

CLK_OUT

Output

Controlled clock output

SCAN_EN_sync

Internal

Synchronized scan enable

SHIFT_REG_CLK_en

Internal

Clock enable signal for shift register

SHIFT_REG_CLK

Internal

Clock source for shift register

CLK_OUT_source

Internal

Clock source for controlled clock output

CLK_OUT_en

Internal

Clock enable signal for controlled clock output

Scan enable driven by top-level pin Configures number of clock pulses during capture cycle (maximum clock pulses = CAP_CYCLE_CONFIG + 1) as well as length of scan chain during shift Scan chain input for loading shift register

 Static signals that do not change during the test session can be controlled through on-chip controllers (such as JTAG) or other means in order to reduce the need for top-level pins.

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2.3.

Scan Enable Synchronization

In order to synchronize the top-level scan enable signal with the fast clock (PLL output), a two-flop synchronization cell is used and clocked by FAST_CLK. This is important because scan enable is used as the trigger signal to gate the clock to the shift register. The output of the synchronization cell produces a scan enable signal which is synchronized with the fast clock (SCAN_EN_sync) and can be used during fast capture test. In version 1.1 of the clock controller RTL, a flop was added on the input side of the synchronization cell and clocked by the trailing edge of SLOW_CLK. Since SCAN_EN normally fans out to the entire circuit and may arrive after FAST_CLK, the flop on SLOW_CLK ensures that SCAN_EN is not synchronized by the fast clock until SLOW_CLK is pulsed thus reducing the risk of a race condition. Note that the scan enable synchronization logic is not used for slow capture mode which uses SLOW_CLK for shift and capture. In the RTL description, the synchronization cell is described as module “tessent_sync_cell” so that it can be replaced with a technology specific synchronization cell from the appropriate library. module tessent_sync_cell (d, clk, q); input d, clk; output q; reg [1:0] R; always @ (posedge clk) begin R