A/L ICT Competency 2.3

January 13, 2017 | Author: Mohamed Irfan | Category: N/A
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Ez;nraypfspd; tpUj;jp (Evolution of Micro Processors) Model(intel)

Model(Motorola)

8088

-

Year

MHZ

TRANSISTORS

1979

8mhz

2900

-

6800

1979

8mhz

6800

80186

6810

1982

6mhz

5500

1982

20mhz

29000

1982

20mhz

-

1982

20mhz

134000

80188 -

68820

80286 80386

68050

1984

40mhz

190000

80486

68040

1990

60mhz

1180000

p.mmx

Power pc

1997

166-200mhz

-

2000

1.2ghz

7.5m

PII PIII

-

2001

1.8-3.8ghz

9.5m

PIV

-

2004

1.6-2.333ghz

42m

-

Power pc

2006

3.2ghz

52m

Core 2 dual

2006

1.6-2.333ghz

151m

Core 2 due

2006

1ghz-2.6ghz

291m

Core i7

2008

2.66-3.2ghz

730m

Ez; nrayp xd;wpd; tpguf;$w;W (specification of CPU) fzdpapd; cpu MdJ fzdpapd; ,ju ghfq;fSf;fhf mwpTWj;jy;> juT, epidtf tpyhrk; Nghd;w rkpf;iQfis ngw;Wf;nfhs;sTk; mtw;wpd; gad;ghL Kbe;jTld; cupa ,lq;fSf;F ,f; rkpf;iQfis fhtpr; nfy;yf;$ba ngsjPf fUtpfNs bus vdg;gLk;. fzdp jha;gyifapy; gpujhdkhf 3busfs; fhzg;gLfpd;wd.

1) juT g]; (Data bus):bus ,JthFk; mjhtJ epidtfj;jpypUe;J gjpaPf;fSf;F (register) juTfis mDg;Gjy; gpd;du; gjpapapy; xU ,lj;jpypUe;J fzdpapDs; ,d;DnkhU ,lj;jpw;F juTfis nfhz;L nry;y gad;gLk;

,Ue;J epidtfj;Jf;F juTfis ngw;Wf;nfhs;sy;, Cs;sPl;L fUtpfspypUe;J juTfis epidtfj;Jf;F nfhz;L tUjy; mNj Neuk; epidtfj;jpypUe;J ntspaPl;Lf;fUtpfSf;F mj;juTfis toq;Fjy;.

2) Kftup g];(Address bus) fzpdpapd; epidtfj;jpy; juTfshdJ rpwpa rpwpa myFfshf (cluster) gpupf;fg;gl;Ls;s epidtf gFjpfspNyNa Nrkpf;fg;gLk;. ,e;j xt;nthU rpwpa gFjpfSf;Fk; xt;nthU tpyhrKk; toq;fg;gl;bUf;Fk;. ,e;j tpyhrq;fis epidtfj;jpypUe;J register f;F Njitg;gLk;NghJ fhtpr;nry;fpd;w busNa ,JthFk;

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3) fl;Lg;ghl;L bus (control bus) ,J CPU tpypUe;J fzpdpapd; ,jug;ghfq;fSf;fhd nry;tjw;fhfntd;W cs;s busfNs ,JthFk;.

nraw;ghl;L

mwpTWj;jy;fspid

fhtpr;

fzpdpapd; fl;likg;gpd; tpUj;jpapid tpgupj;jy; (Explores the evolution of computer architecture) fbfhuk; clock  Xt;nthU fzpdpAk; Mff;Fiwe;jJ xU clock ia itj;jpUf;Fk;

 xU juT mirtpidfdpg;gPl;L eltbf;ifapid Nkw;nfhs;s xU Fwpg;gpl;l vz;zpf;ifahd clock cycle Njitg;gLk;.  vy;yh nraw;ghLfspYk; Ntfj;ij clock apid frequency Na jPu;khdpf;Fk;. ,J hz apy; mstplg;gLk;. vkJ fzpdpia ngWj;j tiu ,J Mhz, Ghz fspy; msf;fg;gLfpd;wJ.  nghJthf fzpdpapd; clock vd;gJ cpu tpd; clock Na Fwpf;Fk;. (master clock)  bus fSk; clock itj;jpUf;Fk; Mdhy; Ntfk; Fiwe;jJ.  ngJthf fzpdpapd; nraw;ghLfshdJ master clock apd; signal apdhNa fl;Lg;gLj;jg;gLk;.  Register MdJ Gjp juit Vw;Wf;nfhs;tjw;F Kjy; clock MdJ rkpf;iQapid jUk; tiu fhj;jpUf;fk;.  700Mhz vdgJ xU nrf;fd; ,w;fhf mjDila Rw;Wf;fspd; vz;zpf;ifia Fwpf;Fk;.

Von Neumann architecture (Von Neumann fl;likg;G ) ENIAC fzpdpapd; nraw;ghnlhd;W Rje;jpukhd ntspaPl;bw;F ngUk; jilahf ,Ue;jNjhL 1 f;F Nkw;gl;l epGzu;fspd; iffspNyNa jq;fpapUe;jJ. ,e;j epiyapiid Nghf;f Jhon Von Neuman vDk; tpQ;Qhdpapdhy; cUthf;fg;gl;lNj Von Neumann fl;likg;G MFk;. ,J Nrkpf;fg;gl;l fl;lis njhFjpapd; vz;zf;fU vdTk; miof;fg;gLfpd;wJ.( stored programme control

concept).

Vnddpy; ,e;j vz;zf;fUit nfhz;bUf;ff;$ba fzpdpfspy; mwpTWj;jy;> jufTis itj;jpUg;gjw;Fk; mtw;iw nrw;gLj;Jtjw;Fk; xU CPU Tk;, gpuj;jpNafkhd xU epidTf fl;likg;Gk; Ngzg;gLtjpdhNyahFk;.

Von Neumann fl;likg;gpw;F Vw;g fzpdpahdJ gpd;tUk; tplaq;fis nfhz;L fhzg;gLk;.  xU gpujhd epidtfk; ,J juT mwpTWj;jy;fis Nrkpj;J itj;jpUf;Fk;.  xU ALU ,J binary data f;fis nraw;gLj;jty;yJ.  Control unit ,J epidtfj;jpy; cs;s mwpTWj;jy;fis thrpj;J mjw;Nfw;g nraw;ghLfis Nkw;nfhs;sty;yJ.  Input, output cgfuzq;fs; ,J cu tpdhy; ,af;fg;gLk;

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,jd; fl;likg;G glkhdJ ikaKiw top myF(Central Processing Unit) fl;Lg;ghl;L myF (CONTROL UNIT)

vz;fzpj ju;f;f myF (ALU)

cs;sPl;L rhjdq;fs; INPUT DEVICES

Kjd;ik epidtfk; MAIN MEMORY (MAIN STORAGE) PRIMARY STORAGE

ntspaPl;L rhjdq;fs; OUTPUT DEVICES

Jizj; Njf;fk; AUXILIARY STORAGE (BACKING STORAGE) SECONDARY STORAGE

NkYk; Von Neuman fl;likg;ghdJ xU gq;fplg;gl;l epidtfj;ij mwpTWj;jy;> juTf;fhf itj;jpUg;gNjhL xU juT bus, Kftup bus apid processorw;Fk; epidtfj;jpw;FkpilNa mwpTWj;jYk; juTk; tupir Kiwg;gb nfhz;L tug;gLk;.

itj;jpUf;fpd;wJ.

,q;F

,f;fl;likg;Gld; njhlu;Gila ghfq;fSk; mtw;wpd; nraw;ghLfisAk; gpd;tUkhW Nehf;fyhk;.

kj;jpa nrw;ghl;L myF

Central processing unit (CPU)

 ,J fzpdpapd; mbg;gil nraw;ghLfis Nkw;nfhs;Sk;;.  epuypd; mwpTWj;jypid fetches, decodes, kw;Wk; execute gz;Zk;.  ,J 3 ghfq;fisf; nfhz;L fhzg;gLfpd;wd. fzpj kw;Wk; ju;f;f myF Arithmetic &Logical unit (ALU)  ,J xU data bus %yk; register kw;Wk; epidtfj;Jld; njhlu;G gl;bUf;Fk;.  ,J fzpj kw;Wk; ju;f;f uPjpahd nraw;ghlfis Nkw;nfhs;Sk;.  ,jDila nraw;ghLfs; fl;Lg;ghl;L myfpdhy; fl;Lg;gLj;jg;gLk;.  mbf;fb Register apid ghjpg;Gwr; nra;Ak; (Over flow, Carry) fl;Lg;ghl;L myF Control unit (cu)  ,J KOf;fzdpapd; Nghf;Ftuj;Jf;fl;Lg;ghl;L Kfhikahsuhf nraw;gLthu;.  Counter register kw;Wk; status register y; cs;s ngWkjpf;Nfw;g vd;d eltbf;ifapid Nkw;nfhs;s Ntz;Lk; vd;gjpid jPu;khdpf;Fk;.  CPUtpd; ghfq;fs; tupir Kiwahd eltbf;iffis Nkw;nfhs;s rkpf;iQfis mDg;Gk;.

gjpapf;fy; (Registers)  CPU tpdhy; gad;gLj;jjf;f dataf;fs,; mwpTWj;jy;fs; ,jpy; itj;jpUf;fg;glbUf;Fk;.  D-Flip Flop apdhy; eilKiwg;gLj;jg;gLk; epidtfk; Memory  ,J nra;epuypiaAk; juitAk; itj;jpUf;Fk;.  xU epiyahd bit mstpy; juTfs; Nrkpf;fg;gl;bUf;Fk;. -word(8>16>32>64)

 xt;nthU word ck; jdpj;Jtkhd tpyhrj;ij nfhz;bUf;Fk;.  me;j word apid ve;j xOq;F KiwapYk; mile;J nfhs;s KbAk;. (Random Access Memory) 3|ILM.Irfan

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 epidtf tpyhrkhdJ milahsk; ,lg;glhj KO vz;zpdhy; gpujpepjpj;Jtg; gLj;jg;gLk;. (unsigned integer)  tpyhrk; ,Lk; KiwahdJ. ---Byte thupahf tpyhrkplg;gl;bUf;Fk;. ----Word thupahf tpyhrkplg;gl;bUf;Fk;. Fetch – execute cycle / tl;lk; CPU

Memory ALU

MAR

Decode Register

IR

PC

MDR

CPU - central processing unit MAR – Memory address register MDR – memory data register IR – instruction register PC – programme counter ALU– Arithmetic logical unit mwpTWj;jiy nfhz;Ltuy; (Instruction fetch)  Programme counter (PC) apy; cs;s KftupahdJ memory address register(MAR) apy; itf;fg;gLk;.  MAR Kftupapy; cs;s mwpTWj;jyhdJ Memory Data Register apd; Clhf (MDR) Nrkpg;gfj;jpypUe;J thrpf;fg;gl;L instruction register apy; (IR) itf;fg;gLk;.

Instruction execute  gpd;du; instruction Decoder MdJ IR apy; cs;s mwTWj;jiy Muha;e;J mt; mwpTWj;jypdhy; toq;fg;gl;l tplaj;jpid nrad;Kiwg;gLj;Jtjw;fhd rkpf;iQfis ,ju ghfq;fSf;F mDg;Gk; ,J gpd;tUk; tplaq;fis cs;slf;fyhk;. 1) ALU MdJ epidtfk; register apy; cs;s operand (+,-,/,>,%,) fis thrpf;Fk;. 2) ALU tpy; cs;s Rw;Wf;fis (circuit) cupa fzpj kw;w fzpg;gpl;L eltbf;iffSf;fhf jahu; nra;jy;. 3) juT ngWkjpfis fzpdpapd; epidtfk; register apy; Nrkpj;jy;. 4) PC apd; ngWkjpapid khw;wy;. xU CPU tpd; Rw;whdJ vg;nghOJk; fetch, Decode, execute, fetch, decode, execute................ vd;W fhzg;gLk;.

 xt;nthU Rw;wpd; Muk;gj;jpNyAk; address bus ,d; ngWkjpahdJ programme counter w;F toq;fg;gLk;.  gpd;du; CPU thdJ mwpTWj;jypid gpujhd epidtfj;jpypUe;J (Cache and / or pipeline) data bus %yk; ngw;W Instruction Register w;F toq;Ffpd;wJ.

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