8255 function

8225 55 5F Fu un nccttiio on nss General The Intel 8255A Programmable peripheral interface (PPI) is a general purpose programmable I/O device which is designed for use with all Intel and most other microprocessors. Its function is that of a general purposes I/O component to Interface peripheral equipment to the microcomputer system bush. The functional configuration of the 8255A is programmed by the systems software so that normally no external logic is necessary to interface peripheral devices or structures.

It provides 24 I/O pins which may be individually programmed in 2 groups of 12 and used in 3 maj modes of operation. It can interface any TTL-compatible I/O device to microprocessor. The 8255 is a 40 pin integrated circuit (IC), designed to perform a variety of interface functions in a computer environment. The high performance and industry standard configuration of the 82C55A make it compatible with the 80C86, 80C88 and other microprocessors. Ports A, B, and C

The 8255A contains three 8-bit ports (A, B, and C). All can be configured in a wide variety of functional characteristics by the system software but each has its own special features or personally to further enhance the power and flexibility of the 8255A. Port A. One 8 bit data output latch/buffer and one 8-bit data input latch. Port B. One 8-bit data output latch/buffer and one 8-bit data input buffer.

Port C. One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and it be used for the controls signal outputs and status signal inputs in conjunction with ports A and B. Groups

The 8255 I/O Pins are divided into ports and are programmed as groups. Group A Connection consist of Port A (PA7 \u2013 PA0) and the upper half of Port C (PC7 \u2013 PC4). Group B (PB0 \u2013 PB7) and the lower half of Port C (PC3 \u2013 PC0).

It consists of Port B

Table 1-1 shows the I/O ports assignments used for programming and access the I/O Ports. In the perso computer the 8255 or its equivalent is decoded at I/O Ports 60H \u2013 63H.

Features:

A0 A1 0 0 0 1 1 0 1 1 Table 1-1

Function Port A Port B Port C Command Register

* 24 Programmable I/O Pins * Fully TTL Compatible * High Speed, No \u201cWait State\u201d Operation with 5MHz and 8MHz 1

* * * *

Direct Bit Set/Reset Capability Enhanced Control Word Read Capability 2.5mA Drive Capability on All I/O Ports Low Standby Power (ICCSB) . . . . . . . . . . . . . . . . . 10mA

PIN configuration

Data Bus Buffer

This 3-stable bi-directional 8-bit buffer is used to interface the 8255A to the systems data bus. Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU. Contro words and status information are also transferred through the data bus buffer. Read/Write and Control Logic

The function of this block is to manage all of the Internal and External transfers of both Data and Contr or Status words. It accepts inputs from the CPU Address and Control business and in turn, issues commands to both of the Control Groups.

CS: Chip Select A \u201clow\u201d on this input pin enables the communication between the 82C55A and the CPU mea microprocessor can read and write to the 8255.

RD: Read A \u201clow\u201d on this input pin enables 82C55A to send the data or status information to the CPU bus. In essence, it allows the CPU to \u201cread from\u201d the 82C55A. WR: Write A \u201clow\u201d on this input pin enables the CPU to write data or control words into the 82C55A. A0 and A1: Port Select 0 and Port Select 1 These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three ports or the control word register. They are normally connected to the least significant bits of the address bus (A0 and A1). D0 - D7: Data Select

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These are the data input/output lines for the device. All information read from and written to the 8255 occurs via these 8 data lines.

RESET A \u201chigh\u201d on this input initializes the control register to 9Bh and all ports (A, B, C) are set to mode. \u201cBus hold\u201d devices internal to the 82C55A will hold the I/O port inputs to a logic \u20 maximum hold current of 400\u00b5A. PA0 - PA7, PB0 - PB7, PC0 - PC7 These signal lines are used as 8-bit I/O ports. They can be connected to peripheral devices. The 8255 has three 8 bit I/O ports and each one can be connected to the physical lines of an external device. These lines are labeled PA0-PA7, PB0-PB7, and PC0-PC7. The groups of the signals are divided into three different I/O ports labeled port A (PA), port B (PB), and port C (PC).

Group A and Group B Controls The functional configuration of each port is programmed by the systems software. In essence, the CPU \u201coutputs\u201d a control word to the 82C55A. The control word contains information such as \u2 \u201cbit reset\u201d, etc., that initializes the functional configuration of the 82C55A. Each of the Control blocks (Group A and Group B) accepts \u201ccommands\u201d from the Read/Writ logic, receives \u201ccontrol words\u201d from the internal data bus and issues the proper commands ports.

Control Group A - Port A and Port C upper (C7 - C4) Control Group B - Port B and Port C lower (C3 - C0)

The control word register can be both written and read as shown in the \u201cBasic Operation\u201d t When the control word is read, bit D7 will always be logic \u201c1\u201d, as this implies control word m information.

Block diagram

Block diagram of the 8255

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Two control groups, labeled group A control and group B control define how the three I/O ports operate. There are several different operating modes for the 8255 and these modes must be defined by the CPU writing programming or control words to the device 8255. The line group of port C consists of two 4 bit ports. One of the 4 bit group is associated with group A control and the other 4 bit group with group B control device signals. The upper 4 bits of port C are associated with group A control while the lower 4 bits are associated with group B control.

The final logic blocks are read/write control logic and data bus buffer. These blocks provide the electri interface between the Z80 and the 8255. The data bus buffer buffers the data I/O lines to/from the Z80 data bus. The read/write control logic routes the data to and from the correct internal registers with the right timing. The internal path being enabled depends on the type of operation performed by the Z80. The type of operation can be I/O read or I/O write.

Control Word Register If bit 7 of the control word is a logical 1 then the 8255 will be configured.

Mode definition to configure the 8255.

of

the

8255

control

registers

If bit 7 of the control word is a logical 0 then each bit of the port C can be set or reset.

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Bit definitions of the 8255 control register to modify single bits of port C Examples: If you want to set/reset bit 0 of port C then set D3 to D1 to Bit 1 of port C will be set/reset if you code 001 to D3 to D1. Bit 6 of port C is set/reset if D3 to D1 is 110.

000.

Mode of 8255:

There are three basic modes of operation that can be selected by the systems software: * Mode O – Basic Input/Output * Mode 1 – Strobed Input/Output * Mode 2 – Bi-Directional Bus

When the reset Input goes “high” all ports will be set to the Input mode (i.e., all 24 lines will be in the h Impedance state). After the reset is removed the 8255A can remain in the input mode with no additiona Initialization required. During the execution of the systems program any of the other modes may be selected using a single output Instruction. This allows a single 8255A to service a variety of peripheral devices with a simple software maintenance routine.

Mode 0 (Basic Input/Output) This functional configuration provides simple input operations for each of the three ports. No “handshaking” is required data is simply written to or read from a specified port.

Mode O Basic Functional Definitions • • • • •

Two 8-bit ports and two 4-bit port Any port can be input or output. Outputs are not latched. Inputs are not latched. 16 different Input/output configurations are not possible in this Mode.

MODE 1 (Strobed Input/Output).

This functional configuration provides a means for transferring I/O data to or from a specified port in conjunction with strobes or “handshaking” signals. In mode 1, port A and Port B use the lines on port C generate or accept these “handshaking” signals.

Mode 1 Basic Functional Definitions • • • •

Two groups (Group A and Group B) Each group contains one 8-bit data port and one 4-bit control/data port The 8-bit data port can be either Inputs or output Both inputs and outputs are latched. The 4-bit port is used for control and status of the 8-bit data port.

Mode 2 (Strobed Bidirectional Bus I/O).

This functional configuration provides a means for communicating with a peripheral device or structure on a single 8-bit bus for both transmitting and receiving data (bi-directional bus I/O). “Handshaking” signals are provided to maintain proper bus flow discipline in a similar manner to MODE.

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MODE 2 Basic Functional Definitions • • • •

Used in Group A only. One 8-bit, bi-directional bus Port (Port A) and a 5-bit control Port (Port C). Both Inputs and Outputs are latched. The 5-bit control port (Port C) is used for control and status for the 8-bit,bi-directional bus port (Port A).

Interrupt Control Functions

When the 8255A is programmed to operate in mode 1 or mode 2, control signals are provided that can used as interrupt request input to the CPU. The interrupt request signal generated from port C, can be inhibited or enabled by setting or resetting the associated INTE flip-flop, using the bit set/reset function port C. This function allows the Programmer to disallow or allow a specific I/O device to interrupt the CPU without affecting any other device in the interrupt structure.

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