8 Bit x 8 Bit Pipelined Multiplier_doulos

2 7 / 1 2 /1 2

8 b i t x 8 b i t P i p e l i n e d M u l ti p l i e r  

8-bit x 8-bit Pipelined Multiplier  Briefly Brief ly interrupting interrupt ing the Built-in Built-in Self Test (BIST) (BIST) theme, this month w e present a s ynthes izable model model of  an 8-bit x 8-bit pipelined multiplier in Verilog.  Although the the design is is synthesizable s ynthesizable as is, a synthesis tool w ith a re-tim re-timing ing capabili capability ty is required in order to cr eate a pipelined pipelined multiplier w ith the pipeline regist registers ers ev enly distributed distr ibuted throughout the design. You can of course remove the pipeline_stages alw ays block and use the

un_pipelined_output assignment. You are w elcom elcome e to use the source c ode w e provide but you must must keep the copyright notice notice w ith the code (see theNotices theNotices page for details).

`timescale 1ns/1ps module mult_piped_8x8_2sC (a, b, clk, reset, y); input[7:0] a,b; input clk,reset; output[15:0] y; //-------------------------------------// Function: always @ posedge clk // //

y(t=0) = a(t-8) * b(t-8)

// Simulation: PASSED // Synthesis: Needs re-timing feature in // synthesis tool // //-------------------------------------reg[7:0] aR[8:0]; reg[7:0] bR[8:0]; reg[15:0] yR[8:0]; always @ (posedge clk) // pipeline_stages begin aR[7] = aR[6]; // pipeline statements bR[7] = bR[6]; yR[7] = yR[6]; aR[6] = aR[5]; bR[6] = bR[5]; yR[6] = yR[5]; aR[5] = aR[4]; bR[5] = bR[4]; yR[5] = yR[4]; aR[4] = aR[3]; bR[4] = bR[3]; yR[4] = yR[3]; aR[3] = aR[2]; bR[3] = bR[2]; www.doulos www.doulos.com/k .com/knowhow nowhow/ver /verilog_designers ilog_designers_guide/model _guide/model s/8bit_x_8bit_pipel ined_mul tipli er/

1/3

27/12/12

8 bit x 8 bit Pipelined Multiplier  

yR[3] = yR[2]; aR[2] = aR[1]; bR[2] = bR[1]; yR[2] = yR[1]; aR[1] = aR[0]; bR[1] = bR[0]; yR[1] = yR[0]; // multiply result (a*b) appears after +clk aR[0] = a; bR[0] = b; yR[0] = multiply_8x8_2sC (aR[0],bR[0]); end function[15:0] multiply_8x8_2sC; input[7:0] a,b; reg[7:0] a_mag,b_mag; reg[14:0] y_mag; reg[14:0] y_neg; begin case (a[7]) 0: a_mag = a[6:0]; 1: a_mag = 128 - a[6:0]; endcase

// max(a_mag) = 128, thus 8 bits

case (b[7]) 0: b_mag = b[6:0]; 1: b_mag = 128 - b[6:0]; endcase y_mag = a_mag * b_mag;

// max(y_mag) = 16384, thus 15 bits

if ((a[7] ^ b[7]) & (y_mag != 0)) // if (a * b) is -ve AND non-zero begin // y_mag >=1,