7th Sem VLSI Lab Manual using Mentor Graphics

2011-12

TH

7 SEM VLSI LAB MANUAL Department of Electronics and Communication Engg.

TABLE OF CONTENT 1. 7TH Sem VTU E&C VLSI LAB Syllabus 06ECL77 2. Part-A Digital Design - Digital Design Execution Steps 3. Test Constraints for Leonardo Spectrum 4. Part-A RV-VLSI Ref. Verilog Code - Main Module, Testbench, GateLevelTestbench 5. Part-B Analog Design - Analog Design Execution Steps 6. Schematic, Schematic Testbench, Excepted Waveforms 7. Parameters - nspice, spi, cir 8. User Guide - Using Mentor Graphics Design Kit

http://www.scribd.com/doc/63648062/7th-Sem-VLSI-Lab-Manual-using-Mentor-Graphics http://www.scribd.com/doc/63645000/User-Guide-Using-mentor-graphics-design-kit

7th Sem, VLSI Lab Manual

VTU-06ECL77

Subject Code : 06ECL77 No. of Practical Hrs/Week : 03 Total no. of Practical Hrs. : 42

2011-12 IA Marks Exam Hours Exam Marks

: 25 : 03 : 50

PART - A DIGITAL DESIGN

ASIC-DIGITAL DESIGN FLOW 1. Write Verilog Code for the following circuits and their Test Bench for verification, observe the waveform and synthesise the code with technological library with given Constraints*. Do the initial timing verification with gate level simulation. i. ii. iii. iv. v. vi. vii. viii.

An inverter A Buffer Transmission Gate Basic/universal gates Flip flop -RS, D, JK, MS, T Serial & Parallel adder 4-bit counter [Synchronous and Asynchronous counter] Successive approximation register [SAR]

* An appropriate constraint should be given PART - B ANALOG DESIGN Analog Design Flow 1. Design an Inverter with given specifications*, completing the design flow mentioned below: a. Draw the schematic and verify the following i) DC Analysis ii) Transient Analysis b. Draw the Layout and verify the DRC, ERC c. Check for LVS d. Extract RC and back annotate the same and verify the Design e. Verify & Optimize for Time, Power and Area to the given constraint*** 2. Design the following circuits with given specifications*, completing the design flow mentioned below: a. Draw the schematic and verify the following i) DC Analysis ii) AC Analysis iii) Transient Analysis b. Draw the Layout and verify the DRC, ERC c. Check for LVS d. Extract RC and back annotate the same and verify the Design. i) A Single Stage differential amplifier ii) Common source and Common Drain amplifier

3. Design an op-amp with given specification* using given differential amplifier Common source and Common Drain amplifier in library** and completing the design flow mentioned below: a. Draw the schematic and verify the following i) DC Analysis ii). AC Analysis iii) Transient Analysis b. Draw the Layout and verify the DRC, ERC c. Check for LVS d. Extract RC and back annotate the same and verify the Design.

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7th Sem, VLSI Lab Manual

VTU-06ECL77

2011-12

4. Design a 4 bit R-2R based DAC for the given specification and completing the design flow mentioned using given op-amp in the library**. a. Draw the schematic and verify the following i) DC Analysis ii) AC Analysis iii) Transient Analysis b. Draw the Layout and verify the DRC, ERC c. Check for LVS d. Extract RC and back annotate the same and verify the Design. 5. For the SAR based ADC mentioned in the figure below draw the mixed signal schematic and verify the functionality by completing ASIC Design FLOW. [Specifications to GDS-II]

* Appropriate specification should be given. ** Applicable Library should be added & information should be given to the Designer. *** An appropriate constraint should be given

http://www.scribd.com/doc/63648062/7th-Sem-VLSI-Lab-Manual-using-Mentor-Graphics

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7th Sem, VLSI Lab Manual PART – A: DIGITAL DESIGN STEPS IN LINUX TERMINAL Linux Terminal Steps: Username: student01 Password: student01 1. Open Terminal from Desktop i.e. Right Click in the center of plane Desktop and use “Open Terminal” 2. Start the License Server 3. Check the License Manager Status 4. Create Directory with Student USN as Directory Name 5. Inside Student USN Directory Create Workspace directory 6. Copy Library files (i.e. tsmc018_typ.syn and adk.v) from /home/student01/libraries/ 7. Here are some Commands in Steps 1 8. Follow the below Steps 2 to execute front end programs

2011-12

Note: $  Linux prompt Just like C:\> MS DOS prompt Linux is Case sensitive  Always use only Small Letters/Alphabets

␢ Space Character/Symbol/Space bar

↵ Carriage Return/Enter key Symbol/Enter key Steps 1:

$ source␢.cshrc↵ $ Lmstat↵ $ mkdir␢1ce01ec001↵ $ cd␢1ce01ec001↵ /1ce01ec001$ vlib␢work↵ /1ce01ec001$ cp␢/home/student01/libraries/*␢.↵ /1ce01ec001$ vi␢inverter.v↵ /1ce01ec001$ vlog␢inverter.v␢inverter_test.v↵ /1ce01ec001$ vlog␢inverter_net.v␢inverter_gatetest.v␢adk.v↵ Rest of the commands please follow STEPS 2

/1ce01ec001$ vsim␢–c␢inverter_test␢–novopt↵ /1ce01ec001$ vsim␢inverter_test␢–novopt↵ Menu Mode /1ce01ec001$ spectrum↵ /1ce01ec001$ ls↵ /1ce01ec001$ cd␢..↵ $ pwd↵ $ cd␢\↵ $ pwd␢--help↵ :wproj1.v $ vi␢--help↵ $ exit↵

Insert

or

Insert Mode

I

Esc

--Insert--

Vi editor

Vi editors basic commands

:q Quit VI. If there have been changes made, the editor will issue a warning message. :q! Quit VI without saving changes. :vi␢proj1.vStarts editing a new file. If changes have not been saved, the editor will give you awarning. :w Write out the current file. :w␢proj2.v Write the buffer to the filename specified. :wq Write the buffer and quit. :wq! Write the buffer and force quit.

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7th Sem, VLSI Lab Manual PART – A: DIGITAL DESIGN STEPS IN LINUX TERMINAL 2011-12 Steps 2: 1. Create Mainmodule Verilog $ vi␢sync_counter.v↵ 2. Check Syntax error of Only Mainmodule Verilog $ vlog␢sync_counter.v↵ 3. Create Testbench to test Mainmodule Verilog $ vi␢sync_counter_testbench.v↵ 4. Check Syntax error of Only Testbench $ vlog␢sync_counter_testbench.v↵ 5. Check compatibility of both Top/Mainmodule and Testbench together to obtain Top-module name $ vlog␢sync_counter.v␢sync_counter_testbench.v↵ 6. Simulate Testbench in Text mode using Top-module name in Vsim $ vsim␢–c␢sync_counter_testbench␢–novopt↵ VSIM1> run␢-all↵ : VSIM2> exit↵ 7. Simulate Testbench in GUI/Graphical mode in Modelsim $ vsim␢sync_counter_testbench␢–novopt↵ 8. Generate SDF and Netlist file from Spectrum using constraints provided $ spectrum↵ load_library␢tsmc018_typ.syn↵ read␢-format␢verilog␢sync_counter.v↵ set␢input2register␢ 2.00↵ set␢input2output ␢ 3.00↵ set␢register2output ␢ 3.00↵ set␢register2register␢ 3.20↵ clock_cycle␢3.2␢clock↵ set_attribute␢-name␢ARRIVAL_TIME␢-value␢"0.4"␢-port␢reset↵ set_attribute␢-name␢ARRIVAL_TIME␢-value␢"0.4"␢-port␢down↵ set_attribute␢-name␢ARRIVAL_TIME␢-value␢"0.4"␢-port␢up↵ optimize↵ write␢-format␢verilog␢sync_counter_netlist.v↵ write␢-format␢sdf␢sync_counter.sdf↵ report_delay␢ >␢delay.rpt↵ report_area␢>␢area.rpt↵ exit↵ 9. Create Gatelevel Testbench to test Mainmodule Verilog using 180 nm Technology $ vi␢sync_counter_gatetestbench.v↵ 10. Check Syntax error of Only Gatelevel Testbench $ vlog␢sync_counter_gatetestbench.v↵ 11. Check compatibility of Netlistfile, Gatelevel Testbench and adk.v library together to obtain Top-module name w.r.t. 180 nm Technology $ vlog␢sync_counter_netlist.v␢sync_counter_gatetestbench.v␢adk.v↵ 12. Simulate Gatelevel Testbench in Text mode using Top-module name in Vsim $ vsim␢–c␢sync_counter_gatetestbench␢–novopt↵ VSIM1> run␢-all↵ : VSIM2> exit↵ 13. Simulate Gatelevel Testbench in GUI/Graphical mode in Modelsim using Top-module name $ vsim␢sync_counter_gatetestbench␢–novopt↵ 14. To Exit the Linux Terminal $ exit↵ Dept. of E&C, CEC

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SKLN, RCVK

7th Sem, VLSI Lab Manual LEONARDO SPECTRUM CONSTRAINTS sync_counter.tcl load_library tsmc018_typ.syn tflipflop.tcl read -format verilog sync_counter.v load_library tsmc018_typ.syn set input2register 2.00 read -format verilog tflipflop.v set input2output 3.00 clock_cycle 1 clock_i set register2output 3.00 set input2register 0.5 set register2register 3.20 set register2register 1 clock_cycle 3.2 clock set register2output 0.5 set_attribute -name ARRIVAL_TIME -value "0.4" -port reset optimize set_attribute -name ARRIVAL_TIME -value "0.4" -port down write -format verilog tflipflop_netlist.v set_attribute -name ARRIVAL_TIME -value "0.4" -port up write -format sdf tflipflop.sdf optimize write -format verilog sync_counter_netlist.v buffer.tcl write -format sdf sync_counter.sdf load_library tsmc018_typ.syn report_delay > delay.rpt read -format verilog buffer.v set input2output 0.6 report_area > area.rpt optimize write -format verilog buffer_netlist.v Async_counter.tcl write -format sdf buffer.sdf load_library tsmc018_typ.syn read -format verilog Async_counter.v serial_adder.tcl elaborate load_library tsmc018_typ.syn set input2register 2.00 read -format verilog full_adder.v set input2output 3.00 read -format verilog serial_adder_4bit.v set register2output 3.00 set input2output 1 set register2register 3.20 optimize clock_cycle 3.2 Clock write -format verilog serialadder_netlist.v set_attribute -name ARRIVAL_TIME -value "0.4" -port Reset write -format sdf serialadder.sdf optimize write -format verilog Async_counter_netlist.v sar.tcl write -format sdf Async_counter.sdf load_library tsmc018_typ.syn report_delay > delay.rpt read -format verilog sar.v report_area > area.rpt set input2register 2.00 set input2output 3.00 dflipflop.tcl set register2output 3.00 load_library tsmc018_typ.syn set register2register 3.20 read -format verilog dflipflop.v clock_cycle 3.2 clock_i optimize optimize write -format verilog dflipflop_netlist.v write -format verilog sar_netlist.v write -format sdf dflipflop.sdf write -format sdf sar.sdf report_delay > delay.rpt master_slave.tcl report_area > area.rpt load_library tsmc018_typ.syn read -format verilog dflipflop.v parllel_adder.tcl read -format verilog masterslave_flipflop.v load_library tsmc018_typ.syn clock_cycle 1 clock_i read -format verilog parllel_adder.v set input2register 0.5 set input2output 1 set register2register 1 optimize set register2output 0.5 write -format verilog parlleladder_netlist.v optimize write -format sdf parlleladder.sdf write -format verilog master_slave_netlist.v write -format sdf masterslave.sdf tgate.tcl load_library tsmc018_typ.syn rsflipflop.tcl read -format verilog tgate.v load_library tsmc018_typ.syn optimize read -format verilog dflipflop.v write -format verilog tgate_netlist.v read -format verilog rsflipflop.v write -format sdf tgate.sdf synthesize optimize write -format verilog rsflipflop_netlist.v write -format sdf rsflipflop.sdf Dept. of E&C, CEC

1

2011-12

SKLN, RCVK

7th Sem, VLSI Lab Manual

LEONARDO SPECTRUM CONSTRAINTS

2011-12 Steps: 1. Create Mainmodule Verilog $ vi sync_counter.v 2. Check Syntax error of Only Mainmodule Verilog $ vlog sync_counter.v 3. Create Testbench to test Mainmodule Verilog $ vi sync_counter_testbench.v 4. Check Syntax error of Only Testbench $ vlog sync_counter_testbench.v 5. Check compatibility of both Top/Mainmodule and Testbench together to obtain Top-module name $ vlog sync_counter.v sync_counter_testbench.v 6. Simulate Testbench in Text mode using Top-module name in Vsim $ vsim –c sync_counter_testbench –novopt run -all 7. Simulate Testbench in GUI/Graphical mode in Modelsim $ vsim sync_counter_testbench –novopt 8. Generate SDF and Netlist file from Spectrum using constraints provided $ spectrum

inverter_syn.tcl load_library tsmc018_typ.syn read -format verilog inverter.v set input2output 0.5 optimize write -format verilog inverter_netlist.v write -format sdf inverter.sdf basic_gate.tcl load_library tsmc018_typ.syn read -format verilog and.v present_design set input2output 1 optimize write -format verilog basic_gates_and.v write -format sdf basic_gates_and.sdf report_delay > and_delay.rpt read -format verilog or.v present_design set input2output 1 optimize write -format verilog basic_gates_or.v write -format sdf basic_gates_or.sdf report_delay > or_delay.rpt



read -format verilog nand.v present_design set input2output 1 optimize write -format verilog basic_gates_nand.v write -format sdf basic_gates_nand.sdf report_delay > nand_delay.rpt read -format verilog nor.v present_design set input2output 1 optimize write -format verilog basic_gates_nor.v write -format sdf basic_gates_nor.sdf report_delay > nor_delay.rpt

9. Create Gatelevel Testbench to test Mainmodule Verilog using 180 nm Technology $ vi sync_counter_gatetestbench.v 10. Check Syntax error of Only Gatelevel Testbench $ vlog sync_counter_gatetestbench.v 11. Check compatibility of Netlistfile, Gatelevel Testbench and adk.v library together to obtain Topmodule name w.r.t. 180 nm Technology $ vlog sync_counter_netlist.v sync_counter_gatetestbench.v adk.v 12. Simulate Gatelevel Testbench in Text mode using Top-module name in Vsim $ vsim –c sync_counter_gatetestbench –novopt run -all 13. Simulate Gatelevel Testbench in GUI/Graphical mode in Modelsim using Top-module name $ vsim sync_counter_gatetestbench –novopt

read -format verilog xor.v present_design set input2output 1 optimize write -format verilog basic_gates_xor.v write -format sdf basic_gates_xor.sdf report_delay > xor_delay.rpt read -format verilog xnor.v present_design set input2output 1 optimize write -format verilog basic_gates_xnor.v write -format sdf basic_gates_xnor.sdf report_delay > xnor_delay.rpt Dept. of E&C, CEC

load_library tsmc018_typ.syn read -format verilog sync_counter.v set input2register 2.00 set input2output 3.00 set register2output 3.00 set register2register 3.20 clock_cycle 3.2 clock set_attribute -name ARRIVAL_TIME -value "0.4" -port reset set_attribute -name ARRIVAL_TIME -value "0.4" -port down set_attribute -name ARRIVAL_TIME -value "0.4" -port up optimize write -format verilog sync_counter_netlist.v write -format sdf sync_counter.sdf report_delay > delay.rpt report_area > area.rpt exit

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SKLN, RCVK

Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab

CEC-2011

//INVERTER module inverter ( input_i, output_o ) ; input input_i ; output output_o ; reg output_o; always @(input_i) begin if (input_i) output_o = 1'b0; else output_o = 1'b1; end endmodule //INVERTER TESTBENCH module inverter_test ; reg input_i ; wire output_o; inverter inverter_dut(.input_i(input_i ), .output_o(output_o)); initial input_i = 1'b0; always #5 input_i = !input_i; initial begin $monitor ($time ," Input_i =%b and output_o =%b " ,input_i,output_o); #2000 $finish ; end endmodule //INVERTER GATELEVEL TESTBENCH module inverter_test ; reg input_i ; wire output_o; inverter inverter_dut(.input_i(input_i ),.output_o(output_o)); initial input_i = 1'b0; always #5 input_i = !input_i; initial begin $monitor ($time ," Input_i =%b and output_o =%b " ,input_i,output_o); #2000 $finish ; end initial begin $sdf_annotate("inverter.sdf",inverter_test.inverter_dut, , , "maximum"); end endmodule VK

Mentor Graphics

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Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab

CEC-2011

//BUFFER module buffer (input_i,output_o); input input_i; output output_o; reg output_o; always @(input_i) begin if (input_i) output_o = 1'b1; else output_o = 1'b0; end endmodule //BUFFER TESTBENCH module buffer_test ; reg input_i ; wire output_o; buffer buffer_dut(.input_i(input_i ), .output_o(output_o)); initial input_i = 1'b0; always #5 input_i = !input_i; initial begin $monitor ($time ," Input_i =%b and output_o =%b " ,input_i,output_o); #2000 $finish ; end endmodule //BUFFER GATE LEVEL TESTBENCH module buffer_test ; reg input_i ; wire output_o; buffer buffer_dut(.input_i(input_i ),.output_o(output_o)); initial input_i = 1'b0; always #5 input_i = !input_i; initial begin $monitor ($time ," Input_i =%b and output_o =%b " ,input_i,output_o); #2000 $finish ; end initial $sdf_annotate("buffer.sdf",buffer_test.buffer_dut); endmodule VK

Mentor Graphics

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Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab

CEC-2011

//TRANSMISSION GATE module tgate (input_i, cntrl_i,output_o); input input_i; input cntrl_i; output output_o; reg output_o; always @(input_i or cntrl_i) begin if (cntrl_i) output_o = input_i; else output_o = 1'b0; end endmodule //TRANSMISSION GATE TESTBENCH module tgate_test ; reg input_i ; reg cntrl_i ; wire output_o; tgate tgate_dut(.input_i(input_i ),.cntrl_i(cntrl_i ),.output_o(output_o)); initial begin input_i = 1'b0; cntrl_i =1'b1; #100 cntrl_i =1'b0 ; #200 cntrl_i =1'b1 ; end always #5 input_i = !input_i; initial begin $monitor ($time ," Input_i =%b cntrl_i =%b and output_o =%b " ,input_i,cntrl_i,output_o); #2000 $finish ; end endmodule //TRANSMISSION GATE GATELEVEL TESTBENCH module tgate_test ; reg input_i ; reg cntrl_i ; wire output_o; tgate tgate_dut(.input_i(input_i ),.cntrl_i(cntrl_i ),.output_o(output_o)); initial begin input_i = 1'b0; cntrl_i =1'b1; #100 cntrl_i =1'b0 ; VK

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Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab

#200 cntrl_i =1'b1 ; end

CEC-2011

always #5 input_i = !input_i; initial begin end

$monitor ($time ," Input_i =%b cntrl_i =%b and output_o =%b " ,input_i,cntrl_i,output_o); #2000 $finish ;

initial $sdf_annotate("tgate.sdf",tgate_test.tgate_dut,, ,"Maximum"); endmodule

//BASIC AND GATE module basic_gate_and(a_i, b_i, c_o); input a_i; input b_i; output c_o; wire c_o; assign c_o = a_i && b_i; endmodule //BASIC OR GATE module basic_gate_or(a_i,b_i,c_o); input a_i; input b_i; output c_o; wire c_o; assign c_o = a_i || b_i; endmodule //BASIC NAND GATE module basic_gate_nand(a_i,b_i,c_o); input a_i; input b_i; output c_o; wire c_o; assign c_o = ~(a_i && b_i); endmodule

VK

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Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab

CEC-2011

//BASIC NOR GATE module basic_gate_nor(a_i,b_i ,c_o); input a_i; input b_i; output c_o; wire c_o; assign c_o = ~(a_i || b_i); endmodule //BASIC XOR GATE module universal_gate_xor(a_i,b_i,c_o); input a_i; input b_i; output c_o; wire c_o; assign c_o = a_i ^ b_i; endmodule //BASIC XNOR GATE module universal_gate_xnor(a_i, b_i, c_o); input a_i; input b_i; output c_o; wire c_o; assign c_o = ~(a_i ^ b_i); endmodule //BASIC UNIVERSAL GATES TESTBENCH module basic_gates_test ; reg a_i ; reg b_i ; wire [5:0]c_o; basic_gate_and and_dut(.a_i(a_i ), .b_i(b_i ), .c_o(c_o[0])); basic_gate_or or_dut(.a_i(a_i ), .b_i(b_i ),.c_o(c_o[1])); basic_gate_nand nand_dut(.a_i(a_i ),.b_i(b_i ),.c_o(c_o[2])); basic_gate_nor nor_dut(.a_i(a_i ),.b_i(b_i ),.c_o(c_o[3])); universal_gate_xor xor_dut(.a_i(a_i ),.b_i(b_i ),.c_o(c_o[4])); universal_gate_xnor xnor_dut(.a_i(a_i ),.b_i(b_i ),.c_o(c_o[5]));

VK

Mentor Graphics

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Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab

CEC-2011

initial begin $display ( $time ,"\t simulation of the and_gate begins " ); a_i =1'b0 ; b_i =1'b0; #10 a_i =1'b0 ; b_i =1'b1; #10 a_i =1'b1 ; b_i =1'b0; #10 a_i =1'b1 ; b_i =1'b1; #5 $display ( " \n" ); end initial begin #40 $display ( $time ," \t simulation of the or_gate begins " ); #10 a_i =1'b0 ; b_i =1'b0; #10 a_i =1'b0 ; b_i =1'b1; #10 a_i =1'b1 ; b_i =1'b0; #10 a_i =1'b1 ; b_i =1'b1; #5 $display ( " \n" ); end initial begin #100 $display ( $time ," \t simulation of the nand_gate begins " ); #10 a_i =1'b0 ; b_i =1'b0; #10 a_i =1'b0 ; b_i =1'b1; #10 a_i =1'b1 ; b_i =1'b0; #10 a_i =1'b1 ; b_i =1'b1; #5 $display ( " \n" ); end initial begin #150 $display ( $time ," \t simulation of the nor_gate begins " ); #10 a_i =1'b0 ; b_i =1'b0; #10 a_i =1'b0 ; b_i =1'b1; #10 a_i =1'b1 ; b_i =1'b0; #10 a_i =1'b1 ; b_i =1'b1; #5 $display ( " \n" ); end initial begin #200 $display ( $time ," \t simulation of the xor_gate begins " ); #10 a_i =1'b0 ; b_i =1'b0; #10 a_i =1'b0 ; b_i =1'b1; #10 a_i =1'b1 ; b_i =1'b0; #10 a_i =1'b1 ; b_i =1'b1; #5 $display ( " \n" ); end VK

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Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab

CEC-2011

initial begin #250 $display ( $time ," \t simulation of the xnor_gate begins " ); #10 a_i =1'b0 ; b_i =1'b0; #10 a_i =1'b0 ; b_i =1'b1; #10 a_i =1'b1 ; b_i =1'b0; #10 a_i =1'b1 ; b_i =1'b1; #5 $display ( " \n" ); end initial begin #300 $finish ; end initial begin fork $monitor ( $time , "\t a=%b b =%b and output of and gate c= %b" ,a_i,b_i,c_o[0] ); #50 $monitor ( $time , "\t a=%b b =%b and output of or gate c= %b" ,a_i,b_i,c_o[1] ); #110 $monitor ( $time , "\t a=%b b =%b and output of nand gate c= %b" ,a_i,b_i,c_o[2] ); #160 $monitor ( $time , "\t a=%b b =%b and output of nor gate c= %b" ,a_i,b_i,c_o[3] ); #210 $monitor ( $time , "\t a=%b b =%b and output of xor gate c= %b" ,a_i,b_i,c_o[4] ); #260 $monitor ( $time , "\t a=%b b =%b and output of xnor gate c= %b" ,a_i,b_i,c_o[5] ); join end endmodule //BASIC UNIVERSAL GATES GATELEVEL TESTBENCH module basic_gates_test ; reg a_i ; reg b_i ; wire [5:0]c_o; basic_gate_and and_dut(.a_i(a_i ),.b_i(b_i ),.c_o(c_o[0])); basic_gate_or or_dut(.a_i(a_i ),.b_i(b_i ),.c_o(c_o[1])); basic_gate_nand nand_dut( .a_i(a_i), .b_i(b_i ), .c_o(c_o[2])); basic_gate_nor nor_dut( .a_i(a_i ), .b_i(b_i ), .c_o(c_o[3])); universal_gate_xor xor_dut( .a_i(a_i ), .b_i(b_i ), .c_o(c_o[4])); universal_gate_xnor xnor_dut( .a_i(a_i ), .b_i(b_i ), .c_o(c_o[5])); initial begin $display ( $time ,"\t simulation of the and_gate begins " ); a_i =1'b0 ; b_i =1'b0; #10 a_i =1'b0 ; b_i =1'b1; #10 a_i =1'b1 ; b_i =1'b0; #10 a_i =1'b1 ; b_i =1'b1; #5 $display ( " \n" ); end VK

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Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab

CEC-2011

initial begin #40 $display ( $time ," \t simulation of the or_gate begins " ); #10 a_i =1'b0 ; b_i =1'b0; #10 a_i =1'b0 ; b_i =1'b1; #10 a_i =1'b1 ; b_i =1'b0; #10 a_i =1'b1 ; b_i =1'b1; #5 $display ( " \n" ); end initial begin #100 $display ( $time ," \t simulation of the nand_gate begins " ); #10 a_i =1'b0 ; b_i =1'b0; #10 a_i =1'b0 ; b_i =1'b1; #10 a_i =1'b1 ; b_i =1'b0; #10 a_i =1'b1 ; b_i =1'b1; #5 $display ( " \n" ); end initial begin #150 $display ( $time ," \t simulation of the nor_gate begins " ); #10 a_i =1'b0 ; b_i =1'b0; #10 a_i =1'b0 ; b_i =1'b1; #10 a_i =1'b1 ; b_i =1'b0; #10 a_i =1'b1 ; b_i =1'b1; #5 $display ( " \n" ); end initial begin #200 $display ( $time ," \t simulation of the xor_gate begins " ); #10 a_i =1'b0 ; b_i =1'b0; #10 a_i =1'b0 ; b_i =1'b1; #10 a_i =1'b1 ; b_i =1'b0; #10 a_i =1'b1 ; b_i =1'b1; #5 $display ( " \n" ); end initial begin #250 $display ( $time ," \t simulation of the xnor_gate begins " ); #10 a_i =1'b0 ; b_i =1'b0; #10 a_i =1'b0 ; b_i =1'b1; #10 a_i =1'b1 ; b_i =1'b0; #10 a_i =1'b1 ; b_i =1'b1; #5 $display ( " \n" ); end VK

Mentor Graphics

8

Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab

initial begin end initial begin

end initial begin

end

CEC-2011

#300 $finish ;

fork $monitor ( $time , "\t a=%b b =%b and output of and gate c= %b" ,a_i,b_i,c_o[0] ); #50 $monitor ( $time , "\t a=%b b =%b and output of or gate c= %b" ,a_i,b_i,c_o[1] ); #110 $monitor ( $time , "\t a=%b b =%b and output of nand gate c= %b" ,a_i,b_i,c_o[2] ); #160 $monitor ( $time , "\t a=%b b =%b and output of nor gate c= %b" ,a_i,b_i,c_o[3] ); #210 $monitor ( $time , "\t a=%b b =%b and output of xor gate c= %b" ,a_i,b_i,c_o[4] ); #260 $monitor ( $time , "\t a=%b b =%b and output of xnor gate c= %b" ,a_i,b_i,c_o[5] ); join

$sdf_annotate("basic_gates_and.sdf",basic_gates_test.and_dut,, ,"Maximum"); $sdf_annotate("basic_gates_or.sdf",basic_gates_test.or_dut,, ,"Maximum"); $sdf_annotate("basic_gates_nand.sdf",basic_gates_test.nand_dut,, ,"Maximum"); $sdf_annotate("basic_gates_nor.sdf",basic_gates_test.nor_dut,, ,"Maximum"); $sdf_annotate("basic_gates_xor.sdf",basic_gates_test.xor_dut,, ,"Maximum"); $sdf_annotate("basic_gates_xnor.sdf",basic_gates_test.xnor_dut,, ,"Maximum");

endmodule

//RS FLIP FLOP module rsflipflop (S,R,clock_i,q_o,qbar_o); input clock_i; input S; input R; output q_o; output qbar_o; wire q_o; wire qbar_o; dflipflop dff(.reset_i(1'b0),.clock_i(clock_i),.data_in_i(w3),.q_o(q_o),.qbar_o(qbar_o)); not n1 (w1 ,R ); and a1 (w2,w1,q_o); or o1 (w3,S,w2); endmodule

VK

Mentor Graphics

9

Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab

CEC-2011

//RS FLIP FLOP TESTBENCH module rsflipflop_test; reg clock_i; reg R; reg S; wire q_o; wire qbar_o; rsflipflop rsff(.R(R),.S(S),.clock_i(clock_i),.q_o(q_o),.qbar_o(qbar_o)); initial begin clock_i =1'b0 ; R =1'b0; end always #5 clock_i = !clock_i ; initial begin #20 R =1'b1 ; #20 S =1'b1 ; R =1'b0; #20 S =1'b0 ; R =1'b0; #30 S =1'b1 ; R =1'b1; #10 S =1'b0 ; R =1'b1; end initial begin end

$monitor($time ," \t clock_i =%b R= %b S =%b q=%b qbar =%b ",clock_i,R,S,q_o,qbar_o); #200 $finish;

endmodule //RS FLIP FLOP GATELEVEL TESTBENCH module rsflipflop_test; reg clock_i; reg R; reg S; wire q_o; wire qbar_o; rsflipflop rsff(.R(R),.S(S),.clock_i(clock_i),.q_o(q_o),.qbar_o(qbar_o)); initial begin clock_i =1'b0 ; R =1'b0; end VK

Mentor Graphics

10

Reference: RV-VLSI, Frontend Programs, Part-A, VTU, 7th Sem, E&C, VLSI Lab

CEC-2011

always #5 clock_i = !clock_i ; initial begin #20 R =1'b1 ; #20 S =1'b1 ; R =1'b0; #20 S =1'b0 ; R =1'b0; #80 S =1'b1 ; R =1'b1; end initial begin $monitor($time ," \t clock_i =%b R= %b S =%b q=%b qbar =%b ",clock_i,R,S,q_o,qbar_o); #200 $finish; end initial begin $sdf_annotate ("rsflipflop.sdf",rsflipflop_test.rsff); end endmodule //D FLIP FLOP module dflipflop (reset_i, clock_i, data_in_i, q_o, qbar_o); input clock_i; input reset_i; input data_in_i; output q_o; output qbar_o; reg q_o; wire qbar_o; always @(posedge clock_i) begin if(reset_i) q_o