7

CHAPTER 7 MEMORY AND I/O DECODING

    

In this chapter ,you will learn The pin functions of a typical memory chip The technique of memory address decoding The reason and logic of using partial address decoding The reason for organizing memory in banks The principles of I/O address decoding

Introduction In the previous chapter we took a peep into the hardware structure of 8086 and a few ICs which have to be used along with it. Now we will delve a bit deeper- the focus of this chapter will be on the way memory and I/O are connected to the processor. Let us start with memory . Whenever we talked about reading or writing from memory , an address was referred to . Assuming that memory is byte organized , it is thought that every location in memory which can store a byte of data ,has a unique address .The total address space of 8086 is from 00000 to FFFFFH . How is it that each location gets a unique address ? Another issue is that the total address space of 1 MB is not obtained as a single chip of RAM – also it is not entirely RAM . ROM is also part of memory and a number of RAM and ROM chips together constitute the total memory i.e. the total address space . Also, when the processor is used , its address space is partitioned such that certain address ranges are standardized for certain specific applications .Thus the IBM PC has a standard memory map –if it is not standardized ,incompatibility issues are likely to arise. This chapter attempts to find answers to all these doubts and queries. The assumption here is that memory space and I/O space are disjoint (Refer Chapter 5) –i.e. the scheme of I/O interfacing used is ‘peripheral or Isolated I/O’. This allows memory to use the full 1 MB of space for itself. 7.1 MEMORY DEVICE PINS The memory that we are talking about can be RAM or ROM –The difference is that ROM can only be read from, so the MEMWR signal from the processor does not have any relevance for ROM. A typical RAM has the pin lines as shown in Fig 7-1. As shown , it has data lines Do to DM-1 .If it is a byte organized memory ,the data lines are D0 to D7 . The number of address lines ( A0 to AN-1 ) depends on the number of locations it contains .For example if it is specified to be a 256 x 8 RAM ,it means that it has 8 data lines and a storage capacity of 256 locations –thus it needs 8 address lines as 256 =2 8 . Think of the following cases then - a 1 K x 8 RAM needs 10 address lines ,as 1K=1024 =2 10 , a 2K x 8 RAM

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has 11 address lines and so on. Thus, it is the capacity of the chip which decides the number of address lines. A0

D0 RAM

DM-1 AN-1

WE CS OE

MEMWR

MEMRD

SELECT

Fig 7.1 Typical RAM with control pins Coming to the other pins of the chips , the active low signals WE is to be connected to the MEMWR signal from the processor side .Only if this pin is activated ,can the write operation be done in the addressed location . WE enables the input tri-state buffers of the data lines of the RAM. For reading ,the pin MEMRD (from the processor side) is to be connected to the OE (output enable) pin of the memory chip for reading .When this pin is low, the output lines are activated ,otherwise they remain tri-stated. Thus OE is meant to enable the output tri state buffers of the RAM. Some RAM devices have only a single pin for reading or writing, which is R/ W .This is fine, as it is obvious that only one of the activities (read or write ) can occur at a time. The pin CS (chip select) or CE ( chip enable or S (Select)) is the pin which enables the memory chip .No activity is possible if this pin is inactivated , as the chip remains turned off . How does this pin get activated? It will be activated only if the address placed on the address bus of the processor is one of the addresses in the address range of this chip .When this condition is satisfied, a select pulse is obtained from the ‘address decoder’ output and the memory chip is turned ON for reading or writing. It is during a memory read or write cycle that the select pulse is obtained i.e. when reading or writing to the particular chip is required and the address is placed on the address bus . A ROM chip is similar except that it does not have the WE pin, as it can only be read from . The ROMs that are used are usually EPROM ,which have a pin to enable the chip to be programmed .( PGM ).

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Why active low control signals? You might have noticed that most of the control signals discussed here and in the previous chapters are active low. This is a TTL concept .The stray capacitances of the control pins can get charged from noise voltages ,and this may cause the signals to cross the threshold of ‘high’ level as defined for TTL –thus if the control signals are active high ,it may cause wrong triggering . On the other hand , an active low signal trigger will happen only when the line is pulled low deliberately by the controller. Example 7-1 How many address and data lines are needed for the memory chips with the following organization? i) 256 x4 ii) 512 x 8 iii) 1K x16 iv) 32K x 8 v) 128K x 8 Solution i) 256 x 4 means, it has 4 data lines , and 256 memory locations ,each of width 4 bits. 8 256 =2 .Thus 8 address lines are needed. ii) 512 x 8 This chip has 8 data lines . 512 =29 . Thus ,it has 9 address lines. iii) 1K x 16 . This chip has 16 data lines . 1K =1024 =210 .It has 10 address lines to access each of the 16 bit data words. iv) 32K x 8 It has 8 data lines. 32K = 25 x 210 =215 . It has 15 address lines ii) 128 K x 8 It has 8 data lines. 128 K = 27 x 210 =217 . It has 17 address lines .

7.2 MEMORY ADDRESS DECODING See Fig 7.2 in which a 2K x 8 memory chip is shown. This memory chip has 11 address lines ,which are directly connected to the 11 lower lines of the address bus of the processor .Now the remaining 9 lines of the address bus of the processor are connected to the inputs of a NAND gate whose output pin feeds the CS pin of the memory chip .Thus it is obvious that the chip is selected(enabled) only if all the input lines of the NAND gate are high –which means that A11 -A19 of the address has to be high for the memory chip to be selected and made active .The NAND gate thus functions as the address decoder for the memory It fixes up the address range of the chip.

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Address Bus of 8086

A0

A0 - A10

A10

MEMORY 2K x 8

A11 A19

CS

o

SELECT

Fig 7.2 Memory with address decoding

Example 7-2 i)Find out the range of addresses that the memory chip in Fig 7.2 contains ii) Repeat the same when the logic of the NAND gate is changed as in Fig 7.3 A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 A 11

o o o o o o

o

SELECT

o 0 0

A13 Fig 7.3 NAND gate decoder Solution

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The address lines from A10 to A0 can vary from 000 0000 0000 to 111 1111 1111. The address lines A19 to A11 must always be 1111 1111 1 for this chip to be selected. As such ,the lower and upper range of the addresses in the chip are seen as A 19

A 18

A 17

A 16

A 15

A 14

A 13

A 12

A 11

A 10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

0 1

0 1

0 1

0 1

0 1

0 1

0 1

0 1

0 1

0 1

0 1

The first address on the chip is 1111 1111

1000

0000

0000

1111

1111

1111

The last address on the chip is 1111

1111

Thus the address range of the chip is FF800H to FFFFFH .i.e.2048 bytes i.e. 2K bytes. If the logic on the NAND gate is modified as in fig 7.3 ,the address range will be 0000

0000

0000

0000

0000

0000

0000

0111

1111

1111

to

i.e. 00000 to 007FFH .ie, 0 to 2047 bytes ,which is 2K bytes. 7.2.1ADDRESS DECODING CONCEPTS  Thus the basic idea of address decoding is to decode the extra unused address lines of the processor to specify the address range.  When more chips are to be interfaced, decode the extra address lines to a different range for each group.  Any logic /logic gate can be used to perform address decoding .From the address decoder output ,the right logic value should be obtained to turn the chip on .Thus the ‘select’ pulse obtained from the address decoding logic can be high or low ,depending on the requirement of the chip select pin of the memory chip.  In general , address decoders can built using: – Random logic (simple gates) – Block decoders (e.g.. 24 , 38 … etc) – Programmable Logic (PLAs,CPLDs, FPGAs, … etc.) The first two types of address decoders will be discussed in detail here .The last type follows the same principle –only ,the devices used are ‘programmable ‘ or even ‘re-programmable’ .This brings in more flexibility to the design .The design of the address decoder is then done using

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advanced design techniques involving hardware description languages and CAD tools . This is beyond the scope of this book and hence is not covered here.

Example 7-3 Design an address decoder using OR logic for a 32K x 8 RAM .Find the address space of this memory chip. Solution: Since it is a 32K RAM , it has 15 address lines . Thus the lower 15 lines of the address bus of the processor is connected to the address lines of the RAM .The upper 5 lines A15 – A19 are used for address decoding . Here the lines are given as input to the OR gate . When the address on the address bus corresponds to A15 to A19 being all at logic 0 , the decoder gives the SELECT pulse to the CS pin of the memory chip and thus it is selected.

32K x 8

A0

D0 RAM

ADDRESS BUS A14

DATA BUS D15

CS

A19

SELECT

A15

Fig 7.4 Address decoding using OR logic The lowest address is thus 0000 0000 0000

0000

0000

and the highest address is 0000 0111 1111

1111

1111

The address range of this memory chip is 00000 to 07FFFH . Example 7-4 Find the address space of the following chips with the address decoding circuitry as shown in the figure7.5a and b . x86 Chapter7

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i) 8K x 8 EPROM ii) 8K x 8 RAM

+5V o A0

PGM

A0

EPROM 8Kx8

A12

D0

A12

A12 D7

CS

A19 A18

SELECT o

A16

A19 A18 A17 A16 A15 A14

A15 A14

A13

o

A0 RAM 8Kx8

D0

D7

OE

A17

A0

D0

A12

D7

OE WE CS

o o o

o

o

D0

D7

SELECT o o o

o

o

A13

Fig 7-5 a EPROM with address decoder Fig 7-5 b RAM with address decoder Solution: Both the memory chips are of 8K capacity .Hence they have 13 address lines .The remaining 7 lines of the processor system bus are used for address decoding. i) In Fig 7-5 a, for the EPROM chip to be selected ,the values of A19 to A13 are to be 1111 101 .Thus the lowest and highest addresses in the chip are 1111 and 1111

1010

0000

0000

0000

1011

1111

1111

1111

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i.e. FA000 H to FBFFFH. ii) In Fig 7-5 b, for the RAM chip to be selected , the values of A19 to A13 are 0001 111. Thus the lowest and highest addresses in the chip are 0001

1110

0000

0000

0000

and 0001

1111

1111

1111

1111

i.e. 1E000 to 1FFFFH . 7.2.2 ADDRESS DECODING USING BLOCK DECODERS A very popular decoder is the three to 8 decoder (74LS138) whose block diagram is shown in Fig 7.6a A Y0 o Select Y1 o B Inputs 7 Y2 o C 4 Y3 o L Y4 o S Y5 o 1 G2 A 3 Y6 o Enable 8 G2 B Y7 o Inputs G1 Fig 7.6a Functional block diagram of the 3 to 8 decoder 74LS138

Inputs Enable G1 X L H H H H H H H H

G2* H X L L L L L L L L

Outputs

Select C X X L L L L H H H H

B X X L L H H L L H H

A X X L H L H L H L H

Y0 H H L H H H H H H H

Y1 Y2 H H H H H H L H H L H H H H H H H H H H

Y3 Y4 H H H H H H H H H H L H H L H H H H H H

Y5 H H H H H H L H H

Y6 Y7 H H H H H H H H H H H H H H H H L H H L

H

Fig 7.6b Decoding Table of 74LS138 Note: G2* =G2 A and G2 B x86 Chapter7

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The output lines are active low and depending on the selection inputs , one output line alone will be active . To enable the decoder chip ,it must be ensured that G2 A and G2 B are at logic level 0 and G1 is at logic 1. The decoding table of the chip is shown in Fig 7.6b Consider that a 1K x 8 RAM chip uses a 3 to 8 decoder for memory decoding .The RAM has 10 address lines .Thus the remaining 10 lines of the processor address bus can be used for decoding . Let us calculate its address space . Consider a hardware connection as shown in Fig 7-7 A10 A11 A12 1

1

A

A13 A14

o

A15 A16

B

G2 A

o

G2 B

A17 A18 A19

G1

0 C

CS

7 Y3 o 4 L S 1 3 8

RAM 1K x 8

A0 -A9 Fig 7.7 Address decoding of a RAM using a block decoder In this ,the address linesA0 to A9 ,from the address bus of the processor are directly connected to the address lines of RAM .The logic on these lines can vary from 00 0000 0000 to 11 1111 1111 . The remaining 10 address lines of the processor are used for address decoding . Thus we see them connected to the pins of the decoder .To enable the decoder ) G2 A and G2 B must be 0,and G1 must be 1. Also ,to enable Y3 , CBA must be 011 . Thus the logic on the lines from A19 to A10 should be 1111 1111 10 . Thus the upper and lower range of the address is as shown in the table . A 19

A 18

A 17

A 16

A 15

A 14

A 13

A 12

A 11

A 10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

0 0

0 1

0 1

0 1

0 1

0 1

0 1

0 1

0 1

0 1

0 1

The address range is 1111 1111 1000 x86 Chapter7

0000

0000 Page 9

To 1111

1111

1011

1111

1111

i.e. FF800H to FFBFFH Subtracting FF800H from FFBFFH ,we get 3FFH which is 1023 which means that there are 1023 +1 addresses on this chip.. Thus there are 1024 (1K)byte locations in the chip. Example 7.5 The figure shows a RAM and a ROM connected to an address decoder ,which is a 3 to 8 decoder. Find the address space of each of these chips.

A16

A17

A18 A 0 – A15

A

B

C

CS

SELECT A19

ROM 64K x 8

G1

Y1 o

G2 A G2 B

Y4

o A 0 – A15

SELECT

RAM 64K x 8

CS

Fig 7.8 Address decoding of a RAM and ROM using a 3 to 8 decoder Solution: Only 4 lines of the address bus are to be used for address decoding, as the remaining 16 lines are to be connected to each of the 64K memory chips . For the ROM ,A19 to A16 are to be 1001 ( A19 =1,CBA=001). .Thus the address range of this chip is 90000H to 9FFFFH. Similarly for the RAM , A19 to A16 are to be 1100 (A`9 =1,CBA=100) . Thus the address range of this chip is x86 Chapter7

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C0000H to CFFFFH. 7.2.3 PARTIAL ADDRESS DECODING In the hardware connection between a memory and a processor ,the lower order address lines are connected directly to the memory address lines ,and the higher order lines are used for addressing .We find that in all our discussions so far the addresses generated are unique and create no ambiguity. This is also called exhaustive decoding. But sometimes, to reduce the hardware used , only some of the upper address lines are used for decoding and this is called partial address decoding. This may be made use of, if it is sure that the system will need much less memory than the full 1MB of the address space .

A0 -A13

16K x 8 RAM

16K x 8 ROM

CS

CS

A14

o

Fig 7.8 Partial address decoding

See Fig 7.8. Here two 16 KB memory chips are decoded using just the condition of the A 14 line .For the RAM ,A14 should be 0 and for ROM A14 should be 1 for the respective chips to be enabled .The address lines A15 to A19 are don’t cares ,which means that each of these chips can be accessed using a number of different addresses which will map to the same physical location. In effect ,this causes ‘foldback memory ‘ or ‘multiple-mapped memory’ to exist . Suppose we try to read from the lowest RAM location .We use the physical address 00000 .But the same data can be read using an address F8000H or E0000H .In fact 32 different addresses can be used to read this data .This is because 5 bits of the address i.e. A15 to A19 ,are don’t cares ,232 =32 . Thus this is the amount of foldback memory that exists.

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Does this cause any problem? Not really ,but if the memory of the system needs to be expanded ,the hardware will have to be modified .As a rule ,partial address decoding is perfectly safe for a small system which does not need any memory expansion.

Example 7.6 Draw a decoding circuit using partial decoding for a RAM and EPROM each of size 8K x 8 .For decoding use only the address lines A13 and A14 . What is the size of its foldback memory?

A0 -A12

A14 A13

8K x 8 RAM

8K x 8 EPROM

CS

CS

o o

o

Fig 7.9 Partial address decoding using two address lines Solution: For the RAM ,it is mandatory to have only the address lines A13 and A14 to be 00. The addresses can vary as shown below. S ince 5 address lines are don’t cares ,there are 32 different addresses with which each location can be accessed. A 19

A 18

A 17

A 16

A 15

A 14

A 13

A 12

A 11

A 10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

X X

X X

X X

X X

X X

0 0

0 0

0 1

0 1

0 1

0 1

0 1

0 1

0 1

0 1

0 1

0 1

0 1

0 1

0 1

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For the EPROM ,it is only mandatory to have the address lines A13 and A14 to be 11. The addresses can vary as shown below. Since 5 address lines are don’t cares ,there are 32 different addresses with which each location can be accessed. A 19

A 18

A 17

A 16

A 15

A 14

A 13

A 12

A 11

A 10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

X X

X X

X X

X X

X X

1 1

1 1

0 1

0 1

0 1

0 1

0 1

0 1

0 1

0 1

0 1

0 1

0 1

0 1

0 1

7.3 MEMORY BANKS 8086 has a 16 bit memory bus –which means that data transfer can occur at a maximum rate of 16 bits (one word ) per bus cycle. But sometimes only a byte needs to be accessed. This means that the processor must have both options –both byte and word transfer must be possible.

MEMORY-2

MEMORY-1

Address Bus Address Bus

D0 –D7 D0 –D15

D8 –D15

Data Bus

Fig 7.10: 16 bit me mory realized using two 8 bit memory chips We know that for a word transfer , two byte locations must be accessed –i.e. two addresses are actually needed Keeping these concepts in mind, let us see how memory is organized for 8086 .A 16 bit data can be obtained by accessing two memory chips in parallel each having 8 bits each of the word. See Fig 7.10 . This is the way memory is organized in 8086 .A 16 bit word is obtained as the concatenation of two bytes in two ‘memory banks’. i..e. memory is organized as two banks –one, the upper bank or high bank with the data corresponding to the upper byte D8 -D15 , and the other x86 Chapter7

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,the lower bank or low bank which has the data lines D0 -D7 . The upper bank is also called the odd memory bank,because it has the odd addresses mapped to it –in the same way ,the lower bank is called the even bank .Let’s how this works out .

Low bank (Selected by A0 )

High bank (selected by BHE ) FFFFF FFFFD

FFFFE FFFFC

8 Bits Odd Address 00003 00001

D15 –D8

8 Bits Even Address

D7 –D0

00002 00000

Fig 7.11 Memory banks of 8086 See Fig 7.11 .Remember that a 16 bit word has one byte with an odd address and one byte wit h an even address .If a byte alone is to be accessed ,it may be in the odd bank or even bank .Thus for reading /writing a byte ,only one of the banks is to be accessed ,but to access a word ,both me mory banks have to be accessed .In the second case, the byte in the given logical address and the byte in the next address are accessed .For instance ,if the instruction is MOV AX ,[0002] the logical addresses involved are 0002 and 0003 –one byte in the even bank ,and one byte in the odd bank . For an instruction MOV AX,[0001] the addresses are 0001 and 0002 – again ,both banks have to be accessed to get the complete word. How are the two banks differentiated.? An even address implies that the LSB of its address i.e. A0 is low . Thus , A0 can be used to enable the even bank .To enable the high (odd) bank ,8086 generates a signal BHE (Bus High Enable)which goes low whenever the addressed data is in the high (odd) bank. In Fig 7.12, see how these two signals are used along with the address decoder output ,to enable the two banks independently . BHE is enabled if and only if the address on the address bus is for accessing a byte in the high bank. That is why it is designated ‘BUS HIGH ‘ enable. A0 is frequently called ( BLE} (Bus Low Enable)because it used to enable the low bank. . Fig No 7.12 ,shows a case when two 32 K x 8 RAMs form the16 bit memory. . Thus the total memory is 64K x 8 bytes. A 32 K RAM needs 15 address lines . Of the 20 address bits from the address bus of the processor , A0 is used to enable the even bank.. A1 to A15 are connected to the address pins A0 to A14 of each RAM chip. The rest of the address lines are used for address decoding . A0 and BHE are used for selecting each of the banks separately

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A0 BHE

A16 -A19 Address Decoder

Address Bus

CS

CS

RAM 32K x 8

RAM 32K x 8

LOW (EVEN) BANK

HIGH (ODD) BANK

A1 -A15

D8 –15

D0 –D7

D0 –D15

Data Bus

Fig 7.12 Memory banks with the respective bank enable signals ,along with the decode r Address

Typical instruction

Data type

BHE A0

Bank accessed

(even) (odd) (even) (odd)

MOV AL, [0000] MOV AL,[0001] MOV AX,[0000] MOV AX,[0001]

byte byte word odd byte even byte

1 0 0 0 1

Low High Both High Low

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0 1 0 1 0

No machine cycles 1 1 1 I cycle II cycle

of

Page 15

Table 7.2 Status of control signals for me mory bank access Now see Table 7.2 and note how and when BHE goes low. What emerges from the table is that , for byte access , BHE goes high if the referred byte is in the high (odd) bank .When a word whose logical address is even, both A0 and BHE are low simultaneously .Hence for the reading or writing of such a word, only one machine cycle is needed. 7.3.1 ODD ADDRESSES WORD For accessing a word whose address is odd ,two machine cycles are expended. See the example instruction MOV AX,[0001] in Table 7.2 .This means that the effective addresses to be accessed are 0001 and 0002 .When the address 0001 ( i.e. physical address corresponding to this) is placed on the address bus ,A0 is not low .So only the upper bank address is accessed in this machine cycle .Only one byte is read in this machine cycle. To get the next byte from the even bank ,one more machine cycle must be used This is why it was mentioned (Section 6.6) that for accessing a word operand from an odd location ,an extra machine cycle machine time has to be added to the instruction cycle time. Thus it is advantageous (in terms of speed) to align all words at even addresses. Many optimized assemblers do this automatically .Otherwise, there is a directive named EVEN which does this. Take the case when the data segment has 7 bytes and a word .The bytes are stored in location 0000 to 0006 .Obviously ,the word will be aligned at the next address, which is odd. If the EVEN directive is used ,the location counter is incremented by 1 ,and the word is stored at location 0008 .This is illustrated in the following data segment definition. .DATA NUMS DB 7 DUP(05) EVEN WDR DW 2345H

;increments location counter to

0008

But this obviously wastes one byte space, and memory is fragmented But this situation cannot be avoided if speed is to be optimized. 7.3.2 WHY MEMORY BANKS ? Thus we see that arranging memory to be in two memory banks causes an additional burden. Then why is the memory system designed this way ? What is being attempted is that ,when a byte alone is to be accessed ,only the bank in which that byte resides , should be enabled –the other bank should remain disabled . What is the problem if both the banks are enabled for any and every access? The answer is that there won’t be any problem in case of a read operation , but it may cause havoc for a write operation .See the following cases. MOV AL,[0000] Note the above instruction which initiates a read cycle. .It is the case of reading a byte .Only the even (low) bank need be enabled to read .But even if the high bank is also enabled ,it doesn’t matter .The data present on the lines D8 to D15 will not be used by the processor .It takes into AL , only the data on lines D0 to D7 and ignores the data on the upper bus. But the writing process creates a problem. Observe the case of the following write instruction . x86 Chapter7

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MOV [0000],AL This should cause only the even bank to be enabled . If the odd (upper) bank also gets enabled ,the logic levels on the data lines D8 –D15 will get written onto the enabled location in the upper bank , which is not admissible. Thus when a ‘byte ‘ alone is to be written into me mory ,it is important to ensure that only one of the memory banks is enabled .

7.3.3 USING SEPARATE WRITE STROBES Another approach is used to enable memory banks ,and it is by generating separate write strobes. Now that the problem has been identified to be associated with ‘writing ‘ ,there is another way to solve it, and it is by generating separate write strobes.

BHE MEMWR A 0 ( BLE}

HWR LWR

Fig 7.13 Using separate write strobes We can use the logic shown in Fig7.13 . When there is the necessity to write a byte to the high order (upper)bank , only the HWR (High write ) signal will be enabled –similarly for writing a byte to the lower bank ,only that bank will be enabled ,but for writing a word , both banks get enabled . Only the write control signal is taken into consideration- reading unwanted data is not a problem as the processor takes from the data bus ,only the byte that it needs. In this scheme, the LWR and HWR signals are applied to the WE pins of the respective memory banks only . Separate bank select signals from the address decoding circuitry is not used. . 7.3.4 MEMORY MAP OF IBM –PC Table 7.1 shows the memory map of IBM PC –i.e. the first version of the PC manufactured by IBM with the 8088 processor ,which has a total memory address space of 1 MB . Address range 00000 to 9FFFFH

Size 640K

Type RAM

Allocation User RAM –with some areas with special allocations like , 1 K (00000 to 003FFH)for interrupt vector table, and some portions for storing BIOS and DOS parameters ,operating system etc

A0000H to BFFFFH

128K

VDR

Video display RAM with portions allocated for video buffers and other video applications

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C0000H to EFFFFH F0000H to FFFFFH

192K

ROM

Memory expansion area for ROM

64K

ROM

BIOS ROM , hard disk and other peripherals’ ROM

Table 7.3 IBM PC memory map For a 4GB (FFFFFFFFH) memory of the current x86 PC, the same memory mapping followed, with RAM at the lower end and ROM area at the upper end.

is

7.4 I/O ADDRESS DECODING It was mentioned in Chapter 5 that there are two schemes for I/O port interfacing .The simpler scheme is ‘memory mapped I/O ‘ ,but this causes I/O to encroach on the memory address space . Hence most systems prefer the other scheme which is designated as ‘Isolated I/O’ ,Peripheral I/O or I/O mapped I/O . We will confine our discussion to this scheme alone. Even though our processor has 20 bits for address ,I/O uses only 16 bits .Thus I/O port addresses can range from 0000 to FFFFH –i.e. the total I/O space is only 64K .i.e. we can use 65,536 different I/O addresses .But since the instructions for input (IN) and output (OUT) are separate , we can have 64 K input ports and 64K output ports .This is actually quite a lot, practically .

Input Ports

8 0 8 6

Data in Data out

Data bus

Output Ports

Fig 7.14 Input and output ports connected to the 8086 Now recollect that ports with 8 bit port addresses use ‘fixed port addressing’ ,while port addresses beyond that have to use the ‘variable port addressing scheme’. Another point to keep in mind that any port can have a 8 bit or 16 bit data bus .

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FFFFH

Variable port addressing

FFH Fixed port addressing 00

0000

Fig 7.15 Sche mes of port addressing 7.4.1 OUTPUT PORTS Output ports use the instruction ‘OUT’ for writing into it .Then the data in the accumulator (AL or AX) gets written into the output device. An output device may be as complex as a video display or as simple as LEDs which have to lighted up . Data from the processor is sent to an output port during the I/O write cycle .This data will be available on the data bus only until the end of a machine cycle. For the output port to be able to use this data, it must be latched .Thus a latch is mandatory for an output port set up.(For memory ,there are latches inside the chip).Fig 7.16 shows a basic output port . Requirements of an output port i) To identify /select the specific device , an address decoder should give a select pulse . ii) To read from the output device ,the IOWR signal must be active. iii) When both the above two conditions are true, the data on the data bus is latched to the output port. iv) All the above activities occur during an I/O write cycle. Output Device

Address Decoder

Address Bus

Select o

CLK

LATCH

Data Bus

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System Data Bus

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Fig 7.16 Basic output port setup Example 7.5 Design a system with 8LEDs connected to the lower 8 bits of the data b us of the 8086 data bus. The LEDs must switch ON and OFF with a delay of 1 second between each switching action. Solution: Fig 7-17 shows the hardware setup .

R

D0 Data Bus of 8086

D7

D0 D7

G

A0 A1 A2 A3 A4 A5 A6 A7

o o o

7 4 L S 3 7 3

OC

Q0

8 LEDs

R Q7

Select

o

IOW

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Fig 7-17 Output port with 8 LEDs interfaced to it

i)

ii) iii) iv) STRT:

v)

The diagram with the address decoder ,the select pulse and the IOW signal is shown .The address decoder gives a high select pulse . This is ANDed with the inverted IOW pulse, and applied to the G pin of the octal transparent latch 74LS373 (Refer Section 6.1.4).The G pin needs a high level pulse to latch the data on its D inputs to its Q outputs . OC must be strapped to ground to enable the output pins of the latch. Current limiting resistors are connected to the cathodes of the LEDs The address decoder specifies an 8 bit address of F8H for the port. The program for switching the LEDs ON and OFF is MOV AL,0FFH ;data to light up all the LEDs OUT 0F8H,AL ; transfer it to the output port CALL DELAY_1SEC ;call the delay procedure MOV AL,00 ;data to switch off the LEDs OUT 0F8H,AL ;transfer it to the output port CALL DELAY_1SEC ;transfer it to the output port JMP STRT ;repeat continuously For the delay procedure refer Example 6.3..

7.4.2 INPUT PORTS Input ports use the IN instruction to give data to the processor which is received in the accumulator of the processor (AL or AX) . An input port requires a tri-state buffer along with it to ensure that is isolated from the bus when it is not selected. A simple switch ca n be an input port , and the alphanumeric keyboard used in PCs is also an input port. Fig 7.18 shows a basic input port . System Data Bus

SELECT Address Bus

E

Address Decoder

IOR

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Fig 7.18 Basic input port Requirements of an input port i) To identify /select the specific device , an address decoder should give a select pulse . ii)

To read from the input device ,the IORD signal must be active

iii)

When the above two conditions are true, the corresponding tri- state buffer gets enabled and data is transferred to the processor. Taking into consideration all these requirements ,let us design a system with two sets of switches acting as two input ports. The tri-state buffer 74LS244 is used. This has two active low enable inputs 1OE and 2OE .When both of them are low ,data at the A inputs appear at the at the Y outputs. But if the enable pins are high ,the output is tri-stated.

1OE 1A0

1

20

VCC

2

19

2Y0

3

18

2OE 1Y0

1A1

4

17

2A0

2Y1

5

16

1Y1

1A2

6

15

2A1

2Y2

7

14

1Y2

1A3

8

13

2A2

2Y3

9

12

1Y3

GND

10

11

2A3

74LS244

Fig 7.19 Functional pin diagram of the octal tri-state buffe r 74LS244 Example 7.6 Find the addresses of the two input devices shown in the figure and write a program to read data from each of these ports and move it to some other registers. Solution: i) Two sets of 8 switches S0 to S7 are connected to the data bus through two tri-statebuse and this setup functions as two input ports . ii) The address of the ports are 8 bit ,as only address lines A0 to A7 have been considered for decoding ,The address of the first port is 7EH and that of the second is 3EH. iii) The address on the address bus decides which of the input ports get selected . x86 Chapter7

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The tri-state buffer ensures that the port which is not selected is isolated from the bus. iv) The program for inputting data from each of these ports is STRT:

IN AL ,3EH MOV BL, AL IN AL, 7EH MOV DL ,AL

;take in data from Port2 ;move data to BL ; take in data from Port1 ;move data to DL

Thus after reading both ports , the switch settings are available This data can be used for processing and/or display

in BL and

CL.

TSB-1 S0

7 4 L S 2 4 4

S7 o

Port-1

1OE

Y0 Y7

D0 -D7 to8086

2OE

SELECT o

IOR o TSB-2 S0

7 4 L S 2 4 4

S7 Port-2 A0 A1 A2 A3 A4 A5 A6 A7

1OE

o

Y0 Y7

2OE

SELECT o o o

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Fig 7.20 Two sets of switches acting as two 8 bit input ports 7.4.3 DECODING 16 BIT I/O ADDRESSES We have used 8 bit addresses so far for I/O devices . But personal computers use 16 bit addresses .as well .In that case ,only the decoding circuitry changes .Address lines A0 to A15 should be used by the address decoder to generate the device select pulse. The other point to remember is use ‘variable port addressing ‘ when writing I/O instructions for ports with 16 bit addresses. 7. 4. 4 PORTS WITH 16 BIT DATA BUS So far we have discussed only I/O ports with 8 bit data bus. But 16 bit data bus is also possible for I/O ports .What becomes different then ? The answer is that ,the situation is similar to the case of memory banks .Recollect the concept of memory banks .If each of the 16 bit ports need to be accessed as two 8 bit ports as well, we have to have 8 bit I/O banks . So we can have I/O banks too ,with 8 bits in the upper bank and 8 bits in the lower bank .To read a word ,both banks can be enabled ,by using both A0 and BHE bits . Fig 7.21 shows the upper and lower I/O banks .Note that here the addresses can have only a maximum size of 16 bits, while for memory ,the addresses are 20 bits.

ODD BANK ENABLED BY BHE

EVEN BANK ENABLED BY A0

HIGH I/O BANK

LOW I/O BANK

0005 0003

0004

0001

0002

D15

D8

D7

D0

Fig 7-21 I/O memory banks Most of the I/O ports used for PCs have 8 bits wide data , but there are 16 bit wide ports like video and analog to digital conversion ports etc . If a port is .by definition , a 16 bit wide port ,use of separate bank select signals are not needed-the port can be selected directly by the address decoding and the I/O read/write signals. That is because data is always read or written as a word, and byte access is not necessary.

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Key points of this chapter 1. Memory mapped I/O causes I/O space to encroach on the memory address space of the processor. 2. Active low control signals prevent accidental triggering by noise voltages or open connections. 3. 74LS138 is a very popular 3 to 8 decoder. 4. The number of locations in a memory chip is 2 N where N is the number of address lines of the chip. 5. Memory is always organized as ‘banks’. 6. The BHE signal goes low when the addressed byte is in the upper bank of memory. 7. The LSB of the address bus i.e..A0 is used to enable the low bank of memory. 8. Memory chips have tri-state buffers and latches inside the chip. 9. All input ports need a tri-state buffer to connect it to the system bus. 10. All output ports need a latch to keep the outputted data ,until it is changed by the next OUT instruction. 11. An I/O address can be 16 bits in size ,in which case ‘variable port addressing ‘ is necessary for writing I/O instructions. QUIZ 1. How many address lines does a 256K memory chip need? 2. Name the important pins in a typical RAM and explain the function of each. 3. Find the numbers of two standard ROM chips and two EPROM chips , along with the way the chips are organized(how many address and data lines). 4. Why are active low signals preferred for use as control signals? 5. What is meant by the term ‘address decoding’ with respect to memory as well as I/O devices? 6. Why is memory organized in ‘banks’? 7. Why is the address line A0 also designated as BLE ? 8. Why are separate write strobes used for memory banks ,but not read strobes? 9. Whenever LEDs are connected to the data output lines ,it is preceded by latches .Why? 10. What is the range of address space for I/O in an 8086 based system? EXERCISE 1. Design an address decoder for two RAM chips and two ROM chips each organized as 1K x 8 chips. Use gates for the decoding circuitry and specify the address range of each chip. 2. Repeat the above problem using the chip 74LS159 (2 to 4 decoder) as address decoders. 3. Using a 3 x 8 decoder , design the decoding setup for eight RAM chips each of size 8Kx 8 .Indicate the address space of each chip. 4. For the following (Fig 7.22a and b)decoding circuitry , find the address range of the memory addresses .

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O

A19 A18 A17 A16 A15 A14 A13

O SELECT

Fig 7-22 a A19 A18

O O

A17 A16

O

O SELECT

A15 A14

O

O

Fig 7-22 b

5.

.Design a memory system using partial address decoding for 4 RAM chips of size 1K x 8 each . 6. Draw a diagram using memory banks for a 16 K x 16 memory . Draw the decoding circuitry ,and use write strobes for enabling the WE pins of the banks . 7. Design a I/O system in which there are two switches connected as an input port . The status of these switches are to be read and fed to corresponding LEDs connected at the output side. Draw the hardware diagram for this and write a program to do this . The address of the ports should be designed . 8. .Design an I/O system in which an input counter counts from 0 to 9 ,then goes back to 0 and then repeats .this sequence.. This count has to be displayed on a seven segment LED. Design the setup with input and output ports.

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