7. Memory Interfacing With Example.pptx

7. Memory Interfacing with Example

19 Aug. 2013

Module 1

Memory interfacing

 Basics of 8085:  Types of memory and memory interfacing.  Decoding techniques – Absolute and Partial

Memory structure and it’s requirements. Basic concepts in memory interfacing. Address decoding and memory address.

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Memory structure and it’s requirements (RAM)

Memory structure and it’s requirements (ROM)

Input data Input buffer

CS

A10 I N T E R N A L

A0

WR

D E C O D E R

R/W Memory N M 2048 8

A11 I N T E R N A L

N = number of register M = word length A0

EPROM 4096 8

D E C O D E R

Output buffer

Output buffer

Logic Diagram for RAM

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CS RD

RD

Output data

N = number of register M = word length

Output data Logic Diagram for EPROM

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7. Memory Interfacing with Example

19 Aug. 2013

Example: If a memory is having 13 address lines and 8 data lines, then the number of registers / memory locations = 2^13 = 8129 word length = 8 bit Note: The number of address lines of a microprocessor depends on the Size of the memory. No. of lines

1 2 3 4 5 6 7

Memory size in bytes

2 4 8 16 32 64 128

8 9 10 11 12 13 14 15 16

256 Bytes 512 Bytes 1024=1k 2048=2k 4096=4k 8129=8k 16384=16k 32768=32k 65536=64k

Basic concepts in memory interfacing (Rules) 4) It is not always necessary to select 1 EPROM and 1 RAM. We can have multiple EPROMs and multiple RAMs as per the requirement of application. 5) We can place EPROM / RAM anywhere in full 64 Kbytes address space. But program memory (EPROM) should be located from address 0000H since reset address of 8085 microprocessor is 0000H. 6) It is not always necessary to locate EPROM and RAM in consecutive memory addresses.

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Basic concepts in memory interfacing (Rules) 1) 8085 can access 64 KB of memory, since address bus is 16-bit. But it is not always necessary to use full 64Kbytes address space. The total memory size depends upon the application. 2) Generally EPROM is used as a program memory and RAM is used as data memory. when both are used then total 64 KB address will be shared by both. 3) The capacity of program memory and data memory depends on the application.

Q.1) Design a microprocessor system for 8085 such that it should contain 8k byte of EPROM and 8k byte of RAM using 1) Absolute / Full Decoding 2) Partial / Linear Decoding. Solution: MEMORY ICs

A15 A14 A13 A12 A11 A10 A9 A8

Starting address Of EPROM

0 0 0 0 0 0 0

End address Of EPROM

0 0 0 1 1 1

Starting address Of RAM End address Of RAM

A7 A6 A5 A4

0 0 0 0

1 1 1

A3 A2

0 0

1 1 1

A1 A0 Address

0 0 0

1 1

1 1

0000H 1FFFH

0 0 1 0 0 0 0 0 0 0 0 0 0 0 0

0

2000H

0 0 1 1 1 1 1

1

3FFFH

1 1 1 1

1 1 1 1

2

7. Memory Interfacing with Example

19 Aug. 2013

1 uF

D0-D7 X1

A0-A7

VCC 6 MHz X2

8085

WR

LE

A0 – A7

1 uF + 5V + 5V READY

A8-A15

ALE

AD0 AD7

75 K RESETIN

7 4 3 7 3

RD IO/M

G A 7 Y5

IOR

4 B L Y6 S 1 Y1 C 3 Y2 8

IOW MEMR MEMW

G1 G2

D7- D0 A12 A11 A10 A9 A8 A7-A0 OE VCC

SW

1 uF

D0 – D7 TRAP RST 7.5 RST 6.5 RST 5.5 INTR

A8 – A15

RESETOUT

INTA

A13

D7- D0 A12 A11 A10 A9 A8 A7-A0 OE WR

EPROM (8K) 2764 G

RAM (8K) 6264 CS

CS

A 7 4 A14 L Y0 B S 1 A15 C 3 Y1 8 G1 G2

Absolute Decoding Technique / Full Decoding

D0-D7 A0-A7 VCC

WR RD IO/M

A8-A15

G A 7 Y5

4 B L Y6 S Y1 1 C 3 Y2 8

IOR

Solution:

IOW

Memory Ics

A15

A14

A13

A12

A11

A10

A9

A8

A7

MEMR

s.a of EPROM1

0

0

0

0

0

0

0

0

0

e.a of EPROM1

0

0

0

1

1

1

1

1

s.a of EPROM2

0

0

1

0

0

0

0

0

e.a of EPROM2

0

0

1

1

1

1

1

s.a of RAM1

0

1

0

X

X

0

0

e.a of RAM1

MEMW

G1 G2

D7- D0 A12 A11 A10 A9 A8 A7-A0 OE

EPROM (8K) 2764 CS

Q.2) Design a microprocessor system for 8085 such that it should contain 16k byte of EPROM and 4k byte of RAM using 8 Kbyte EPROMs and 2k byte RAMs.

D7- D0 A12 A11 A10 A9 A8 A7-A0 OE WR

A6

A5

A4

A3

A2

A1

A0

ADDRESS

0

0

0

0

0

0

0

0000H

1

1

1

1

1

1

1

1

1FFFH

0

0

0

0

0

0

0

0

2000H

1

1

1

1

1

1

1

1

1

3FFFH

0

0

0

0

0

0

0

0

0

4000H

1

1

1

1

1

1

1

1

1

47FFH

RAM (8K) 6264 CS

A13

0

1

0

X

X

1

1

s.a of RAM2

0

1

1

X

X

0

0

0

0

0

0

0

0

0

0

0

6000H

s.a of RAM2

0

1

1

X

X

1

1

1

1

1

1

1

1

1

1

1

67FFH

Linear Decoding Technique / Partial Decoding

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3

7. Memory Interfacing with Example

19 Aug. 2013

D0-D7 VCC

A0-A7

G

A8-A15

WR

A 7 Y5 4 RD L Y6 B S 1 Y1 IO/M 3 C 8 Y2

IOR IOW MEMR

A13

7 Y0 4 L Y1 S 1 Y2 3 8 Y3

A

B

A15

D7- D0 A12 A11 A10 A9 A8 A7-A0 OE D7- D0 A12 A11 A10 A9 A8 A7-A0 OE

EPROM (8K) 2764 CS

EPROM (8K) 2764 CS

D7- D0 A10

A9

A8

A7-A0 OE WR

RAM (2K) 6116 CS

D7- D0 A10 A9

C

G1 G2

A8

A7-A0

OE WR

CS

A11 A12

A11 A12

D0-D7

VCC

A0-A7 A8-A15

G

WR

A 7 Y5 4 RD L Y6 B S 1 Y1 IO/M 3 C 8 Y2

IOR IOW MEMR MEMW

G1 G2

VCC

A13

Memory Ics

A15

A14

A13

A12

A11

A10

A9

A8

A7

s.a of EPROM1

0

0

0

0

0

0

0

0

0

e.a of EPROM1

0

0

0

0

0

0

1

1

s.a of EPROM2

0

0

0

0

0

0

0

0

e.a of EPROM2

0

0

0

0

0

0

1

s.a of EPROM3

0

0

1

0

0

0

e.a of EPROM3

0

0

1

0

0

0

s.a of EPROM4

0

0

1

0

0

0

e.a of EPROM4

0

0

1

0

0

0

A6

A5

A4

A3

A2

A1

A0

ADDRESS

0

0

0

0

0

0

0

0000H

1

1

1

1

1

1

1

1

03FFH

0

0

0

0

0

0

0

0

0000H

1

1

1

1

1

1

1

1

1

03FFH

0

0

0

0

0

0

0

0

0

0

2000H

1

1

1

1

1

1

1

1

1

1

23FFH

0

0

0

0

0

0

0

0

0

0

2000H

1

1

1

1

1

1

1

1

1

1

23FFH

RAM (2K) 6116

G

A14

Solution:

MEMW

G1 G2

VCC

Q.3) Interface 2kb EPROM to 8085 using EPROM (1k X 4) chips, 74LS138 decoder and full address decoding and give the address map.

D7- D4 A9

A8 A7-A0 OE WR D3- D0 A9

EPROM (1K) CS

A8 A7-A0 OE WR

EPROM (1K) CS

Q.4) Design an 8085 based system for the following specifications: (a) CPU working at 3 MHz. (b) 8kB EPROM using 4kB devices. (c) 4kB RAM using 2kB devices. (d) One 8259 PIC in I/O mapped I/O. (e) One 8255 in I/O mapped I/O. Draw the complete interfacing diagram with latches, chip select logic, Reset circuit.

D7- D4 A9 A8 A7-A0 OE WR D3- D0 A9 A8 A7-A0 OE WR

EPROM (1K) CS

EPROM (1K) CS

G

A 7 Y0 4 A14 L B S 1 A15 3 Y1 C 8 G1 G2

A12

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A11 A10

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7. Memory Interfacing with Example

19 Aug. 2013

I/O Map

Solution:

A7 A15

A6 A14

A5 A13

A4 A12

A3 A11

A2 A10

A1 A9

A0 A8

ADDRESS

Port A

0

1

0

0

0

0

0

0

40H

Port B

0

1

0

0

0

0

0

1

41H

Port C

0

1

0

0

0

0

1

0

42H

CWR

0

1

0

0

0

0

1

1

43H

8259 Chip

0

1

0

1

0

0

0

0/1

50/51H

Ports and Registers

Memory Map: A15

Memory Ics S.A. of EPROM1

0

A14

0

A13

0

A12

A11

0

0

A10

0

A9

0

A8

0

A7

0

A6

0

A5

0

A4

0

A3

0

A2

0

A1

0

A0

0

ADDRESS

0000H

E.A. of EPROM1

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

0FFFH

S.A. of EPROM2

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

1000H

E.A. of EPROM2

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1FFFH

S.A. of RAM1

0

0

1

0

X

0

0

0

0

0

0

0

0

0

0

0

2000H

E.A. of RAM1

0

0

1

0

X

1

1

1

1

1

1

1

1

1

1

1

27FFH

S.A. of RAM1

0

0

1

1

X

0

0

0

0

0

0

0

0

0

0

0

3000H

E.A. of RAM1

0

0

1

1

X

1

1

1

1

1

1

1

1

1

1

1

37FFH

1 uF

D0-D7 A0-A7

VCC X1

G

WR 6 MHz X2 1 uF

8085

ALE LE

A0 – A7 + 5V

+ 5V READY

AD0 AD7

75 K RESETIN SW

1 uF

7 4 3 7 3

VCC

D0 – D7

INTR RESETOUT

IOR IOW MEMR MEMW

G1 G2

TRAP RST 7.5 RST 6.5 RST 5.5

INTA

A8-A15

A 7 Y5 4 RD L Y6 B S 1 Y1 IO/M 3 C 8 Y2

A8 – A15

A12

D7- D0 A11 A10 A9

A8 A7-A0 OE D7- D0 A11 A10 A9

EPROM 1(4K) CS

A8 A7-A0 OE

EPROM2 (4K) CS

D7- D0 A10

A9

A8

A7-A0 OE WR

RAM1 (2K) CS

D7- D0 A10 A9

A8

A7-A0

OE WR

RAM2 (2K) CS

G

A 7 Y0 4 A13 L Y1 B S 1 Y2 A14 3 C 8 Y3

A11 A11

G1 G2

A15

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7. Memory Interfacing with Example

19 Aug. 2013

D0-D7

VCC

A0-A7 A8-A15

G

WR

University Questions (ELECTRONICS)  May-2012

A 7 Y5 4 L Y6 B S 1 Y1 IO/M 3 C 8 Y2

IOR

RD

1) Design a system based on 8085 with following configuration (i) 8K x 8 EPROM using 4K x 8 chips (10 Marks) (ii) 8K x 8 RAM using 4K x 8 chips Draw memory map and interface diagram.

IOW MEMR MEMW

G1 G2

+ 5V

 Dec-2012 VCC

A12

Vcc A0,A1

G

A 7 Y4 4 A13 L B S 1 A14 3 C 8 Y5

D0-D7

PA

OE

8 WR 2 5 5 RESET OUT

G1 G2

A15

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A0 D0-D7

CS

PC

IR0

OE

8 WR 2 5 9

PB

Reset

SP/EN

INTR

INT

INTA

INTA CS

IR7 CAS0 CAS1 CAS2

2) Design 8085 based system with following specifications : (i) CPU operating at 3 MHz. (12 Marks) (ii) 16 KB program memory using 4 KB devices. (iii) 4 KB data memory using 2 KB devices. (iv) One 8 bit input port and one 8 bit output port performing interrupt driven I/O and interfaced in I/O mapped I/O mode. Use exhaustive decoding approach. Give detailed I/O map and memory map and neat interfacing diagram.

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