08.508 DSP Lab Manual Part-A

 

08.508

Digital Signal Processing Lab

Department of Electronics & Communication, VKCET

08.508 Digital Signal Processing Lab Manual PART-A

Department of ECE, VKCET

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08.508

Digital Signal Processing Lab

“Some people make things things happen, some watch things happen, while others wonder what happened” 

Department of ECE, VKCET

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08.508

Digital Signal Processing Lab Syllabus

Credits: 4 PART A: Experiments on Digital Signal Processors.

1. 2. 3. 4. 5. 6.

Sine wave generation. Real Time FIR Filter Filter implementation (Low-pass, High-pass High-pass and Band-pass) Real Time IIR Filter Filter Implementation (Low-pass, High-pass and Band-pass) Pseudo Random Sequence Generator. Real time DFT of sine wave. Sampling a given Analog signal and study study of aliasing. aliasing.

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Digital Signal Processing Lab

Prerequisite knowledge and/or skills:

• • •

Wri Write te comput computer er progra programs ms in an objec object-o t-orie riente nted d languag languagee such as C or C++. C++. Und Under erst stand and basic basic line linear ar-sy -syst stem em conce concept pts: s: li linea nearr ti time me-s -shi hift ft in inva vari rian ance ce,, sy syst stem em functions, Laplace transforms, z-transforms. Represent Repres ent digital digital filters filters as difference difference equations, signal flow graphs, z-transfor z-transform m

• •

system function, poles and zeroes. Unders Understand tand Fourier Fourier transf transform orm properties properties in continu continuous ous and discrete discrete domains. domains. Unde Underst rstand and digit digital al filt filter er (IIR (IIR and and FIR) FIR) design designing ing conce concepts pts..

Objectives:

• • • • •

To defi define ne and and use use Dis Discre crete te Four Fourier ier Transf Transform ormss (DFTs (DFTs)) To design design and and understa understand nd simple simple finit finitee impuls impulsee respons responsee (FIR) (FIR) filte filters rs To design design and and understa understand nd simple simple infin infinite ite im impul pulse se respons responsee (IIR) (IIR) filter filterss To train train the the studen students ts to to design design and impl impleme ement nt pract practica icall DSP sys system temss To progr program am a DSP DSP chip chip TMS320 TMS320C671 C6713 3 to filte filterr signal signalss using using Code Code Compos Composer er Studio compiler for the chip. The student should understand how to design algorithms for implementation

Outcomes:

Students will: a) Have the ability to conduct experiments, as well as to analyze and interpret data in various problems using MATLAB, and DSP starter kit using TMS320C6713  b) Be able to design discrete-time filters and/or implement implement and verify a filtering system c) Gain knowledge of DSP and be able to design filtering methods in discrete-time domains, as well as to analyze the method in the frequency do domain main

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Digital Signal Processing Lab

Index

INTRODUCTIO INTRO DUCTION N TO DSP STARTER KIT (DSK) USNIG TMS320C6 TMS320C6713...................... 713..........................6 ....6 SINE WAVE GENERATION GENERATION AND REAL-TIME DFT USING DSK...................................24 DSK............................... ....24 PSEUDO RANDOM RANDOM SEQUENCE GENERATOR GENERATOR USING DSK...................................... DSK.............................. .............31 .....31 REAL TIME IIR FILTER DESIGN DESIGN USING DSK...................................................................34 DSK................................................... ................34 REAL TIME FIR FILTER DESIGN DESIGN USING DSK.................................................... DSK.................................................................. ..............51 51 BIBLIOGRAPHY .......................................................................................................................64

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08.508 Expt. Exp t. No. 1 Objectives:

Digital Signal Processing Lab INTROD INTRODUCT UCTION ION TO DSP DSP STAR STARTER TER KIT (DSK) (DSK) U USNIG SNIG TMS320C6 TMS320C6713 713

a) To study the architecture of TMS320C6713 DSP processor   b) To familiarize DSP Starter Kit (DSK) for for TMS320C6713 c) To familiarize Code Composer Studio (CCS) software for DSK 

Equipments required: 1. DSK for TMS320C6713 2. PC installed Software- CCS 3. USB cable 4. Audio stereo cable (3.5mm banana connector at one end and crocodile pin at other end) 5. DSO and connecting probe Theory: 1.1 Introduction to DSP processors:

Digital Signal Processing is the mathematics, the algorithms, and the techniques used to manipulate the signals in digital form. Signals originate as sensory data from the real world: seismic vibrations, visual images, sound waves, etc. This technology includes a wide variety of goals, such as: enhancement of visual images, recognition and generation of speech, compression of data for storage and transmission, etc. Digital Signal Processors Digital Processors are microproces microprocessors sors specifically specifically designed designed to handle Digital Signal Processing tasks. These devices can be used for variety of applications like cellular telephones to advanced scientific instruments. Hardware engineers use "DSP" to mean Digital Signal Processor, just as algorithm developers use "DSP" to mean Digital Signal Processing. Microprocessor or General Purpose Processor such as Intel xx86 or Motorola 680xx family contains only CPU. There is no RAM, ROM, I/O ports and Timer  Microcontroller such as 8051 family contains CPU, RAM, ROM, I/O ports, Timer and Interrupt circuitry. Some Microcontrollers also contain ADC, DAC and Flash Memory DSP Processors such as Texas Instruments and Analog Devices contains CPU, RAM, ROM, I/O ports and Timer. DSP processors are optimized for fast arithmetic, extended precision, dual operand fetch, zero overhead loop and circular buffering.

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Digital Signal Processing Lab

The basic features of a DSP Processor are: Features

Use

Fast-Multiply accumulate

Most DSP algorithms, including filtering, transforms, etc. are multiplication- intensive

Multiple Mult iple – Access Access memory memory archite architecture cture

Many data-int data-intensive ensive DSP operations operations require require reading reading a program program instruction and multiple data items during each instruction cycle for best performance

Spec Sp ecia iallized ized addr addres esssing ing mod modes es

Effi Effici cien entt han handl dlin ing g of of dat dataa arr array ayss and and firs rstt-iin, firs rstt-ou outt buf bufffer erss in in memory

Specialized program contr ntrol

Efficien entt co con ntrol of loops ops for man any y iterat atiive DSP DSP algo gorrithms. Fast interrupt handling for frequent I/O operations.

On-chip On-chi p peripheral peripheralss and I/O interfaces interfaces

On-chip On-chip peripheral peripheralss like like A/D A/D converter converterss allow allow for small small low low cost system designs. Similarly I/O interfaces tailored for common  peripherals allow clean interfaces to off-chip I/O devices.

DSP Chip Manufacturers: There are various manufacturers for DSP chips. Some of the well known companies are Analog Devi De vices ces,, Moto Motoro rola la,, Luce Lucent nt Te Techn chnol olog ogie ies, s, NEC, NEC, SGSSGS-Th Thom omps pson on,, Cone Conexan xant, t, and Te Texa xass Instruments. In the lab Texas Instruments (TI) DSP chip TMS320C6713 is used. 1.2 TMS320C6713 DSP Processor In 1983, Texas Instruments released their first generation of DSP chips, the TMS320 single-chip DSP series. The first generation chips (C1x family) could execute an instruction in a single 200-nanosecond (ns) instruction cycle. The current generation of TI DSPs includes the C2000, C5000, and C6000 series, which can run up to eight 32-bit parallel instructions in one 4.44ns instruction cycle, for an instruction rate of 1.8 x 109 instructions per second. The C2000 and C5000 series are fixed-point processors. The C6000 series contains both fixed point and floating-point processors. In the lab, we will be using the C6713 processor, a member of C67x

family of floating-point processors. Features of TMS320C6713 are: • Highest-Performance Floating-Point Digital Signal Processor (DSP): • Eight 32-Bit Instructions/Cycle 32/64-Bit Data Word • 300, 225, 200MHz (GDP* and ZDP*), and 225, 200, 167MHz (PYP*) Clock Rates • • 3.3, 4.4, 5, 6 Instruction Cycle Times 2400/1800, 1800/1350, 1600/1200, and 1336/1000 MIPS /MFLOPS # •  ______________________  ___________ _______________________ _______________________ _______________________ _______________________ _______________________ _______________________ ______________________ ____________________  _________  * GDP, ZDP and PYP are the three types of Plastic Ball Grid Array IC package # MIPS stand for 'Million Instructions Per Second' and MFLOPS stands for "Million Floating-Point Operations Per Second"

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Digital Signal Processing Lab

Rich Peripheral Set, Optimized for Audio Highly Optimized C/C++ Compiler • Extended Temperature Devices Available • Advanced Very Long Instruction Word (VLIW) TMS320C67x™ DSP Core • Eight Independent Functional Units: •



Two ALUs (Fixed-Point) Four ALUs (Floating- and Fixed-Point) Two Multipliers (Floating- and Fixed-Point) Load-Store Architecture With 32 32-Bit General-Purpose Registers Instruction Packing Reduces Code Size All Instructions Conditional Instruction Set Features  Native Instructions for IEEE 754 Single- and Double-Precision Byte-Addressable (8-, 16-, 32-Bit Data) 8-Bit Overflow Protection Saturation; Bit-Field Extract, Set, Clear; Bit-Counting; Normalization  

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• • • • • • •

L1/L2 Memory Architecture • 4K-Byte L1P Program Cache (Direct-Mapped) 4K-Byte L1D Data Cache (2-Way) • 256K-Byte L2 Memory Total: 64K-Byte L2 Unified Cache/Mapped RAM, and • 192K-Byte Additional L2 Mapped RAM • Device Configuration Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot • Endianness*: Little Endian, Big Endian • • 32-Bit External Memory Interface (EMIF) • Glueless Interface to SRAM, EPROM, Flash, SBSRAM, and SDRAM 512M-Byte Total Addressable External Memory Space • Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels) 16-Bit Host-Port Interface (HPI) Two Multichannel Audio Serial Ports (McASPs) 1. Two Indep Independe endent nt Clock Clock Zones Zones Each Each (1 TX TX and 1 RX) RX) 2. Eight Eight Seri Serial al Data Data Pins Pins Per Per Port: Port: Individually assignable to any of the Clock Zones

 ____________________________________ ___________________________________________________________________  _________________________________________________________________________ ______________________________  _  Endianness is the attribute of a system that indicates whether integers are represented from left to right or right to left. Big endian endia n is the most signifi significant cant byte of any multi-byte multi-byte data field is stored stored at the lowest lowest memory address address,, which is also the address of the larger field. Little endian means that the least least significant byte of any multi-byte data fiel field d is stored at the lowest memory address, which is also the address of the larger field.

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08.508

Digital Signal Processing Lab Each Clock Zone Includes: 1. Progra Programma mmable ble Clock Clock Generat Generator or 2. Progra Programma mmable ble Fram Framee Sync Sync Gener Generato atorr 3. TDM Stream Streamss From From 2-32 2-32 Time Time Slots Slots 4. Su Suppo pport rt for for Slo Slott Siz Size: e:

8, 12, 16, 20, 24, 28, 32 Bits 5. Data Data Format Formatter ter for for Bit Bit Manipu Manipulat lation ion 3. Wide Variety Variety of I2S and and Similar Similar Bit Stream Formats Formats 4. Integrated Integrated Digital Digital Audio Interf Interface ace Transmit Transmitter ter (DIT) (DIT) Supports Supports:: 1. S/PDIF S/PDIF*, *, IEC609 IEC6095858-1, 1, AES-3, AES-3, CP-430 CP-430 Format Formatss 2. Up to 16 tran transm smit it pins pins 3. Enhanc Enhanced ed Chann Channel el Stat Status/ us/Use Userr Data Data 5. Extensive Error Checking and Recovery Two Inter-Integrated Circuit Bus (I2C Bus™) Multi-Master and Slave Interfaces Two Multi-channel Buffered Serial Ports: 6. Serial Serial-Per -Periph iphera eral-I l-Inte nterfa rface ce (SPI) (SPI) 7. Hi Highgh-Sp Speed eed TDM TDM Int Inter erfa face ce 8. AC97 AC97 Int Inter erffac acee Two 32-Bit General-Purpose Timers Dedicated GPIO Module with 16 pins (External Interrupt Capable) Flexible Phase-Locked-Loop (PLL) Based Clock Generator Module IEEE-1149.1 (JTAG#) Boundary-Scan-Compatible Package Options: 208-Pin PowerPAD™ Plastic (Low-Profile) Quad Flat pack (PYP) • 272-BGA Packages (GDP and ZDP) • 0.13-µm/6-Level Copper Metal Process • CMOS Technology 3.3-V I/Os, 1.2-V Internal (GDP & PYP) 3.3-V I/Os, 1.4-V Internal (GDP)(300 MHz only)  _______________________________________________________  ___________________________ ______________________________________________  __________________  * S/PDIF is a digital audio interconnect used in consumer audio equipment over relatively short distances. The name stands  for Sony/Philips Digital Interconnect Format. S/PDIF is standardized in IEC 60958-1. IEC stands for International Electro techni technical cal Commis Commissio sion n and is non-gov non-govern ernmen mental tal int intern ernati ationa onall standar standards ds organi organizat zation ion tha thatt pre prepar pares es and publis publishes hes  International Standards for all electrical, electronic and related technologies – collectivel collectivelyy known as "electro technology". *AES3 *AES 3 is the digita digitall audio standard and frequently frequently called AES/EBU AES/EBU and also published as part of IEC 60958, is used for carrying digital audio signals between devices. It was developed by the Audio Engineering Society (AES) and the European  Broadcasting Union (EBU) (EBU) #JTAG stands for Joint Test Action Group. It was initially devised devised for testing printed circuit boards using boundary scan and also widely used for IC debug ports

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Digital Signal Processing Lab

1.3 Architecture of TMS320C6713 Functional block of TMS320C6713 processor is shown below:

Internal memory includes a two-level cache architecture with 4kB of level 1 program cache (L1P), 4kB of level 1 data cache (L1D), and 256kB of level 2 memory shared between  program and data space. It has a glueless (direct) interface to both synchronous memories (SDRAM and SBSRAM) and asynchronous memories (SRAM and EPROM). On-chip On-chi p peripheral peripheralss include include two McBSPs (Multi-chan (Multi-channel nel Buffered Buffered Serial Serial Port), Port), two McASPs (Multi-channel Audio Serial Port), two general purpose timers, a HPI (Host Port Interface Interf ace)) and a 32-bit 32-bit EMIF EMIF (Exter (External nal Memory Memory Interf Interface ace), ), one dedicat dedicated ed GPIO GPIO (G (Gener eneralalPurposee Input/outpu Purpos Input/output) t) module and two I2C (Inter Integrated Integrated Circuit) Circuit) ports. It requires requires 3.3V for I/O and 1.26V for the core (internal). Internal buses include a 32-bit program address bus, a 256 bit program data bus to accommodate eight 32-bit instructions, two 32-bit data address buses, two 64-bit data buses and two 64-bit store data buses. With a 32-bit address bus, the total memory space is, including external memory spaces. CPU Features: The CPU consists of eight independent functional units divided into two data paths, A and B, as shown in functional block. Each path has a unit for multiply operations (.M), for logical and arithmetic operations (.L), for branch, bit manipulation, and arithmetic operations (.S), and for loading/storing and arithmetic operations (.D). The eight functional units consist of four floating/ fixed-point ALUs (two .L and two .S), two fixed-point ALUs (.D units), and two floating / fixed point multipliers (.M units). Each functional unit can read directly from or write directly d irectly to the Department of ECE, VKCET

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Digital Signal Processing Lab

register file within its own path. Each path includes a set of sixteen 32-bit registers, A0 through A15 and B0 through B15.Units ending in 1 write to register file A, and units ending in 2 write to register file B. Two cross-paths (1x and 2x) allow functional units from one data path to access a 32-bit operand from the register file on the opposite side. There can be a maximum of two cross path source reads per cycle. Each functional unit side can access data from the registers on the opposite side using a cross-path (i.e., the functional units on one side can access the register set from the other side). There are 32 general-purpose registers, but some of them are reserved for specific addressing or are used for conditional instructions.

Memory Features: Memory configuration is:

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Digital Signal Processing Lab

Memory map range address is:

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Digital Signal Processing Lab

1.4 DSP Starter Kit Thee TMS32 Th TMS320C 0C67 6713 13 DSP DSP chip chip is very very po powe werf rful ul by it itse self lf,, but fo forr devel developm opmen entt of  programs, a supporting architecture is required to store programs and data, and bring signals on and off the board. In order to use this DSP chip in a lab or development environment, a circuit  board containing appropriate components, designed and manufactured by TI, is provided. Together, Code Composer Studio, the DSP chip, and supporting hardware make up the DSP Starter Kit, or DSK. Package Contents:

TMS320C6713 DSK Overview Block Diagram

The C6713 DSK has a TMS320C6713 DSP on-board that allows full-speed verification of code with Code Composer Studio. The C76713 DSK provides: Department of ECE, VKCET

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Digital Signal Processing Lab

1. A USB USB Inter nterffac acee 2. SDRAM an and RO ROM 3. An analog analog interf interface ace circuit circuit for Data conversion conversion (AIC) 4. An I/ I/O po port 5. Embedd Embedded ed JTAG JTAG emulat emulation ion suppor supportt Connectors Connect ors on the C6713 DSK provide provide DSP external memory interface interface (EMIF) (EMIF) and peripheral peripheral signals that enable its functionality to be expanded with custom or third party daughter boards. The DSK provides a C6713 hardware reference design that can assist you in the development of your own C6713-based products. In addition to providing a reference for interfacing the DSP to various vario us types types of memories and peripherals peripherals,, the design also addresses addresses power, clock, JTAG, and  parallel peripheral interfaces. The C6711 DSK includes a stereo codec. This analog interface circuit (AIC) has the following characteristics: High-Performance Stereo Codec 90-dB SNR Multi-bit Sigma-Delta ADC (A-weighted at 48 kHz) • • 100-dB SNR Multi-bit Sigma-Delta DAC (A-weighted at 48 kHz) 1.42 V – 3.6 V Core Digital Supply: Compatible With TI C54x DSP Core Voltages • 2.7 V – 3.6 V Buffer and Analog Supply: Compatible Both TI C54x DSP Buffer • Voltages 8 kHz, 16 kHz, 24 kHz, 32 kHz, 44 kHz, 48 kHz and 96-kH 96-kHzz Sampling-Freque Sampling-Frequency ncy Support Software Control via TI McBSP-Compatible Multiprotocol Serial Port I2C-Compatible and SPI-Compatible Serial-Port Protocols • • Glue less Interface to TI McBSPs Audio-Data Input/output Via TI McBSP-Compatible Programmable Audio Interface • I2S-Compatible Interface Requiring Only One McBSP for both ADC and DAC Standard I2S, MSB, or LSB Justified-Data Transfers • 16/20/24/32-Bit Word Lengths • AIC32 stereo codec line with Line In, Line Out, MIC and headphone jacks to interface with analog audio signals that are sampled and digitized so it can be processed by DSP •

The C6713DSK has the following features: Department of ECE, VKCET

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Digital Signal Processing Lab

The 6713 DSK is a low-co low-cost st standa standalon lonee develop developme ment nt platf platform orm that that enable enabless customers to evaluate and develop applications for the TI C67XX DSP family. The DSK also serves as a hardware reference design for the TMS320C6713 DSP. Schematics, logic equations and application notes are available to ease hardware development and reduce time to market. Thee DSK Th DSK us uses es the the 32-bi 32-bitt EMIF EMIF for for th thee SDRAM SDRAM (CE0 (CE0)) an and d da daug ught hter er ca card rd expansion interface (CE2 and CE3). The Flash is attached to CE1 of the EMIF in 8-bit mode. An on-board AIC23 codec allows the DSP to transmit and receive analog signals. McBSP0 is used for the codec control interface and McBSP1 is used for data. Analog audio I/O is done through four 3.5mm audio jacks that correspond to microphone input, line input, line output and headphone output. The codec can select the microphone or the line input as the active input. The analog output is driven to both the line out (fixed gain) and headphone (adjustable gain) connectors. McBSP1 can be re-routed to the expansion connectors in software. A programmable logic device called a CPLD is used to implement glue logic that ties the board components together. The CPLD has a register based user interface that lets the user configure the board by reading and writing to the CPLD registers. The registers reside at the midpoint of CE1. The DSK includes 4 LEDs and 4 DIP switches as a simple way to provide the user with interactive feedback. Both are accessed acce ssed by reading and writing to the CPLD registers. An provide includedthe 5V external supply3.3V is used to power theanalog board.voltages. On-board voltage regulators 1.26V DSP power core voltage, digital and 3.3V A voltage supervisor monitors the internally generated voltage, and will hold the board in reset until the supplies is within operating specifications and the reset button is released. If desired, JP1 and JP2 can be used as power test points for the core an and d I/O power supplies. Codee Compos Cod Composer er co comm mmuni unica cate tess wi with th th thee DSK DSK th thro roug ugh h an embe embedde dded d JTAG JTAG emulator with a USB host interface. The DSK can also be used with an external emulator through the external JTAG connector. Code Composer Studio (CCS): CCS is a powerful integrated development environment that provides a useful transition  between a high-level (C or assembly) DSP program and an on-board machine Digital Signal Pr Proc oces essi sing ng lang languag uagee progr program am.. CCS CCS co cons nsis ists ts of a se sett of so soft ftwa ware re to tool olss and li libr brar arie iess fo forr

developing DSP programs, compiling and linking them into machine code, and writing them into memory on the DSP chip and on-board external memory. It also contains diagnostic tools for analyzing and tracing algorithms as they are being implemented on-board. In the lab, we will always use CCS to develop, compile, and link programs that will be downloaded from a PC to DSP hardware.

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Digital Signal Processing Lab

1.5 INSTALLATION System Requirements: Minimum •

• • • •

233MHz 233 MHz or Higher Higher Pentium Pentium-Co -Compa mpatib tible le CPU 600MB of free hard disk space 128MB of RAM SVGA (800 x 600 ) display Local CD-ROM drive

Recommended •

• •

500MHz

or

Higher

Pent ntiium

Compatible CPU 128MB RAM 16bit Color 

Supported Operating Systems • • • •

Windows® 98 Windows NT® 4.0 Service Pack 4 or higher  Windows® 2000 Service Pack 1 Windows® XP

Troubleshooting Connectivity: If Code ComposerDSK Studio IDE fails to configure your port correctly, perform the following steps: 1. Test the USB port by running DSK Port test from the start menu Use Start → Programs → Texas Instruments → Code Composer Studio → Code Composer Studio C6713 DSK Tools → C6713 DSK Diagnostic Utilities OR  Click on “6713 “6713 DSK Diagnostics Utilities” Utilities” icon in the desktop The below Screen will appear 

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2. Select → Start → Select 6713 DSK Diagnostic Diagnostic Utility Utility Icon from Desktop Desktop 3. The The Scre Screen en Loo Look k like like as as abov abovee 4. Select Start Option 5. Utilit Utility y Progr Program am will will tes testt the the board board 6. After testing Diagnostic Status you will get PASS If the board still fails to detect Go to CMOS setup → Enable the USB Port Option (The required Device drivers will load along with CCS Installation) OR  Reconnect USB cable, refresh the PC and do the first step 1.6 Introduction to Code Composer Studio Code Composer is the DSP industry's first fully integrated development environment (IDE) with DSP-specif DSP-specific ic functionalit functionality. y. With a familiar familiar environment environment liked MS-based MS-based VC++, Code Composer lets you edit, build, debug, profile and manage projects from a single unified environment. Other unique features include graphical signal analysis, injection/extraction of data signals via file I/O, multi-processor debugging, automated testing and customization via a Cinterpretive scripting language and much more. CODE COMPOSER FEATURES INCLUDE: 1. IDE (Inte (Integra grated ted Develo Developme pment nt Environ Environmen ment) t) 2. Debug IDE 3. Adva Advance nced d wat watch ch wi wind ndow owss 4. Inte Integr grat ated ed edi edito tor  r  5. File I/O, Probe Points Points,, and graphi graphical cal algorit algorithm hm scope scope probes probes 6. Advance Advanced d graphi graphical cal signal signal anal analys ysis is 7. Automated Automated testing testing and customizati customization on via scripting scripting 8. Visual Visual projec projectt manag manageme ement nt sys system tem 9. Compile Compile in in the the backgroun background d while while editin editing g and debugging debugging 10. Multi-proc Multi-processor essor debugging debugging 11. Help on the the target target DSP Procedure to work on Code Composer Studio: To create the New Project In CCS, select ‘Project’ and then ‘New’. A window w indow named ‘Project Creation’ will appear. In the field labeled ‘Project Name’, enter ‘Lab01’ (or your own project name). In the field ‘Location’, click on the ‘. . .’ on the right side of the field and navigate to the folder to store the file. In the field ‘Project Type’, verify that ‘Executable (.out)’ is selected, and in the field ‘Target’, verify that ‘TMS32067XX’ is selected. Finally, click on ‘Finish’. CCS has now created a project file Lab01.pjt, which will be used to build an executable program. This file is stored on specified path.

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To add supporting files to project: The next step in creating a project is to add the appropriate support files to the file Lab01. In the CCS window, go to ‘Project’ and then ‘Add Files to Project . . .’. In the window that appears, click on the folder next to where it says ‘Look In:’ Make sure that you are in the path where support files are saved. The C source code file contains functions for initializing the DSP and peripherals. The Vectors file contains information about what interrupts (if any) will be used and gives the linker information about resetting the CPU. This file needs to appear in the first  block of program memory. The linker command file tells the linker how the vectors file and the internal, external, and flash memory are to be organized in memory. In addition, it specifies what  parts of the program are to be stored in internal memory and what parts are to be stored in the external memory. In general, the program instructions and local/global variables will be stored in internal random access memory or IRAM. To Add Appropriate Libraries to a Project: In addition to the support files that you have been given, there are pre-compiled files from TI that need to be included with your project. For this project, we need run-time support libr librar arie ies. s. For For the the C671 C6713 3 DSK, DSK, ther theree ar aree thre threee supp suppor ortt li libr brar arie iess ne need eded ed:: cs csl6 l671 713. 3.li lib, b, dsk6713bsl.lib, and rts6700.lib. The first is a chip support library, the second a board support library, and the third is a real-time support library. Besides the above support libraries, there is a

GEL (general extensionadded language) 6713.gel) used initialize GEL file was automatically when file the (dsk6211 project file Lab01.pjt wastocreated, butthe theDSK. otherThe libraries must be explicitly included in the same manner as the previous files. Go to ‘Project’ and then ‘Add Files to Project’. For ‘Files of type’, select ‘Object and Library Files (*.o*,*.l*)’. Navigate to the path for support and select the files rts6700.lib . . . In the left sub-window of the CCS main window, double-click on the folder ’Libraries’ to make sure the file was added correctly. These files, along with our other support files, form the black box that will be required for every project created in this lab. The only files that change are the source code files that code a DSP algorithm and possibly a vectors file.

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To Create a Source file File → New → Type the code (Save & give file name, E.g.: sum.c). To Add Source Code Files to a Project: The last file that you need to add is your C source code file. This file will contain the code needed to perform the required task. Go back to ‘Project’ and then ‘Add Files to Project. For ‘Files of type’, select ’C/C++ source files (*.c)’, click on the file and add it to your project  by clicking on ‘Open’. Files for Non-real time programs: 1. Library file- rts6700.lib Path: C:\CCStudio_v3.1\c6000\cgtools\lib\rts6700.lib 2. Command and linking file- hello.cmd Path: C:\CCStudio_v3.1\tutorial\dsk6713\hello1\hello.cmd Files for real time programs: 1. Configuration file: To create configuration file-

File →Use New → DSP/BIOS Configuration dsk6713.cdb Save as filename.cdb  (keep same name as project, so it is easy to identify) in the project folder and add this file to the project as similar way to other files (But file type is *.cdb). Then three files are added in generated file folder automatically. Within that open filenamecfg_c.c file and copy the line “#include”filenamecfg.h”, “ #include”filenamecfg.h”, paste it to the source file 2. Library file: dsk6713bsl.lib Path: C:\CCStudio_v3.1\c6000\\dsk6713\lib\dsk6713bsl.lib 3. Add header file generated within filenamecfg.h to source file To Compile: Project → Compile To Build: Project → build, which will create the final .out executable file.(Eg. sum.out). Procedure to Load and Run program: Load the program to DSK: DSK: File → Load pr program ogram → sum.out (Which is in the folder “Debug” in the project folder.) To execute project: Debug → Run. To watch variables: View → Memory Enter the variable in the field of address and select format

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Digital Signal Processing Lab

To plot variables: View → Graph → Time/frequency The following display will appear 

Give the variable name in the field “Start Address” and suitable parameters for others Procedure to run real time program: a) To To connect DSK to PC 1. Connect DSO DSO probe to the audio cord’ cord’s crocodile crocodile end and connect audio cord cord to Line-out pin of DSK  2. Connect power supply to DSK  DSK 

3. Connect Wait for POST to le complete, POST observe observe 1 kHz sinusoidal wave in DSO 4. USB cable cab from from PCduring to DSK  DSK  5. Launch Code Code Composer Composer Studio Studio C6713 C6713 DSK  6. CCS will will load and and wait for your your input 7. Connect Connect to C6713 C6713 DSK by Debug>Conn Debug>Connect ect (or Alt+C) Alt+C) and verify verify “The target target now connected” message on left corner of CCS  b) To To develop and run the program for sine wave generation 1. Create Create new proj project ect named named “sine “sine.pj .pjt”. t”. 2. Add library library file file “dsk6713bsl “dsk6713bsl.lib” .lib” to the projec projectt 3. Create ate DSP/BIOS co con nfiguration file and save “sinewave.cdb” 4. Add “sinew “sinewave. ave.cdb” cdb” to the projec projectt

con onffiguration

file

as

5. Type the the source source code code and save save as “sine “sinewav wave.c” e.c” Department of ECE, VKCET

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Digital Signal Processing Lab 6. Add the source source code to the the proj project ect 7. Open Open “s “sin inew ewav avec ecfg fg_c _c.c” .c” and co copy py - #i #inc nclu lude de "s "sin inew ewave avecf cfg. g.h" h" sa save ve it to th thee source code “sinewave.c” 8. Comp Compil ilee proj projec ectt 9. Buil Build d the the proj projec ectt 10. Load the executable executable file and run the program program and observe sine sine wave and plot it with frequency and volt

Sample programs and outputs 1.Linear convolution #include #include int y[20]; int x[10]={1,2,3,2,1,0,0,0,0}; int h[10]={2,1,0,1,2,0,0,0,0}; main() { int l=5; int m=5; int n,k;

:

for(n=0;nConnect Debug>Connect (or (or Alt+C) Alt+C) and verify verify “The “The target target now connected” message on left corner of CCS

  2. DFT of Real-time sine wave a) To To connect DSK to PC 1. Connect Signal Signal generator generator (set (set as 1Vpp, 2 kHz sine sine wave) probe probe to the audio audio cord’ss crocodile end and connect audio cord to Line-in pin of DSK  cord’ 2. Connect power supply to DSK  DSK  3. Wait for for POST to complete complete 4. Connect USB cable cable from from PC to DSK  5. Launch Code Code Composer Composer Studio Studio C6713 C6713 DSK  6. CCS will will load load and wait wait for your your input input 7. Connect to C6713 C6713 DSK by Debug>Connect Debug>Connect (or Al Alt+C) t+C) and verify verify “The target target now connected” message on left corner of CCS  b) To To develop and run the program for DFT of real time sinewave 1. Create Create new proje project ct named named “dftsin “dftsinewa ewave.p ve.pjt” jt”.. 2. 3. 4. 5.

Typethe thesource source source code and as t“dftsinewav “dftsinewave.c” e.c” Add sou rce code cod e to thesave projec project Add library library file “dsk6713bsl. “dsk6713bsl.lib” lib” to the the project project Crea Create te DSP/ DSP/B BIOS IOS conf confiigura gurattion fil ilee and and save ave conf confiigura gurattion file as “dftsinewave.cdb” 6. Add “dft “dftsin sinewa ewave.c ve.cdb” db” to to the projec projectt 7. Comp Compil ilee proj projec ectt 8. Buil Build d the the proj projec ectt 9. Load Load the execu executab table le file file and and run run the progra program m 10. Observe the input buffer buffer and DFT sequence using Vi View ew > Memory tool Programs: 1. Sine wave generation

#include "sinewavecfg.h" #include #include "C:\CCStudio_v3.1\C6000\dsk6713\include\dsk6713.h" #include "C:\CCStudio_v3.1\C6000\dsk6713\include\dsk6713_aic23.h" #define Fs 32000 // Sampling frequency in Hz #define f 5000 // Frequency in Hz #define pi ( ( double )3.1415927 ) #define Vm 12659//Peak value of sine wave with 79uV resolution, 12659 for 1Vpp float x[Fs/1000];

// Fs/1000 is length of sequence

DSK6713_AIC23_Config config = { \   0x0017, /* 0 DSK6713_AIC23_LEFTINVOL Left line input channel volume */ \ Department of ECE, VKCET

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Digital Signal Processing Lab

  0x0017, /* 1 DSK6713_AIC23_RIGHTINVOL Right line input channel volume */\   0x00ff, /* 2 DSK6713_AIC23_LEFTHPVOL Left channel headphone volume */ \ 0x00ff, /* 3 DSK6713_AIC23_LEFTHPVOL right channel headphone volume */ \   0x0011, /* 4 DSK6713_AIC23_ANAPA DSK6713_AIC23_ANAPATH Analog audio path control */ \   0x0000, /* 5 DSK6713_AIC23_DIGPA DSK6713_AIC23_DIGPATH Digital audio path control */ \   0x0000, /* 6 DSK6713_AIC23_POWERDOWN Power down control */ \   0x0043, /* 7 DSK6713_AIC23_DIGIF Digital audio interface format */ \   0x0081, /* 8 DSK6713_AIC23_SAMPLERATE DSK6713_AIC23_SAMPLERATE Sample rate control */ \   0x0001 /* 9 DSK6713_AIC23_DIGACT Digital interface activation */ \ }; void main() { int n; float b; int N=Fs/f; double theta =2*pi*f/Fs; DSK6713_AIC23_CodecHandle hCodec; DSodec K6ec 71=3_DSK6 iniK671 t();713_ //;Initiali// zOpen e ben oarth d esuco ppdec orct library hCod hC DS 3_AI AIC2 C23_ 3_op open enCo Code dec( c(0, 0, &con &confi fig) g); //Op the code DSK6 DS K671 713_ 3_AI AIC2 C23_ 3_se setF tFre req( q(hC hCod odec ec,, 4); 4); //Se //Sett the the samp sampli ling ng rat ratee at 32 32 kHz kHz for(n=0;n