05 Unit 2

SOFTWARE ARCHITECTURE OF THE 8088 AND 8086 MICROPROCESSOR

UNIT 2: SOFTWARE ARCHITECTURE OF THE 8088 AND 8086 MICROPROCESSORS.

INTRODUCTION: To Program either the 8088 or 8086 using assembly language, we must understand how the microprocessor and its memory and input/output subsystems operate from a software point of view. This module will examine the software architecture of the 8088 and 8086 microprocessor. The following topics are covered here :

2.1 Internal architecture of microprocessor 2.2 Memory address space and data organization 2.3 Register and memory 2.4 Input/Output

LEARNING OBJECTIVES: The objectives of this topic are to: 1. Introduce the internal architecture and its register. 2. Show what can be done with architecture and how to do it through software.

LEARNING OUTCOMES: After completed this module trainees should be able to : 1. List down the various register in the microprocessors 2. Explain how information such as numbers, characters, and instruction stored in memory. 3. Understand the used of data register 4. Explain how the memory and internal register array are instructed. 5. Define the terms memory segment and offset address. 6. Calculate the effective address for the next program step using the contents of the instruction pointer(IP) and code segment(CS) register.

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SOFTWARE ARCHITECTURE OF THE 8088 AND 8086 MICROPROCESSOR

2.1 INTERNAL ARCHITECTURE OF THE 8088/8086 MICROPROCESSOR. 2.1.1 Internal Hardware architectures The internal architectures of the 8088 and 8086 are similar. They both employ parallel processing, that is they are implemented with several simultaneously operating processing unit. Figure 2.1.1a illustrates the internal architecture of the 8088 and 8086 microprocessors.

EXECUTION UNIT

INSTRUCTION PIPELINE

BUS INTERFACE UNIT

SYSTEM BUS

SYSTEM BUS

Figure 2.1.1a

Pipelined architecture of the 8088/8086 microprocessors.

There are two processing units, each unit has dedicated functions and both operate at the same time. This parallel processing effectively makes the fetch and execution of instructions independent operations. The processing units are : 1. The bus interface unit (BIU) 2. The execution unit (EU)

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SOFTWARE ARCHITECTURE OF THE 8088 AND 8086 MICROPROCESSOR

2.1.1.1. Bus interface unit (BIU) The bus interface unit is the 8088/8086’s interface to the outside world. Interface mean the path by which it connects to the external devices. •

The BIU is responsible for performing all external bus operations, such as instruction fetching, reading and writing of data operands for memory, and inputting or outputting data for input/output peripherals.

•

These information transfers takes place over the system bus. This bus includes an 8 bit bi-directional data bus for the 8088 (16 bit for the 8086), a 20-bit address bus, and the signals needed to control transfers over the bus.

•

Perform other functions related to instruction and data acquisition.

•

Responsible for instruction queuing and address generation.

•

The BIU contains the segment registers, the instruction pointer, address generation adder, bus control logic, and an instruction queue. Figure 2.1.1b shows the bus interface unit of the 8088/8086 in more detail.

Figure 2.1.1b Execution and bus interface unit

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SOFTWARE ARCHITECTURE OF THE 8088 AND 8086 MICROPROCESSOR

•

The BIU uses a mechanism known as instruction queue to implement a pipeline architecture. This queue permits the 8088 to prefetch up to 4 bytes (6 bytes for 8086) of instruction code.

•

Whenever the queue is not full- that is, it has room for at least 2 more bytes, and, at the same time, the execution unit is not asking it to read or write data from memory – the BIU is free to look ahead in the program by prefetching the next sequential instructions.

•

Prefetched instructions are held in the first – in first – out (FIFO) queue. Whenever a byte is loaded at the input end of the queue, it is automatically shifted up through the FIFO to the empty location nearest the output. The code is held until the execution unit is ready to accept it.

•

Since instructions are normally waiting in the queue, the time needed to fetch many instructions of the microcomputers is eliminated. If the queue is full and the EU is not requesting access to data in memory, the BIU does not need to perform any bus cycle. These intervals of no bus activity, which occurs between bus cycles, are known as idle states.

2.1.1.2 Execution unit (EU) •

The execution unit is responsible for decoding and executing instructions. It consist of :

•

i.

Arithmetic logic unit (ALU)

ii.

Status and control flags

iii.

General purpose register

iv.

Temporary – operand register.

The EU accesses instructions from the output end of the instruction queue and data from the general purpose registers or memory.

•

It reads one instruction byte after the other from the output of the queue, decodes them, generates data addresses if necessary, passes them to BIU and requests it to perform the read or write cycle to memory or I/O, and performs the operation specified by the instruction.

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SOFTWARE ARCHITECTURE OF THE 8088 AND 8086 MICROPROCESSOR

•

During the execution of the instruction, the EU may test the status and control flags, and updates these flags based on the results of executing the instruction. If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted to the top of the queue.

2.1.2 Software Model Of The 8088/8086 Microprocessor. •

The purpose of developing a software model is to aid the programmer in understanding the operation of the microcomputer system from a software point of view.

•

The programmer needs to know the various registers within the device and to understand their purpose, functions, operating capabilities, and limitations.

•

The programmer also needs to know how external memory and input/output peripherals are organized and how they are addressed to obtain instructions and data.

•

The software architecture of the 8088/8086 microprocessors includes 13 16-bit internal registers. ⇒ The instruction pointer (IP) ⇒ Four data register :i. ii. iii. iv.

AX BX CX DX

⇒ Two pointer register :i. ii.

BP SP

⇒ Two index register :i. ii.

SI DI

⇒ Four segment register :i. ii. iii. iv.

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CS DS SS ES

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SOFTWARE ARCHITECTURE OF THE 8088 AND 8086 MICROPROCESSOR

⇒ Status register •

The software architecture of the 8088 microprocessor is illustrated with the software model shown in Figure 2.1.2, which is 8088 architecture implements independent memory and input/output address space.

•

Notice that the memory address space is 1,048,576 bytes (1 Mbyte) in length and the I/O address space is 65,536 bytes (64Kbytes) in length.

External memory Address space 8088/8086 MPU

0000H

Code segment ( 64 K bytes )

CS

0000H Data segment ( 64 K bytes )

DS SS

Input/output Address space

ES AH

AL

BH

BL

CH

CL

DH

DL

Stack segment ( 64 K bytes )

FFFFH

SP BP SI DI

Extra segment ( 64 K bytes )

SR FFFFH Figure 2.1.2 Software model of the 8088/8086 microprocessor

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SOFTWARE ARCHITECTURE OF THE 8088 AND 8086 MICROPROCESSOR

Exercise 2.1 1. Name the two interval processing units of the 8088. 2. Which processing unit of the 8088 is the interface to the outside world? 3. What are the lengths of the 8086’s address bus and data bus? 4. How large is the instruction queue of the 8088? The 8086? 5. List the elements of the execution unit. 6. What Is the purpose of a software model for a microprocessor? 7. What must an assembly-language programmer know about the registers within the 8088 microprocessor? 8. How many registers are located within the 8088? 9. How large is the 8088’s memory address space? 10. How large is the 8086’s I/O address space?

.

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SOFTWARE ARCHITECTURE OF THE 8088 AND 8086 MICROPROCESSOR

2.2

MEMORY ADDRESS SPACE AND DATA ORGANIZATION.

2.2.1 Memory Address Space How information such as numbers, characters, and instructions are stored in memory? •

Figure 2.2.1a shows that 8088 microcomputer supports 1Mbytes of external memory.

•

This memory space is organized from a software point of view as individual bytes of data stored at consecutive addresses over the address range 0000 16 to FFFF 16 .

•

The memory in an 8088-based microcomputer is actually organized as 8-bit bytes, not as 16 bit words.

FFFFF FFFFE FFFFD FFFFC

5 4 3 2 1 0

Figure 2.2.1a Memory address space of the 8088/8086 microprocessor.

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SOFTWARE ARCHITECTURE OF THE 8088 AND 8086 MICROPROCESSOR

The 8088 can access any two consecutive bytes as a word of data : •

The lower address bytes is the least significant byte of the word and the higher address byte is its most significant byte.

•

Figure 2.2.1b shows how a word of data is stored in memory. Notice that the storage location at the lower address, 00724 16 , contains the value 0000 0010 2 = 02 16 .

•

The content of the next – higher address storage location, 00725 16 , are 0101 0101 2 = 55 16 . These two bytes represent the word 0101010100000010 2 = 5502 16 .

Address

Memory (binary)

Memory (hexadecimal)

00725 16

0101 0101

55

00724 16

0000 0010

02

Figure 2.2.1b Storing a word of data in memory. •

Words of data can be stored what are called even or odd- addressed word boundaries.

•

The least significant bit of the address determines the type of word boundaries. If this bit is 0, the word is said to be held at an even address boundary; that is, a word at an even- address boundary corresponds to two consecutive bytes, with the least significant byte located at an even address.

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SOFTWARE ARCHITECTURE OF THE 8088 AND 8086 MICROPROCESSOR

Example:

The word in Figure 2.2.1b has its least significant byte at address

00724 16 . Therefore, it is stored at an even- address boundary. •

A word of data stored at an even- address boundary, such as 00000 16 , 00002 16 , 00004 16 , and so on, is said to be an aligned word. That is all aligned words are located at an address that is multiple of 2.

•

A word of data stored at an odd-address boundary, such as 00001 16 , 00003 16 or 00005 16 and so on, is called a misaligned word.

•

Figure 2.2.1c shows some aligned and misaligned words of data.

•

Here words 0, 2, 4 and 6 are examples of aligned-data words. While words 1 , 3 and 5 are misaligned words.

•

Notice that misaligned word 1 consists of byte 1 from aligned word 0 and byte 2 from aligned word 2.

•

When expressing address and data in hexadecimal form, it is common to use the letter H to specify the base. The number 00AB 16 can also be written as 00ABH.

Figure 2.2.1c Examples of aligned and misaligned data words.

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SOFTWARE ARCHITECTURE OF THE 8088 AND 8086 MICROPROCESSOR

EXAMPLE 2.2.1A What is the data word shown in fig. 2.2.1d? Express the result in hexadecimal form. Is it stored at an even – or odd address word boundary? Is it an aligned or misaligned word of data? Solution

Address

Memory (binary)

0072C 16

11111101

0072B 16

10101010

Figure 2.2.1d

The most significant byte of the word is stored at address 0072C 16 and equals 11111101 2 = FD 16 = FDH Its least significant byte is stored at address 0072B 16 and is 10101010 2 = AA 16 = AAH Together the 2 bytes give the word 11111101 10101010 2 = FDAA 16 = FDAAH Expressing the address of the least significant byte in binary form gives 0072BH = 0072B 16 = 00000000011100101011 2 Since the right most bit (LSB) is logic 1, the word is stored at an odd-address boundary in memory; therefore, it is a misaligned word of data.

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SOFTWARE ARCHITECTURE OF THE 8088 AND 8086 MICROPROCESSOR

Double word The double word is another data form that can be processed by the 8088 microcomputer. •

A double word corresponds to four consecutive bytes of data stored in memory; an example of double word data is a pointer.

•

A pointer is a two-word address element that is used to access data or code outside the current segment of memory.

•

The word of this pointer that is stored at the higher address is called the segment base address and the word at the lower address is called the offset value.

•

A double word of data can be aligned or misaligned. An aligned double word is located at an address that is multiple of 4 (e.g., 00000 16 , 00004 16 , and 00008 16 ).

•

A number of aligned and misaligned double words of data are shown in figure 2.2.1e.

Figure 2.2.1e.

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SOFTWARE ARCHITECTURE OF THE 8088 AND 8086 MICROPROCESSOR

An example showing the storage of a pointer in memory is given in Figure 2.2.1f. •

The higher address word, which represents the segment base address, is stored starting at even-address boundary 00006 16 .

•

The most significant byte of this word is at address 00007 16

and

equals

00111011 2 = 3B 16 . •

Its least significant byte is at address 00006 16 and equals 01001100 2 = 4C 16 .

•

Combining these two values, we get the segment-base address, which equal 0011101101001100 2 = 3B4C 16 .

•

The offset part of the pointer is the lower address word. Its least significant byte is stored at address 00004 16 ; this location contains 01100101 2 = 65 16 .

•

The most significant byte is at address 00005 16 , which contains 00000000 2 = 00 16 .

•

The resulting offset is 0000000001100101 2 = 0065 16 . The complete double word is 3B4C0065 16 . Since this double word starts at address 00004 16 . It is an example of an aligned double word of data.

Address

Memory (binary)

Memory (hexadecimal)

00007 16

0011 1011

3B

00006 16

0100 1100

4C

00005 16

0000 0000

00

00004 16

0110 0101

65

Figure 2.2.1f Storing a 32-bit pointer in memory. EXAMPLE 2.2.1B How should the pointer with segment base address equal to A000 16 and offset address 55FF 16 be stored at an even-address boundary starting at 00008 16 ? Is the double word aligned or misaligned?

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SOFTWARE ARCHITECTURE OF THE 8088 AND 8086 MICROPROCESSOR

Solution :

Storage of the two-word pointer requires four consecutive byte locations in memory, starting at address 00008 16 . •

the least significant byte of the offset is stored at address 00008 16 and is shown as FF 16 in figure 2.2.1g

•

The most significant byte of the offset, 55 16 , is stored at address 00009 16 . These two bytes are followed by the least significant byte of the segment base address, 00 16 , at address 0000A 16 , and its most significant byte,A0 16 , at address 0000B 16 . Since the double word is stored in memory starting at address 00008 16 , it is aligned.

Address

Memory (binary)

0000B 16

A0

0000A 16

00

00009 16

55

00008 16

FF

Figure 2.2.1g

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SOFTWARE ARCHITECTURE OF THE 8088 AND 8086 MICROPROCESSOR

Exercise 2.2.1 1. What is the highest address in the 8088’s memory address space? The lowest address?

2. Is memory in the 8088 microcomputer organized as bytes, words, or double words?

3. The contents of memory location B000H are FFH and those at B0001H are 00H. What is the data word stored at address B000H? Is the word aligned or misaligned?

4. What is the value of the double word stored in memory starting at address B003H if the content of memory locations B0003H, B0004H, B0005H and B0006H are 11H, 22H, 33H, and 44H respectively? Is this an example of an aligned double word or a misaligned double word?

5. Show how the word ABCDH is stored in memory starting at address 0A002H. Is the word aligned or misaligned?

6. Show how the double word 12345678H will be stored in memory starting at address A001H. Is the double word aligned or misaligned.

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SOFTWARE ARCHITECTURE OF THE 8088 AND 8086 MICROPROCESSOR

2.2.2 Data Types

Integer data type: •

The 8088 can process data as either unsigned or signed integer numbers; each type of integer can be either byte – wide or word- wide.

Unsigned integer •

Figure 2.2.2a represents an unsigned byte integer ; this data type can used to represent decimal numbers in the range 0 through 255.

•

The unsigned word integer is shown in fig. 2.2b; it can be used to represent decimal numbers in the range 0 through 65,535. MSB

LSB

D7

D0

Figure 2.2.2a Unsigned byte integer MSB

LSB

D15

D0

Figure 2.2.2b Unsigned byte integer EXAMPLE 2.2.2A What decimal value does the unsigned word integer 1000 16 represent? Solution : First, the hexadecimal integer is converted to binary form 1000 16 = 0001000000000000 2 Next, find the value for the binary number 0001000000000000 2 = 212 = 2048

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SOFTWARE ARCHITECTURE OF THE 8088 AND 8086 MICROPROCESSOR

Signed integer : The signed byte integer and signed word integer of Figure 2.2.2c (i) and (ii) are similar to the unsigned integer data types . But here the most significant bit is a signed bit. •

A zero in this bit position identifies a positive number. For this reason, the signed integer byte can represent decimal numbers in range =127 to – 128, and the signed integer word permits numbers in the range =32,767 to –32,768.

•

For example, the number =3 expressed as a signed integer byte is 00000011 2 (03 16 ).

•

The 8088 always expresses negative numbers in 2’s-complement notation. Therefore, -3 is coded as 11111101 2 (FD 16 ) MSB

LSB

D7

D0

Sign bit MSB

LSB

D15

D0

Sign bit Figure 2.2.2c (i) Signed byte integer (ii) Signed word integer. EXAMPLE 2.2.2B A signed word integer equals FEFF 16 . What decimal number does it represent? Solution : Expressing the hexadecimal number in binary form, FEFF 16 = 1111111011111111 2 Since the most significant bit is 1, the number is negative and is in 2’s complement form. Converting to its binary equivalent by subtracting 1 from the least significant bit and then complementing all bits gives:

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SOFTWARE ARCHITECTURE OF THE 8088 AND 8086 MICROPROCESSOR

FEFF 16 = -0000000100000001 2 = -257

Binary-Coded Decimal (BCD) The 8088 can also process data that is coded as binary-coded decimal (BCD) numbers. •

Figure 2.2.2d lists the BCD values for decimal numbers 0 through 9.

•

BCD data can be stored in either unpacked or packed form.

Decimal 0 1 2 3 4 5 6 7 8 9

BCD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001

Figure 2.2.2c BCD numbers

Unpacked BCD digit A single BCD digit is stored in the four least significant bits, and the upper four bits are set to 0. MSB

LSB D0

D3 BCD digit

Figure 2.2.2d

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An unpacked BCD digit

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SOFTWARE ARCHITECTURE OF THE 8088 AND 8086 MICROPROCESSOR

Packed BCD digit Two BCD numbers are stored in a byte. The upper four bits represent the most significant digit of a two-digit BCD number :

MSB D7

D4

LSB D0

D3

BCD digit 1

BCD digit 0

Figure 2.2.2e A packed BCD digits EXAMPLE 2.2.2.C The packed BCD data stored at byte address 01000 16 equals 10010001 2 . What is the two- digit decimal number?

Solution :

Writing the value 10010001 2 as separate BCD digits gives : 10010001 2 = 1001 BCD 0001 BCD = 91 10

American Standard Code for Information Interchange (ASCII) Information expressed in ASCII ( American Standard Code for Information Interchange) can also be directly processed by the 8088 microprocessor. •

The chart in fig. 2.2.2f(i)

shows how numbers, letters, and control

characters are coded in ASCII. Ex; the number 5 is coded as H 1 H 0 = 0110101 2 = 35H Where H denotes that the ASCII-coded number is in Hexadecimal form. As shown in fig. 2.2.2f (ii) , ASCII Data are stored as one character per byte.

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SOFTWARE ARCHITECTURE OF THE 8088 AND 8086 MICROPROCESSOR

EXAMPLE 2.2.2.D Byte addresses 01100 16 through 01104 16 contain the ASCII data 01000001, 01010011, 01000011, 01001001, and 01001001, respectively. What do the data stand for? Solution : Using the chart in fig. 2.2.2f(i) the data are converted to ASCII as follows: (01100H) = 01000001 2 = A (01101H) = 01010011 2 = S (01102H) = 01000011 2 = C (01103H) = 01001001 2 = I (01104H) = 01001001 2 = I

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SOFTWARE ARCHITECTURE OF THE 8088 AND 8086 MICROPROCESSOR

B7 B6 B5 H1 b4 b3 b1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1

b2

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0

1

2

3

4

5

6

7

H2

0

0 0

NUL

DLE

SP

0

@

P

´

p

0

0 1

SOH

DC1

!

1

A

Q

a

q

0

1 2

STX

DC2

“

2

B

R

b

r

0

1 3

ETX

DC3

#

3

C

S

c

s

1

0 4

EOT

DC4

$

4

D

T

d

t

1

0 5

ENQ

NAK

%

5

E

U

e

u

1

1 6

ACK

SYN

&

6

F

V

f

v

1

1 7

BEL

ETB

‘

7

G

W

g

w

0

0 8

BS

CAN

(

8

H

X

h

x

0

0 9

HT

EM

)

9

I

Y

I

y

0

1 A

LF

SUB

*

:

J

Z

j

z

0

1 B

V

ESC

+

;

K

[

k

}

1

0 C

FF

FS

,

<

L

\

l

|

1

0 D

CR

GS

_

=

M

]

m

{

1

0 E

SO

RS

.

>

N

^

n

~

1

0 F

SI

US

/

?

O

-

o

DEL

Figure 2.2.2f (i) ASCII table MSB D7

LSB D0 ASCII Digit Figure 2.2.2f (ii) ASCII digit

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SOFTWARE ARCHITECTURE OF THE 8088 AND 8086 MICROPROCESSOR

Exercise 2.2.2 1. List five data types processed directly by the 8088.

2. Express each of the signed decimal integers that follow as either a byte or word hexadecimal number (Use 2’s complement notation for negative numbers)

a) +127 b) -10 c) -128 d) +500

3. How would the integer in problem 2(d) be stored in memory starting at address 0A000H?

4. How would the decimal number -1000 be expressed for processing by the 8088?

5. Express the decimal numbers that follow as unpacked and packed BCD bytes.

a) 29 b) 88

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SOFTWARE ARCHITECTURE OF THE 8088 AND 8086 MICROPROCESSOR

7. How would the BCD number in problem 5(a) be stored in memory starting at address 0B000H? (Assume that the least significant digit is stored at the lower address)

8. What is the statement coded in ASCII by the following binary strings?

1001110 1000101 1011000 1010100 0100000 1001001

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SOFTWARE ARCHITECTURE OF THE 8088 AND 8086 MICROPROCESSOR

2.3

REGISTERS AND MEMORY

2.3.1 Segment Registers And Memory Segmentation Even though the 8088 has a 1 Mbyte address space, not all this memory can be active at one time. •

The 1 Mbytes of memory can be partitioned into 64Kbyte (65,536) segments.

•

A segment represents an independently addressable unit of memory consisting of 64K consecutive byte-wide storage locations.Each segment is assigned a base address that identifies its starting point – that is, its lowest address bytestorage location.

•

•

Only four of the 64Kbyte segments can be active at a time : i.

Code segment

ii.

Stack segment

iii.

Data segment

iv.

Extra segment

The segments of memory that are active,are identified by the values of addresses held in the 8088’s four internal segment registers, as shown in fig.2.3.1a.

•

i.

CS (code segment)

ii.

SS (stack segment)

iii.

DS (data segment)

iv.

ES (extra segment)

Each of this registers contain a 16-bit base address that points to the lowest addressed byte of the segment in memory.

•

Four segments give a maximum of 256Kbytes of active memory, 64Kbytes are for code (program storage), 64Kbytes are for stack, and 128Kbytes are for data storage.

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SOFTWARE ARCHITECTURE OF THE 8088 AND 8086 MICROPROCESSOR

FFFFFH

Code segment CS

Stack segment

SS DS ES

Data segment

8088/8086

Extra segment

00000H

Figure 2.3.1a Active segments of memory. •

The values held in these registers are usually referred to as the current-segment register values; for example, the value in CS points to the first word wide storage location in the current code segment. Code is always fetched as words, not as bytes.

•

Figure 2.3.1b illustrates the segmentation of memory. In this diagram the 64Kbyte segments are identified with letters such as A, B, and C.

•

The data segment (DS) register contains the value B. Therefore, the second 64Kbyte segment of memory from the top, labeled B, acts as the current data – storage segment.

•

This is one of the segments in which data that are to be processed by the microcomputer are stored.

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SOFTWARE ARCHITECTURE OF THE 8088 AND 8086 MICROPROCESSOR

•

Part of the microcomputer’s memory address space must contain read/write storage locations that can be accessed by instructions as storage locations for source and destination operands.

•

Segment E is selected by CS as the code segment. In this segment of memory from which instructions of the program are currently being fetched for execution.

•

The stack segment (SS) register contains H, thereby selecting the 64Kbyte segment labeled as H for use as a stack.

•

Finally, the extra segment register ES is loaded with value J such that segment J of memory can function as a second 64Kbyte data-storage segment.

FFFFFH

A B DATA: DS:

B

CODE: CS:

E

STACK: SS:

H

EXTRA: ES:

J

C D E F G

J

H I

K

0000H

Figure 2.3.1b Contiguous, adjacent, disjointed, and overlapping segments. •

The segment registers are said to be user accessible. This mean that the programmer can change their contents for a program to gain access to another

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SOFTWARE ARCHITECTURE OF THE 8088 AND 8086 MICROPROCESSOR

part of memory, one just has to change the value of the appropriate register or registers. •

A new data space, with up to 128Kbytes, can be brought in simply by changing the values in DS and ES.

•

There is one restriction on the value that can be assigned to a segment as a base address; it must reside on a 16-byte address boundary. This is because increasing the 16 bit value in a segment register by 1 actually increases the corresponding memory address by 16. Example : 00000 16 , 00010 16 , 00020 16 and so on.

•

Other than this restriction, segments can be set up to be contiguous, adjacent, disjointed, or even overlapping. Example : In fig. 2.3.1b, segments A and B are contiguous, whereas segments B and C are overlapping

2.3.2 Dedicated, Reserved, And General- Use Memory Any part of the 8088 microcomputer’s 1Mbyte address space can be implemented for user’s access; however, some address locations have dedicated functions and should not be used as general memory for storage of data or instructions of a program. Let us now look at these reserved, dedicated use, and general use parts of memory.

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SOFTWARE ARCHITECTURE OF THE 8088 AND 8086 MICROPROCESSOR

•

Figure 2.3.2a shows the reserved, dedicated-use, and general-use parts of the 8088/8086 address space.

RESERVED

FFFFFH

DEDICATED

FFFFCH FFFFBH FFFF0H FFFEFH

~ ~

OPEN

~ ~

80H 7FH RESERVED

14H 13H

DEDICATED 0H Figure 2.3.2a Dedicated-use, reserved, and general-use memory.

Dedicated memory : •

Storage location from address 00000 16 to 00013 16 .

•

Used for storage of pointers for the 8088’s internal interrupts and exceptions.

Pointer = Two word address element and requires 4 bytes of memory •

This dedicated memory can contain up to 32 pointers.

Reserved memory : •

Storage location from address 00014 16 to 0007F 16 .

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SOFTWARE ARCHITECTURE OF THE 8088 AND 8086 MICROPROCESSOR

•

These 128 bytes of memory are used for storage of pointers to interrupt service routines.

•

Saved for storage of pointers that are used by the user-defined interrupts.

General-use memory:

•

Storage location from 00080 16 to FFFEF 16 .

•

Used to store data or instructions of the program.

At the high end of the memory address space is another reserved pointer area, located from address FFFFC 16 through FFFFF 16 . These four memory locations are reserved for use with future products and should not be used.

Intel Corporation, the manufacturer of the 8088 has identified the 12 storage locations from address FFFF0 16 through FFFFB 16 as dedicated for functions such as storage of the hardware reset jump instruction. For instance, physical address FFFF0 16 is where the 8088/8086 begins execution after receiving a reset.

2.3.3 Instruction Pointer (IP) •

16 bits in length and identifies the location of the next word of instruction code to be fetched from the current code segment of memory.

•

Contains the offset of the next word of instruction code instead of its actual address.This is because the IP and CS are both 16 bits in length, but 20-bit address is needed to access memory.

•

Internal to the 8088, the offset in IP is combined with the current value in CS to generate the address of the instruction code. Therefore, the value of the address for the next code access is often denoted as CS:IP.

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Normal Operation : •

The 8088 fetches instructions from the code segment of memory, stores them in its instruction queue, and executes them one after the other.

•

Every time an instruction is fetched from memory, the 8088 updates the value in IP such that it points to the first byte of the next sequential word of code.

•

I this way, it is always ready to fetch the next sequential instruction of the program; that is, IP is incremented by 2.

•

The 8088 prefetches up to four bytes of instruction code into its internal code queue and holds them there waiting for execution.

•

After an instruction is read from the output of the instruction queue, it is decoded; if necessary, operands are read from either the data segment of memory or internal registers.

•

The operation specified in the instruction is performed on the operands and the result is written back to either an internal registers or a storage location in memory.

•

The 8088 is now ready to execute the next instruction in the code queue.

•

The active code segment can be changed simply by executing an instruction that loads a new value into the CS register; thus, we can use any 64Kbyte segment of memory for storage of instruction code.

2.3.4 Data Registers •

There are four general-purpose data registers located within the 8088 processor.

•

During program execution, they are used for temporary storage of frequently used intermediate results.

•

Their contents can be read, loaded, or modified through software. Any of the general-purpose data registers can be used as the source or destination of an operand during an arithmetic operation such as ADD, or logic operation such as AND.

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•

The values of two pieces of data, A and B, could be moved from memory into separate data registers and operations such as addition, subtraction, and multiplication performed on them. The advantage of storing these data in internal registers instead of memory during processing is that they can be accessed much faster.

•

The four registers, known as the data registers, are shown in more detail in fig 2.3.4a

H D15

D8 D7

D0 Accumul ator

AX AH

Register Operation AX Word multiply, word divide, word I/O

L

Base

BL

CX CH

Count CL

BX

Byte multiply, byte divide

CX

Translate

CL

String Operations,loops

DX

Variable shift and rotate Word multiply, word divide, indirect I/O

DL (a) Figure 2.3.4

(b) (a) General purpose data registers. (b) Dedicated registers functions.

•

Notice that they are refered to as : 1. Accumulator register (A) 2. Base register (B) 3. Count register (C) 4. Data register (D)

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DX DH

AH

Byte multiply, divide,byte I/O,translate,decimal arithmetic

AL

BX BH

AL

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SOFTWARE ARCHITECTURE OF THE 8088 AND 8086 MICROPROCESSOR

•

These names imply special functions they are meant to perform in the 8088 microprocessor.

•

Fig. 2.3.4b summarizes these operations.

Notice that the C register is used during string and loop operations. Example: The value in the C register is the number of bytes to be processed in a string operation. This is the reason it is given the name count register. •

Another example of the dedicated use of data registers is that all input/output operations must use accumulator register AL or AX for data.

•

Each of these registers can be accessed either as a whole (16 Bits) for word data operations or as two 8 bit registers for a byte-wide data operations.

•

References to a register as a word are identified by an X after the register letter; for instance, the 16-bit accumulator is referenced as AX. Similarly, the other three word registers are referred to as BX, CX, and DX.

•

When referencing one of these registers an a byte-wide basis, the high byte and low byte are identified by following the register name with the letter H or L, respectively. For the A register, the most significant byte is referred to as AH and the least significant byte as AL; the other byte-wide register pairs are BH and BL,CH and CH and CL, and DH and DL.

•

Actually, some of the data registers can also be used to store address information such as a base address or input/output address.Ex. BX could hold a 16 bit base address.

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2.3.5 Pointer And Index Registers •

There are four other general purpose register : two pointer registers and two index registers.

•

They are used to store what are called offset addresses. An offset address represents the displacement of a storage location in memory from the segment base address in a segment register.

•

They are used as a pointer or index to select a specific storage location within a 64 Kbyte segment of memory.

•

Values in index registers are used to reference data relative to the data segment or extra segment register.

•

Values in Pointer registers are used to store offset addresses of memory location relative to the stack segment register.

•

The values in these registers can be read, loaded, or modified through software.

•

To use the offset address in a register, the instruction simply specifies the register that contains the value of the offset address.

• D15

D0

SP

Stack Pointer

BP

Base Pointer

SI

Source index

DI

Destination Index

Figure 2.3.5 Pointer and Index registers

•

Figure 2.3.5 shows that the two pointer registers are the stack pointer (SP) and base pointer (BP). The values in SP and BP are used as offsets from the current value of SS during the execution of instructions that involves the stack segment

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of memory and permits easy access to storage locations in the stack part of memory. •

During the execution of instructions that involves SP and BP as a base address, the value in the base register is automatically combined with the contents of the stack segment register to produce the memory address.

•

The value in SP always represents the offset of the next stack location that is to be accessed. That is, combining SP with the value in SS(SS:SP) results in a 20bit address that points to the top of the stack(TOS).

•

BP also represents an offset relative to the SS register. It is used to access data within the stack segment of memory. To do this, it is employed as the offset in an addressing mode called the based addressing mode.

•

One common use of BP is to reference parameters that were passed to a subroutine by way of the stack. In this case, instructions are included in the subroutine that use based addressing to read the values of parameters from the stack.

•

The index register are used to hold offset addresses for instructions that access data stored in the data segment of memory and are automatically combined with the value in the DS or ES register during address calculation.

•

The source index (SI) register is used to hold an offset that identifies the location of a destination operand.

•

The destination index(DI) registers holds an offset that identifies the location of a destination operand.

•

The index registers can also be uses as source or destination registers in arithmetic and logical operations. These registers must always be used for 16-bit operations and cannot be accessed as two separate bytes.

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2.3.6 Status Register Status register, also called the flag register, is another 16-bit register within the 8088. This register is shown in more detail in fig. 2.3.6. Notice that just nine of its bits are implemented. Six of these bits represent status flags : 1.

Carry flag (CF)

2.

Parity flag (PF)

3.

Auxiliary Carry flag (AF)

4.

Zero flag (ZF)

5.

Sign flag (SF)

6.

Overflow flag (OF) •

The logic state of these status flags indicate conditions that are produced as the result of executing an instruction.

•

After executing an instruction, such as ADD, specific flag bits are reset (logic 0) or set (logic 1) based on the result that is produced.

Control flag TF

DF

Status flag IF

OF

SF

ZF

AF

PF

CF

CARRY

PARITY AUXILIARY CARRY ZERO SIGN OVERFLOW INTERRUPT-ENABLE DIRECTION TRAP Figure 2.3.6 Status and control flags.

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The Operation of Flags: 1.

The carry flag: CF is set if there is a carry out or borrow- in for the most significant bit of the result during the execution of an arithmetic instruction. Otherwise, CF is reset.

2.

The parity flag: PF is set if the result produced by the instruction has an even parity- that is, if it contains an even number of bits at the 1 logic level. If parity is odd, PF is reset.

3.

The auxiliary carry flag: AF is set if there is a carry-out from the low nibble into the high nibble or a borrow-in from the high nibble into the low nibble of the lower byte in a 16 bit word. Otherwise AF is reset.

4.

The zero flag: ZF is set if the result of an arithmetic or logic operation is zero. Otherwise, ZF is reset.

5.

The sign flag: The MSB of the result is copied into SF. Thus SF is set if the result is a negative number or reset if it is positive.

6.

The overflow flag: When OF is set, it indicates that the signed result is out of range. If the result is not out of range, OF remains reset.

The other three implemented flag bits- direction flag (DF), interrupt enable flag (IF), and trap flag (TF)- are control flags. These three flags are provided to control functions of the 8088 as follows:

1.

The trap flag (TF): If the TF is set, the 8088 goes into the single-step mode of operation. When in the single step mode, it executes an instruction and then jumps to a special service routine to determine the effect of executing the instruction. This type of operation is very useful for debugging programs.

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2.

The interrupt flag (IF): For the 8088 to recognize maskable interrupt request at its INT input, the IF flag must be set. When IF is reset, requests at INT are ignored and the maskable interrupt interface is disabled.

3.

The direction flag (DF): The logic level of DF determines the direction in which string operations will occur. When set, the string instruction automatically decrements the address; therefore, the string data transfers proceed from high address to low address. On the other hand, resetting DF causes the string address to be incremented, that is data transfers proceed from low address to high address. •

The instruction set of the 8088 includes instructions for saving, loading, or manipulating the flags.

•

Special instructions are provided to permit user software to set or reset CF, DF, and IF at any point in the program.

2.3.7 Generating a memory address •

A logical address in the 8088 microcomputer is described by a segment base and an offset.

•

Both the segment base and offset are 16-bit quantities since all registers and memory locations used in address calculations are 16 bits long as shown in fig. 2.3.7a. OFFSET VALUE

0 SEGMENT REGISTER 0

0000

ADDER

20 – BIT PHYSICAL MEMORY ADDRESS Figure . 2.3.7a.

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• •

The physical addresses that are used to access memory are 20 bits in length. The generation of the physical address involves combining a 16-bit offset value that is located in the instruction pointer, a base register, an index register, or a pointer register and a 16 bit segment base value that is located in one of the segment registers.

Physical Memory Address = Segment Base value + Offset value •

Source of offset value depends on which type of memory reference is taking place.

•

The segment base value always resides in one of the segment registers : CS,DS,SS and ES.

Instruction acquisition : •

Source of the Segment base value always the Code Segment(CS)

•

Source of the Offset value is always the Instruction Pointer(IP)

•

Physical address can be denoted as CS:IP

Execution of an instruction : •

The Segment base value will be specified by the Data Segment (DS).

•

The Offset value will be in the Destination Index (DI).

•

The physical address is given as DS:DI

A provision in the processor called the segment override prefix can be used to change the segment from which the variable is accessed. Ex :

A prefix could be used to make a data access occur in which the segment base

is in the ES register.

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Pushing parameters onto the stack : •

The Segment base value will be in the Stack Segment(SS)

•

The Offset value will be in the Stack Pointer(SP)

•

The physical address is given as SS:SP

Segment Base Address •

The starting location of the 64Kbyte segment in memory.

•

The lowest address byte in the segment.

•

Figure 2.3.7b shows that the Offset identifies the distance in byte that the storage location of interest resides from this starting address.

•

The lowest address byte in a segment has an Offset of 0000H and the highest address byte has an Offset of FFFH.

Figure 2.3.7b Boundaries of a segment

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Figure 2.3.7c shows how a segment base value in segment register and an offset value are combined to form a physical address.

Shift left 4 bits 15 1 2 3 4

19

0

1

2

3

4

0 15

0

2

2

SEGMENT 0 BASE

LOGICAL ADDRESS

0 OFFSET 0

0 0 2 2 15

19

1

0

2 3 6

2

0 PHYSICAL ADDRESS

TO MEMORY Figure 2.3.7c Physical address calculation example.

Segment base value 1234H = 0001001000110100 2 1. The value in the segment register is shifted left by four bit position, with LSBs filled with zeros. This gives the segment address the location where the segment starts.

00010010001101000000 2 = 12340H Offset value

0022H = 0000000000100010 2

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2. The Offset value then added to the 16 LSBs of the shifted segment value.

00010010001101000000 2 + 0000000000100010 2 = 00010010001101100010 = 12362H 3. The result of this addition is the 20 bit physical address. •

This address calculation is done automatically within the 8088 microprocessor each time a memory access is initiated.

Try This :

1. What would be the offset required to map to physical address location 002C3H if the contents of the corresponding segment register are 002AH?

2. Calculate the value of each of the physical addresses that follows.Assume all numbers as hexadecimal numbers.

a. 1000:1234 b. 0100:ABCD c. A200:12CF d. B2C0:FA12

3. Find the unknown value for each of the following physical addresses. Assume all numbers as hexadecimal numbers.

a. A000: ? = A0123 b. ? :14DA = 235DA c. D765: ? = DABC0 d. ? :CD21 = 32D21

4. If the current values in the code segment register and the instruction pointer are 0200H and 01ACH,respectively, what physical address is used in the next instruction fetch?.

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5. A data segment is to be located from address A0000H to AFFFFH, what value must be loaded into DS?

PHYSICAL ADDRESS OFFSET(3H)

LOGICAL ADDRESS OFFSET (13H)

SEGMENT BASE

2C4H 2C3H 2C2H 2C1H 2C0H 2BFH 2BEH 2BDH 2BCH 2BBH 2BAH 2B9H 2B8H 2B7H 2B6H 2B5H 2B4H 2B3H 2B2H 2B1H 2B0H

Figure 2.3.7d Relationship between logical and physical addresses.

•

Actually, many different logical address can be mapped to the same physical address location in memory. This is done by changing the segment value in the segment register and its corresponding offset.

•

The diagram in figure 2.3.7d demonstrates this idea.

•

Notice that segment base 002BH with the offset 0013H maps to physical address 002C3H in memory. However, if the segment base is changed to 002CH with the new offset of 0003H the physical address is still 002C3H. The physical address 002BH:0013H is equal to the physical address 002CH:0003H.

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2.3.8 The Stack

The stack is implemented in memory of the 8088 microcomputer and used for temporary storage of information such as data or addresses. •

When a call instruction is executed the 8088 automatically pushes the current values in CS and IP onto the stack..

•

The contents of other register can also be saved on the stack by executing PUSH instructions.

Ex : When the instruction PUSH SI is executed, it causes the contents of SI to be pushed onto the stack. •

POP instruction can be included to pop values from the stack back into their corresponding internal registers.

Ex : POP SI causes the value at the top of the stack to be popped back into SI. •

A RETURN instruction causes the values of CS and IP to be popped off the stack and be put back into the same internal register where they originally resided.

•

The stack is 64Kbytes long = 32Kwords.

•

Figure 2.3.8a shows the lowest address word in the current stack is pointed to by the segment base value in the SS register.

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Memory (wordwide) SS:FFFEH

. . .

8088/8086 SP

SS:SP

. Stack Segment . . .

SS

SS:0000H

Bottom of stack

Top of stack

End of stack

Figure 2.3.8a Stack segment of memory.

•

The content of the SP and BP registers are used as offsets into stack segment of memory.

•

SP- Contains an offset value that points to a storage location in the current stack segment.

•

The address obtained from the contents of SS and SP (SS:SP) is the physical address of the last storage location in the stack to which data were pushed. This memory address is known as the top of the stack (TOS).

•

At the microcomputer start up, the value in SP is FFFEH, combining this value with the current value in SS gives the highest address word location in the stack (SS:FFFEH) that is the bottom of the stack.(BOS).

•

The 8088 can push data and address information onto the stack from it’s internal registers or a storage location in memory.

•

Data transferred to and from the stack are word wide.

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PUSH : •

Each time a word is to be pushed onto the top of stack, the value in SP is first automatically decrement by two and then the content of the register are written into the stack part of memory.

•

The stack grows down in memory from the bottom of stack (SS:FFFEH) toward the end of stack (SS:0000H).

POP : •

When the value is popped from the top of the stack the reverse of this sequence occurs.

•

The physical address defined by SS and SP points to the location of the last value pushed onto the stack.

•

It’s content are first popped off the stack and put into the spesific register within the 8088.

•

SP is automatically increment by two. The top of the stack then corresponds to the address of the previous value pushed onto the stack..

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EXAMPLE: Execution of the PUSH AX instruction

Figure 2.3.8b Stack just prior to push operation. •

Stack segment(SS) contains 105H. As indicated, the bottom of stack resides at the physical address derived from SS and offset FFFEH. This give the bottom of the stack address, ABOS as :

A BOS = 1050H + FFFEH = 1104EH •

The stack pointer which represents theoffset from the beginning of the stack specified by the contents of SS to the top of the stack, equals 0008H. Therefore the current top of the stack is at the physical address A TOS which equal :

A TOS = 1050H + 0008H = 1058H •

Addresses with higher values than that top of the stack 1058H contain valid stack data.

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•

Addresses lower than that top of the stack not yet contain valid stack data. The last value pushed to the stack in figure 2.3.8b is BBAAH.

•

Figure 2.3.8c demonstrates what happens when the PUSH AX instruction is executed.

Figure 2.3.8c Stack after execution of the PUSH AX instruction.

•

AX contains the number 1234H.

•

The execution of the PUSH instruction causes the stack pointer to be decremented by two but does not affect the contents of the stack segment register.

•

The next location to be accessed in the stack corresponds to address 1056H. It is to this location that the value in AX is pushed.

•

Notice that the MSB of AX, 12H now resides in memory address 1057H and LSB byte of AX, 34H is held in memory address 1056H.

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EXAMPLE Stack data are popped from the stack back into register from which they were pushed. •

In figure 2.3.8c The stack is shown to be in the state that resulted due to PUSH AX example, that is SP = 0006H, SS = 105H, the address at the top of the stack = 1056H and the word at the top of the stack = 1234H.

Figure 2.3.8d Instruction POP AX and POP BX are executed •

Execution of the first instruction causes the 8088 to read the value from the top of the stack and put it into the AX register as 1234H

•

SP is incremented by two to give 0008H and another read operation is initiated from the stack. This second read corresponds to the POP BX instruction and it causes the value BBAAH to be loaded into BX register. SP is increment once more and now equals 000AH. Therefore the new top of the the stack is at address 105AH.

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•

Notice that the value that read out of 1056H and 1058H remain at these addresses but now reside at location that are above the top of the stack, therefore they no longer represent valid stack data. If new data are pushed to the stack these values are written over.

•

Any number of stacks may exist in an 8088 microcomputer. A new stack can be brought in by simply changing the value in the SS register. Executing the instruction MOV SS,DX loads a new value from DS into SS. Although many stacks can exist, only one can be active at a time.

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Exercise 2.3 1. How large is a memory segment in the 8088 microcomputer?

2. What register defines the beginning of the current code segment in memory?

3. How much of the 8088’s active memory is available as general-purpose data storage memory?

4. What is the address range of the general use part of the memory address space?

5. What is stored at address FFFF0H?

6. Provide an overview of the fetch and the execution of an instruction by the 8088.

7. Make a list of general-purpose data registers of the 8088

8. How are the upper and lower bytes of a data register denoted?

9.

What kind of information is stored in the pointer and index register?

10. For which segment register are the contents of the pointer registers used as an offset?

11. What do SI and DI stand for?

12. Categorize each flag bit of the 8088 as either a control flag or a flag that monitors the status due to execution of an instruction.

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13. Describe the function of each status flag

14. How are the status flags used by software?

15. What does TF stand for?

16. Which flag determines whether the address for a string operation is incremented or decremented.? 17. What is the word length of the 8088’s physical address?

18. What two address elements are combined to form a physical address?

19. Calculate the value of each of the physical addresses that follows. Assume all numbers as hexadecimal numbers.

a) 1000:1234 b) 0100:ABCD c) A200:12CF d) B2C0:FA12

20. If the current values in the code segment register and the instruction pointer are 0200H and 01ACH respectively, what physical address is used in the next instruction fetch?

21. If the data segment register contains the value found in problem 6, what value must be loaded into DI if it is to point to a destination operand stored in memory at address A1234H?

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22. If the current values in the stack segment register and stack pointer are C000H and FF00H,respectively, what is the address of the top of the stack?

23. Show how the value EE11H from register AX would be pushed onto the top of the stack as it exists in problem 22.

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2.4

INPUT/OUTPUT ADDRESS SPACE

•

The 8088 has separate memory and input/output (I/O) address space.

•

The I/O address space is the place where I/O interfaces, such as printer and terminal ports, are implemented.

•

Figure 2.4 shows a map of 8088’s I/O address space. Notice that this address range is from 0000H to FFFFH. This represents just 64Kbyte addresses; therefore, unlike memory, I/O addresses are only 16 bits long. Each of these addresses corresponds to one byte-wide I/O port.

~ ~

~FFFFH ~ OPEN 100H FFH F8H F7H

RESERVED

PAGE 0

OPEN 0000H

Figure 2.4 I/O address space •

The part of the map from address 0000H through 00FFH is referred to as page 0.

•

Certain of the 8088’s I/O instructions can perform only input or output datatransfer operations to I/O device located in this part of the I/O address space.

•

Other I/O instructions can input or output data for devices located anywhere in the I/O address space.

•

I/O data transfers can be byte-wide or word-wide. Notice that the eight locations from address 00F8H through 00FFH are specified as reserved by Intel Corporation and should not be used.

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Exercise 2.4 1. For the 8088 microprocessors, are the input/output and memory address common or separate?

2. How large is the 8088’s I/O address?

3. What is the name given to the part of the I/O address space from address 0000H through 00FFH?

SUMMARY In this unit we have studied : 1. The software architecture of the 8088 and 8086 microprocessor in detail. 2. There are two processing units, each unit has dedicated functions and both operate at the same time. This parallel processing effectively makes the fetch and execution of instructions independent operations. The processing units are : i.The bus interface unit (BIU) ii.The execution unit (EU) 3. The software architecture of the 8088/8086 microprocessors includes 13 16-bit internal registers. 4. How information such as numbers, characters, and instructions are stored in memory.

5. Segment Registers and Memory Segmentation 6. The 8088 has separate memory and input/output (I/O) address space. The I/O address space is the place where I/O interfaces, such as printer and terminal ports, are implemented.

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ANSWERS Exercise 2.1 1.

Bus Interface Unit ( BIU ) and Execution Unit ( EU )

2.

Bus Interface Unit ( BIU )

3.

20 bit , 16 bit

4.

4 byte for 8088 , 6 byte for 8086.

5.

General register , operand , ALU , and flag.

6.

The purpose of a software model for microprocessor is to aid the programmer in understanding the operation of the microcomputer system from a software point of view.

7.

The purpose , function , operating capabilities and limitations.

8.

13 – 16 bit register

9.

1,048,576 ( 1M) bytes

10.

65,536 bytes ( 64 k ) bytes

Exercise 2.2.1 1.

FFFFF H , 00000 H

2.

8 bit bytes

3.

Address

Memory (Hexadecimal)

0B001 16

00

0B000 16

FF

The data word is 00FF H. The word is aligned. 4.

The double word is 44332211 H . The double word is misaligned.

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5.

Address

Memory (Hexadecimal)

0A003 16

AB

0A002 16

CD

The LSB of the lower address is 0A002 H, so the word is aligned. 6. Address

Memory (Hexadecimal) 12

A0013 16 A0012 16

34

A0011 16

56

A0010 16

78

The LSB of the lower address is A0010 H , so the double word is aligned.

Exercise 2.2.2 1.

Unsigned integer , signed integer , unpacked BCD , packed BCD and ASCII.

2.

a) + 127 = 01111111B = 7F H b) – 10 , using + 10 = 00001010B =

11110101B

=+

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=

11110110B

=

F6 H

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SOFTWARE ARCHITECTURE OF THE 8088 AND 8086 MICROPROCESSOR

c) – 128 , using + 128 = 10000000 B = 01111111

1s comp

=+

2nd comp

1

=

10000000 B

=

80 H

d) + 500 = 111110100 B = 1F4 H

3.

4.

Address

Memory (Hexadecimal) 0A001 16

01

0A000 16

F4

-1000 , using = +1000 = 1111101000 B = 0000010111 B

1s comp

=+

2nd comp

1

= 0000011000 B = 018 H

5.

a) unpack : 00000010 B, 00001001 B Pack : 00101001 B b) unpack : 00001000 B, 00001000 B pack : 10001000 B

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6.

7.

Address

Memory (Binary)

0B001 16

00000010

0B000 16

00001001

NEXT 1

Exercise 2.3 1.

64 k bytes

2.

CS

3.

Up to 128 k bytes

4.

80 H through FFFEF H.

5.

Control transfer to the reset power – up initialization software routine.

6.

The instruction is fetched from memory , decode within the 8088 , operand are read from memory or internal register , the operation specified by the instruction is perform on the data ; and the result are written back to either memory or an internal register.

7.

Accumulator ( AX ) , Base ( BX ) , Count ( CX ) and Data ( DX ).

8.

DH and DL

9.

Offset address of a memory location relative to a segment base address.

10.

SS

11.

Source Index register ; Destination Index register

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12.

13.

Flag

Type

CF

Status

PF

Status

AF

Status

ZF

Status

SF

Status

OF

Status

TF

Control

IF

Control

DF

Control

The function of each status flag 1.

The carry flag: CF is set if there is a carry out or borrow- in for the most significant bit of the result during the execution of an arithmetic instruction. Otherwise, CF is reset.

2.

The parity flag: PF is set if the result produced by the instruction has an even parity- that is, if it contains an even number of bits at the 1 logic level. If parity is odd, PF is reset.

3.

The auxiliary carry flag: AF is set if there is a carry-out from the low nibble into the high nibble or a borrow-in from the high nibble into the low nibble of the lower byte in a 16 bit word. Otherwise AF is reset.

4.

The zero flag: ZF is set if the result of an arithmetic or logic operation is zero. Otherwise, ZF is reset.

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5.

The sign flag: The MSB of the result is copied into SF. Thus SF is set if the result is a negative number or reset if it is positive.

6.

The overflow flag: When OF is set, it indicates that the signed result is out of range. If the result is not out of range, OF remains reset.

14.

Instruction can be used to test the state of these flags and based on their setting, modify the sequence in which instructions of the program are executed.

15.

Trap Flag

16.

DF

17.

20 bit

18.

Offset value and Segment register

19.

a) 11234 H b) 0BBCD H c) A32CF H d) C2612 H

20.

021AC H

21.

1234 H

22.

CFF00 H

23.

FEFE H – (SP) ( AH ) = EE H – CFEFF H ( AL ) = 11 H – CFEFE H

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Exercise 2.4 1.

Yes

2.

64 k bytes

3.

Page 0

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