02-General Purpose Processors

Chapter 3 General-Purpose Processors

1

Introduction •

General-Purpose Processor ▫

▫

Processor designed for a variety of computation tasks Low unit cost, in part because manufacturer spreads !" over large numbers of units 

▫

Carefully designed since higher !" is acceptable 

▫

Can yield good performance, si)e and power

Low !" cost, short time-to-market*prototype, high +eibility 

▫

#otorola sold half a billion $%&C'( microcontrollers microcontrollers in 1996 alone

ser .ust writes software/ software/ no processor design

a0k0a0 1microprocessor2  1micro2 used when they were implemented on one or a few chips rather than entire rooms 2

Introduction •

General-Purpose Processor ▫

▫

Processor designed for a variety of computation tasks Low unit cost, in part because manufacturer spreads !" over large numbers of units 

▫

Carefully designed since higher !" is acceptable 

▫

Can yield good performance, si)e and power

Low !" cost, short time-to-market*prototype, high +eibility 

▫

#otorola sold half a billion $%&C'( microcontrollers microcontrollers in 1996 alone

ser .ust writes software/ software/ no processor design

a0k0a0 1microprocessor2  1micro2 used when they were implemented on one or a few chips rather than entire rooms 2

4asic 5rchitecture •

Processor

Control unit and datapath0

Control unit

Datapath

ALU Controller 

•

•

Control /Status

6atapath is general0 Control unit doesn7t store the algorithm  the algorithm is 1programmed2 into the memory

Registers

PC

IR 

I/O Memory

3

6atapath 8perations •

Load  –

Processor

!ead memory location into register

Control unit

Datapath

ALU

• ALU operation

Controller 

&1

Control /Status

 –  Input certain registers through ALU, store back in register 

Registers

• tore  –  !rite register to "e"or# location

1$ PC

11

IR 

I/O Memory

%%% 1$ 11

%%% 4

Control nit •

Control unit9 con:gures the datapath operations  –

•

Processor Control unit

;e stored in memory  1program2

Datapath

ALU Controller 

Control /Status

Instruction cycle  broken into several sub-operations, each one clock cycle, e0g09  –

 –

 –

 –

 –

?etch9 Get net instruction into I! 6ecode9 6etermine what the instruction means ?etch operands9 #ove data from memory to datapath register "ecute9 #ove data through the 5L ;tore results9 @rite data from register to memory

Registers

PC

IR 

 R0

I/O   100 loa( R$, )*'$$+

101

inc R1, R$

102 store )*'$1+, R1

Memory

500 501

R1

%%% 1$

%%% '

Control nit ;ub-8perations •

?etch  –

 –

 –

Processor Control unit

Get net instruction into I! PC9 program counter, always points to net instruction I!9 holds the fetched instruction

Datapath

ALU Controller 

Control /Status

Registers

PC

100

IR  loa( R$, )*'$$+

 R0

I/O   100 loa( R$, )*'$$+

101

inc R1, R$

102 store )*'$1+, R1

Memory

500 501

R1

%%% 1$

%%% 

Control nit ;ub-8perations •

6ecode  –

Processor Control unit

6etermine what the instruction means

Datapath

ALU Controller 

Control /Status

Registers

PC

100

IR  loa( R$, )*'$$+

 R0

I/O   100 loa( R$, )*'$$+

101

inc R1, R$

102 store )*'$1+, R1

Memory

500 501

R1

%%% 1$

%%% -

Control nit ;ub-8perations •

?etch operands  –

#ove data from memory to datapath register

Processor Control unit

Datapath

ALU Controller 

Control /Status

Registers

1$ PC

100

IR  loa( R$, )*'$$+

 R0

I/O   100 loa( R$, )*'$$+

101

inc R1, R$

102 store )*'$1+, R1

Memory

500 501

R1

%%% 1$

%%% .

Control nit ;ub-8perations •

"ecute #ove data through the 5L  Ahis particular instruction does nothing during this sub-operation

Processor Control unit

Datapath

 –

ALU Controller 

Control /Status

Registers

 –

1$ PC

100

IR  loa( R$, )*'$$+

 R0

I/O   100 loa( R$, )*'$$+

101

inc R1, R$

102 store )*'$1+, R1

Memory

500 501

R1

%%% 1$

%%% /

Control nit ;ub-8perations •

;tore results @rite data from register to memory  Ahis particular instruction does nothing during this sub-operation

Processor Control unit

Datapath

 –

ALU Controller 

Control /Status

Registers

 –

1$ PC

100

IR  loa( R$, )*'$$+

 R0

I/O   100 loa( R$, )*'$$+

101

inc R1, R$

102 store )*'$1+, R1

Memory

500 501

R1

%%% 1$

%%% 1$

Instruction Cycles PC01$$ etch eco(e

Processor

etch ops

ec%

tore results

Control unit

Datapath

ALU clk 

Controller 

Control /Status

Registers

1$ PC 100

IR  loa( R$, )*'$$+

 R0

I/O   100 loa( R$, )*'$$+

101

inc R1, R$

102 store )*'$1+, R1

Memory

500 501

R1

%%% 1$

%%% 11

Instruction Cycles PC01$$ etch eco(e

Processor

etch ops

ec%

tore results

Control unit

Datapath

ALU clk 

PC01$1 etch eco(e

Controller 

etch ops

ec%

&1

Control /Status

Registers

tore results

clk 

1$ PC 101

IR  inc R1, R$

 R0

I/O   100 loa( R$, )*'$$+

101

inc R1, R$

102 store )*'$1+, R1

Memory

500 501

11 R1

%%% 1$

%%% 12

Instruction Cycles PC01$$ etch eco(e

Processor

etch ops

ec%

tore results

Control unit

Datapath

ALU clk 

PC01$1 etch eco(e

Controller 

etch ops

ec%

Control /Status

Registers

tore results

clk 

1$ PC 102

PC01$2 etch eco(e clk 

etch ops

ec%

IR  store )*'$1+, R1

tore results

 R0

I/O   100 loa( R$, )*'$$+

101

inc R1, R$

102 store )*'$1+, R1

Memory

11 R1

%%%

1$ 501 11 500

%%% 13

5rchitectural Considerations •

N-bit  processor ▫

▫

▫

•

-bit 5L, registers, buses, memory data interface "mbedded9 %-bit, B$-bit, 3-bit common 6esktop*servers9 3-bit, even $D

PC si)e determines address space

Processor Control unit

Datapath

ALU Controller 

Control /Status

Registers

PC

IR 

I/O Memory

14

5rchitectural Considerations •

Clock fre

&ow communicate with eternal signalsN

Interrupts 2

;oftware 6evelopment Process •

C ile

C ile

Co"piler  Ginar# ile

Ginar# ile

 –

As"% ile

Ginar# ile

Librar# ec% ile

ebugger 

Pro9 data is present, but not in huge amounts e0g0, EC!, disk drive, digital camera =assuming ;PP for image compression>, washing machine, microwave oven

#icrocontroller features  –

8n-chip peripherals •

•

 –  –  –

 Aimers, analog-digital converters, serial communication, etc0  Aightly integrated for programmer, typically part of register space

8n-chip program and data memory 6irect programmer access to many of the chip7s pins ;peciali)ed instructions for bit-manipulation and other low-level operations 3$

5nother Common 5;IP9 6igital ;ignal Processors =6;P> •

?or signal processing applications  –

 –  –

•

Large amounts of digiti)ed data, often streaming 6ata transformations must be applied fast e0g0, cell-phone voice :lter, digital AE, music synthesi)er

6;P features  –  –

 –

;everal instruction eecution units #ultiple-accumulate single-cycle instruction, other instrs0 "Ocient vector operations  e0g0, add two arrays •

Eector 5Ls, loop buKers, etc0 31

 Arend9 "ven #ore Customi)ed 5;IPs •

•

In the past, microprocessors were ac 32

;electing a #icroprocessor •

Issues  –  –

•

 Aechnical9 speed, power, si)e, cost 8ther9 development environment, prior epertise, licensing, etc0

;peed9 how evaluate a processor7s speedN  –  –  –

Clock speed  but instructions per cycle may diKer Instructions per second  but work per instr0 may diKer 6hrystone9 ;ynthetic benchmark, developed in B%D0 6hrystones*sec0 •

#IP;9 B #IP;  BJ(J 6hrystones per second =based on 6igital7s E5Q BB*J%'>0 50k0a0 6hrystone #IP;0 Commonly used today0  –

 –  –

;o, J(' #IP;  J('HBJ(J  B,3BJ,J(' 6hrystones per second

;P"C9 set of more realistic benchmarks, but oriented to desktops ""#4C  "6 "mbedded 4enchmark Consortium, www0eembc0org •

;uites of benchmarks9 automotive, consumer electronics, networking, oOce automation, telecommunications

33

General Purpose Processors Processor

Clock spee(

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Intel .$'1 )otorola .9C.11

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4K R;), 12. RA), 32 I?;, 6i"er, UAR6 4K R;), 1/2 RA), 32 I?;, 6i"er, !6, PI

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34

6esigning a General Purpose Processor

 F"'

•

ot something an embedded system designer normally would do  –

 –

eclarationsF bit PC*1+, IR*1+= bit )*4k+*1+, R*1+*1+=

#uch more optimi)ed, AliasesF much more bottom-up   op IR*1'%%12+   rn IR*11%%.+ design r" IR*-%%4+

PC0$=

etch

IR0)*PC+= PC0PC&1

eco(e

 $ro! states ,elo#

)o:1 op 0 $$$$

4ut instructive to see how simply we can build one top down !emember that real processors aren7t usually built this way •

Reset

$$$1

$$1$

$$11

$1$$

$1$1

(ir IR*-%%$+ i"" IR*-%%$+ rel IR*-%%$+

$11$

R*rn+ 0 )*(ir+ to Fetch

)o:2

)*(ir+ 0 R*rn+ to Fetch

)o:3

)*rn+ 0 R*r"+ to Fetch

)o:4

R*rn+0 i"" to Fetch

A((

R*rn+ 0R*rn+&R*r"+ to Fetch

ub

R*rn+ 0 R*rn+5R*r"+ to Fetch

BJ

PC07R*rn+0$8 Orel FPC to Fetch

3'

5rchitecture of a ;imple #icroprocessor •

;torage devices for each declared variable  –

•

•

register :le holds each of the variables

8ne 5L carries out every re